GB2102177A - AC plasma panel control - Google Patents

Abstract

In an AC plasma matrix panel, border sustain circuits needed for generating a constant supply of free particles are eliminated by the application of a 'distributed conditioning' waveform to all display cells, e.g. at 120 Hz, causing them to discharge without loss of memory of their ON/OFF state, which at other times is preserved by a sustain waveform. These waveforms, together with WRITE, ERASE and BULK ERASE are provided from ROM's addressed by logic signals. The first pulse 1 of the distributed conditioning waveform reverses wall charge only on a cell already ON, causing a flash; pulse II adds wall charge and fires only a cell already OFF, causing a flash at f and again at the pulse end at g: pulse III reverses wall charge on a cell originally ON, causing a second flash and leaving the cell ON. The flashes at 120 Hz are negligible against the 50 kHz flashing of ON cells. <IMAGE>

Description

SPECIFICATION AC plasma panel control The present invention is concerned with AC plasma panels.

AC plasma display panels are presently in commercial use as digitally addressable information display devices. The panel itself typically consists of two glass plates with a gas mixture sealed between them. A plurality of Xaxis electrodes extend in a mutually parallel array on an interior substrate of one plate, and a plurality of Y-axis electrodes extend in a mutually parallel array on the interior of the other plate. The X-axis electrodes are at a 900 angle to the Y-axis electrodes, thereby forming a plurality of intersections between the X-axis and Y-axis electrodes. A typically commercially available AC plasma panel has 512 X-axis electrodes and 512 Y-axis electrodes, yielding 262,144 intersections.

When a voltage of between 180 and 205 volts is applied across an X-axis electrode and a Y-axis electrode, a discharge in the gas occurs at the cell formed by the electrodes, causing a pulse of light to be emitted at this point. Simultaneously, a charge is collected on the cell wall, which results in the cell being an "on" cell. Once such a discharge has been produced and the cell is turned "on", the collected wall charge acts to continue the discharging when a lesser AC sustain voltage is applied between the electrodes.

In an "on" cell, the gas will discharge and the cell will emit a pulse of light at each transition of the applied AC sustain waveform. The sustain voltage, however, is insufficient to initiate a discharge at an X-Y intersection. This phenomenon is known as inherent memory, and was originally disclosed by Baker et al, in U.S.

Patent 3,499,167, and by Bitzer et al, in U.S.

Patent 3,959,1 90. By precisely timing, shaping, and phasing, multiple alternating voltage waveforms supplied to X and Y axes electrodes, the generation, sustaining and erasure of light emitting gas discharges at selected locations on the plasma display panel can be controlled.

Four functions are used to control the operation of an AC plasma panel: the write function, the erase function, the sustain function, and the bulk-erase function. The write function causes a selected cell on the panel to change from the "off", or non-light emitting state, to the "on" or light emitting state. The sustain function maintains the state of all cells on the panel, i.e., causes "on" cells to remain "on", and "off" cells to remain "off". The erase function causes a selected cell to be changed from the "on" state to the "off" state. The bulk-erase function causes all "on" cells in the panel simultaneously to be changed to the "off" state.

Operation of the write, erase, sustain, and buikerase functions is generally controlled by four logic signals: the X-sustain signal XS, the Ysustain signal YS, the X-address pulse XAP, and the Y-address pulse YAP. These signals, generally supplied by a waveform ROM (Read Only Memory), are digital pulse trains typically recurring at a frequency of 50 kHz. The logic signals are supplied to the sustain and drive circuits, and cause the circuits to execute the four control functions on the panel. Since the typical operational frequency of the plasma display system is 50 kHz, the complex waveform for each of the four control functions is executed in a 20 microsecond period.

Since these complex waveforms include several rising and falling edges in one 20 microsecond cycle, the time available to produce the initial discharge in the gas at the intersection between the electrodes is typically 3 to 5 microseconds. The discharge physics of a gas plasma display panel requires that there be sufficient free particles, such as electrons and ions, present in the gas mixture when the 180 to 200 volt potential is applied to a cell. These particles initiate an avalanche process causing the cell to be turned "on". If these particles are not present in sufficient quantity, the cell may not be turned "on" and the impression of the lesser AC sustain voltage between the electrodes forming the cell will not produce the emission of light.

The typical technique used to supply a sufficient quantity of free particles for a cell to be turned "on" uses a border at the edges of the plasma display panel, forming a perimeter around the addressable display area of the panel. The border includes a group of X-electrodes and Yelectrodes at the edges of the panel. A special voltage waveform is applied to cells formed by electrode intersections in the border areas to cause very intense discharges to occur in the border areas.

These intense discharges flood the addressable display area of the plasma panel with a sufficient number of particles to enable the panel to be addressed with relative accuracy.

Such border discharges present several problems. The cells of the plasma panel in the display area are affected in varying degrees, depending upon their distance from the border electrodes. Thus, the density of free particles is likely to be higher at the edges of the display areas than at the center of the display area. This may result in non-uniform operating characteristics of the display area, which may adversely affect the process of addressing these cells.

Under low ambient light conditions, light generated in the border area is highly visible, even though it is optically masked, usually by taping the area of the panel where the border electrodes are located. Light from the border area is transmitted to other areas inside the plasma display panel by reflection and light scattering. A typical 512 by 512 panel has nine rod-shaped spacers of 1/8" length between the two glass plates forming the panel, which serve to maintain a separation of electrodes on the two glass plates.

Since these spacers are inside the panel, they will reflect and scatter the high intensity border light into the display area of the panel.

In the process of manufacturing the plasma panel, small amounts of contaminant gases, such as water vapor, CO, CO2, and partially fragmented hydrocarbons are introduced into the panel. These contaminants condense on the surface of the cells in the panel which are not frequently turned on. They can adversely affect performance of the plasma panel, increasing the voltage required to turn a cell "on". Use of border discharges does nothing to correct this condition.

In order to operate a system using border discharges to provide free particles, two sustain circuits and logic timing and control circuits for these sustain circuits are needed. In addition, the border sustainers need a separate high voltage power supply in the 120-1 50 volt range. This additional circuitry adds to the cost, size, and heat dissipation problems of the plasma display system.

These problems, associated with the prior art, are eliminated in the present invention through the use of a distributed conditioning operation which causes all cells in the viewing area of the plasma panel to be periodically discharged. This periodic activity provides the free particles required, and eliminates the need for border discharges. The key to the distributed conditioning function is that it discharges the cells without affecting the inherent memory of the panel. In other words, a cell that was "off" before the distributed conditioning operation will be "off" after the operation. Similarly, a cell that was "on" before distributed conditioning will remain "on" after the distributed conditioning operation.

When all of the cells in the panel are discharged, the free particles needed to perform the write function are generated. Once a plasma display panel has been supplied with free particles, reliable write operations can occur during an extended period of time. Therefore, continuous discharges are not necessary in order to ensure reliable write operations.

The distributed conditioning operation generates light pulses throughout the display area of the panel, and it is therefore important that the operation be performed as infrequently as possible to maximize the contrast ratio of the panel. On the other hand, it has been found that, if the period between conditioning operations is too long, the panel will appear to flicker at a low illumination level. For this reason, the operation is typically performed periodically at a rate of 120 Hz. This frequency is selected as a compromise between these conflicting factors. The use of the distributed conditioning function at a 120 Hz rate also does not significantly slow the update rate of the panel.

The distributed conditioning process provides several significant advantages. It provides a uniform supply of free particles in a plasma panel display area so that addressing operations can be undertaken under uniform conditions throughout the panel. Since the border sustainers are no longer necessary, the constant annoyance of the intense light along the borders, reflected and dispersed within the panel, is no longer present.

Since all of the cells in the plasmal panel viewing area are periodically discharged, condensation will not collect in cells which have not been written and are not being sustained.

Contamination on the surface of these cells is also prevented, since when the cell is periodically turned on by the distributed conditioning operation, the contaminants are immediately driven from the surface. These contaminants will then move to areas of the plasma panel not being used for display purposes, these areas being away from the viewing area of the panel, and collection of contaminants there being less harmful.

The implementation of the distributed conditioning operation requires the addition of two integrated circuit chips, and may require expansion of the waveform ROM. By adding these few components, the entire border sustainer circuitry may be eliminated. The elimination of the border sustainer also makes possible the elimination of an extra power supply. It can therefore be seen that the use of the distributed conditioning technique will result in considerable cost savings in manufacture of the panel, as well as in improved operating characteristics.

The invention is described further hereinafter by way of example only, with reference to the accompanying drawings, in which: Figure 1 is a diagram of the electrode configuration of a known AC plasma panel showing border sustainer electrodes and display area electrodes for a border sustainer type system; Figure 2 is a waveform diagram showing the outputs of the drive circuitry, the Y-border sustainer output, the applied cell voltage Y-X and the applied border cell voltage YBDRX, for a known border sustainer-type system;; Figure 3 shows the various logic signal outputs from the waveform ROM which are inputs to the sustainer and driver circuitry, the outputs of the driver circuitry, the wall charge of "on" and "off" cells, and the applied cell voltage Y-X for a distributed conditioning operation carried out between two sustain functions in accordance with the present invention; Fiqure 4 is a block diagram of a plasma display panel and its interface and control circuitry, containing the present invention; Figure 5 is a block diagram of the interface and control circuitry, including the waveform ROM and its logic signal outputs, which are supplied to the system of Figure 4; Figure 6 is a chart of the address groups and ROM address locations for the operations controlled by the waveform ROM of Figure 5; ; Figure 7 is a schematic diagram of the distributed conditioning circuit shown in Figure 5; Figure 8 is a schematic diagram of the sustainer and driver circuitry for the plasma display panel system shown in Figure 4, using the present invention; Figure 9 is a chart showing the output of the Xdriver circuit of Figure 8 to an X-electrode being addressed, for a given distributed conditioning DCON signal, X-Sustain XS, and X-Address Pulse XAP input; and Figure 10 is a chart showing the output of the Y-driver circuit of Figure 8 to a Y-electrode being addressed, for a given Y-Sustain YS and Y Address Pulse YAP input; In order that the advantages of the present invention be made apparent, it is necessary to understand the operating characteristics of a border sustainer system. Figure 1 depicts a plasma panel 70 and some of the electrodes contained in that panel.The X-border electrodes 76 and the Y-border electrodes 78 are located around the perimeter of the plasmal panel. The electrodes in the visual display area 75 of the plasma panel 70 and X-electrodes 72 and Yelectrodes 74. The X-electrodes 76, 72 are formed on an interior substrate of a first glass plate, while the Y-electrodes 78, 74 are formed on a second glass plate. These plates are spaced from one another, and a gas is sealed between them. The electrodes 72-78 depicted in Figure 1 represent only a portion of the total number electrodes, since there are 512 X-electrodes and 512 Y-electrodes.

Free particles used to initiate the discharges in the visual display area 75 are generated by discharges at intersections between the Xelectrodes 72 and the Y-border electrodes 78, and the intersections between the Y-electrodes 74 and the X-border electrodes 76. The voltage levels which are supplied to these electrodes during a sustain operation are shown in Figure 2.

The voltage supplied to the X-electrodes 72 is Xdriver, the voltage supplied to the Y-electrodes 74 is Y-driver, the voltage supplied to the Y-border electrodes 78 is YBDR The voltage levels supplied to the X-border electrodes 76 is not shown.

The voltage applied to a single display area cell, or intersection between an X-electrode 72 and a Y-electrode 74 in the viewing area 75, is the applied cell voltage Y-X. The points in the applied cell voltage Y-X where light pulses will be emitted from "on" cells are indicated by a and b in Figure 2.

The voltage applied to border cells, or intersections between the X-electrodes 72 and the Y-border electrodes 78, is the applied border voltage YBDRX driven The voltage applied to the Y-border electrodes 78, VBDRT is of a greater magnitude than the voltage applied to Yelectrodes 74 in the viewing area 75. The magnitude of this voltage, VBDR, is typically 1 20 to 1 50 volts, which is the voltage level high enough to ensure that discharges will occur in the border areas even though the cells in these areas may have absorbed contamination on the cell surfaces.

The applied border voltage, Y,,,--X-driver, will therefore vary between VBDR and -V,,,, a 220 to 250 volt swing. This large voltage swing will cause very intense discharges to occur in the border cells at the point indicated on the applied border voltage YBDRX-driver waveform as c, and a second discharge will take place at d. These discharges generate the particles necessary to ensure that reliable write operations occur in the visual display area 75 of the plasma panel 70.

The present invention completely eliminates the border sustainer circuitry and border electrodes which were previously used to supply free particles. This is accomplished through a periodic distributed conditioning of the entire panel. The concept of distributed conditioning is to periodically discharge all the cells in the visual display area 75 of the plasma panel 70. To accomplish this, the voltages shown in Figure 3 are applied to the X-electrodes 72 and Yelectrodes 74 in the viewing area 75 of the plasma panel 70. The distributed conditioning function, which is performed in a 40 microseconds period, is preceded and followed by sustain functions, in Figure 3, for purposes of comparison. The distributed conditioning voltage waveform, like the sustain waveform, is transmitted to every cell in the visual display area 75 of the plasma panel 70.The applied cell voltage Y-X shown in Figure 3 is thus the voltage applied to each cell in the panel.

Also shown in Figure 3 are waveforms depicting the wall charge of an "on" cell and the wall charge of an "off" cell. The wall charge which accumulates on the walls of an "on" cell causes a voltage to be generated by the cell. Since the charge and the voltage generated are directly proportional, the wall charge can be measured by the magnitude of the voltage. When the applied cell voltage Y-X during a sustain function is applied to an "on" cell, the wall charge of the cell will change polarity each time the applied cell voltage Y-X crosses AC zero. When the wall charge changes polarity, a pulse of light is emitted from the cell.Because an "off" cell, as shown in Figure 3, has no initial charge, the applied cell voltage Y-X during a sustain operation, will be insufficient to effect the wall charge, and thus no polarity reversal occurs, and no light is emitted.

The applied cell voltage Y-X during a distributed conditioning operation, shown in Figure 3, has three distinct component pulses, these pulses causing different effects on "on" cells and "off" cells. The pulse indicated by I affects only the "on" cells, in the same manner as the positive sustain pulse effects only "on" cells.

This pulse I causes the wall charge of these "on" cells to reverse polarity to the positive side of AC zero, emitting a pulse of light. Pulse I has absolutely no effect on cells which are "off", and the wall charge of "off" cells will remain at the AC zero point in the manner described for the sustain waveform.

Pulse II is at a voltage level of 2Vcc2 above the AC zero point (which is at a D.C. potential of --V,,,). Pulse il does not affect "on" cells, since the wall charge of an "on" cell is already positive and thus the differential voltage applied to an "on" cell by this pulse II is only Vcc2. However, pulse li causes the wall charge of "off" cells to rise, following the applied cell voltage Y-X. This rise in the wall charge of "off" cells will cause each "off" cell to emit light at the point indicated by f. The applied cell voltage Y-X then drops to the AC zero point, and because the voltage differential is sufficient, the wall charge of "off" cells will follow the trailing edge of pulse II and return to AC zero, emitting light at point g.It should be noted that the pulse II causes the "off" cells to discharge twice, and leaves them with a 0 level wall charge, or in an "off" state. The wall charge of "on" cells is unaffected by pulse II, and remains at a high level relative to AC zero.

The third component pulse of the distributed conditioning function is pulse III, which affects the cells in the manner described for the second pulse of a sustain operation. Thus it causes the wall charge of "on" cells to reverse polarity, causing the "on" cells to emit light. Pulse 111 has no effect at all on "off" cells.

It can therefore be seen that the net effect of a distributed conditioning function is to perform a sustain function for "on" cells, and to cause all "off" cells to be discharged twice. The distributed conditioning function does not effect the state of the cells, so "on" cells will remain "on" and "off" cells will remain "off". As shown in Figure 3, the distributed conditioning pulses are generated in a 40 microsecond period, while the sustain pulses, as previously described, are generated in a 20 microsecond period.

The distributed conditioning function is typically applied to the plasma panel at a 120 Hz rate. The selection of a proper frequency for the distributed conditioning function is determined by several factors. The lower limit of the distributed conditioning frequency is determined by the flicker frequency, which is the frequency at which the human eye is able to notice a substantial flicker in light. Since all cells of the plasma panel periodically generate a pulse of light due to the distributed conditioning function, a human observer will notice an annoying flicker in the light emitted from the plasma panel, if the frequency at which this is distributed conditioning function is being performed is too low. The flicker frequency is approximately 40 to 70 Hz, depending upon the observer.Therefore, a 1 20 Hz repetition rate is distributed conditioning is high enough to eliminate the possibility of a flicker being observed in the light emitted from the panel.

Because all the "off" cells in the display area of panel emit light during the distributed conditioning operation the contrast ratio of the display area will be lowered. If all "off" cells do not emit any light, the contrast ratio is theoretically infinitely high. However, due to the light emitted by border sustainers in a conventional system, and the light emitted by "on"cells being scattered, the contrast ratio is actually somewhat lower than this. By using the distributed conditioning function at a frequency of 1 20 Hz, the "off" cells will be discharged once for each 41 7 times the "on" cells are discharged; the contrast ratio is therefore 417 to 1 at 120 Hz.

This contrast ratio is sufficiently high so the effect of discharging all "off" cells at a 120 Hz rate is negligible.

The final factor to be considered in determining the distributed conditioning rate is the reduction in the display update rate. Since the distributed conditioning function must be inserted into the addressing and sustain waveforms, the maximum update rate of the plasma panel will be lowered.

At a frequency of 120 Hz, the display update rate is lowered by only 0.48% which is negligible reduction.

Figure 4 shows the plasma panel 70, and the driver and sustainer circuitry controlling the panel 70. The driver and sustainer circuitry are of the type disclosed in our European Patent Application No. 81303065.7 entitled "Plasma Display Panel Drive" which was published on the 20th of January, 1 982 under Publication No. 0044182.

Reference is hereby directed to that Application for details of the driver and sustainer circuitry.

The plasma panel 70, as shown in Figure 1, includes X-electrodes 72 and Y-electrodes 74.

These electrodes, as shown in Figure 4, are an Xaxis driver circuit 250 and a Y-axis driver circuit 1 50. A pair of sustain circuits 210 and 110 are used to provide the sustain signal to the driver circuits 250 and 150, respectively. Float circuits 211 and 111 are used to supply floating supply levels of Vcci and Vcc2 to the driver circuits 250 and 150, respectively. The X-sustain circuit 210 is controlled by an X-sustain signal XS, and the Ysustain circuit is controlled by a Y-sustain signal YS.Addressing of individual cells of the panel 70, to accomplish selective writing and erasing of these cells, is controlled by an address pulse XAP and a Y-address pulse YAP, supplied from a waveform ROM (Read Only Memory) through a pair of level shift circuits 240 and 140, which are required since the driver circuits 250 and 1 50 operate on floating grounds. X-address information and Y-address information is supplied to the driver circuits 250, 1 50 through a pair of level shift circuits 93 and 91 respectively, and identifies which cells on the plasma panel 70 are to receive the X and Y address pulses.

The present system further comprises a distributed conditioning signal DCON supplied to the X-axis driver circuit 250 via a level shift circuit 200. The waveform ROM, therefore is required to output an inverse distributed conditioning signal DCON, since the level shift circuit 200 inverts the signal.

The waveform ROM and its addressing circuitry are shown in Figure 5. A distributed conditioning input 50 and a mode control input 12 determine which of 1 6 address groups in the waveform ROM 40 will be accessed. The distributed conditioning input 50 is generated by distributed conditioning circuit 52 and comprises two address bits, 50a and 50b, supplied to the waveform ROM 40. These two bits form the most significant address bits for the ROM 40, and determine whether the address group which is to be accessed is in address groups 1 to 4, 5 to 8, 9 to 12, or 13 to 16, as shown by the chart in Figure 6. The two next most significant address bits for the waveform ROM 40 are bits 1 2a and 12b, which are generated by a function logic circuit 11.These bits 12a,12b determine which of the four basic functions (bulk-erase, erase, write, or sustain) will be implemented, as shown in Figure 6.

It may be seen from the chart in Figure 6 that each of the address groups has 64 addressable data words, as shown in the column marked "ROM Address". Sequencing through these 64 addresses is controlled by timing information 38, supplied by a system counter/sequencer 34 and a system clock 32 of Figure 5. The chart in Figure 6 shows, under the heading "Function", the operations that will be performed for each of these 1 6 address groups. It may be seen that address groups 5 to 8 are not used; the choice of these 4 address groups to be unused will be apparent later, when the operation of the distributed conditioning circuit 52 is explained.

Address groups 9 to 12 all contain the first 20 microseconds of distributed conditioning; these four address groups are identical. Address groups 1 3 to 1 6 all contain the second 20 microseconds of distributed conditioning function; these four waveform groups are identical. The redundant storage of each half of the distributed conditioning function in four ROM areas facilitates easier addressing of the waveform ROM. Since only 1K of memory is used in this application, this redundancy does not seriously effect system cost. During normal operation of the plasma panel 70, the system will operate using one of the first four address groups, that is, bulk-erase, erase, write, or sustain.When a distributed conditioning function is to be performed, address bits 50a and 50b will switch from 00 to 10, causing the first 20 microseconds of distributed conditioning to be performed. At the end of this 20 microseconds, the address bits 50 and 50b will switch to 11, causing the second 20 microseconds of distributed conditioning waveforms to be accessed. When the second 20 microseconds of distributed conditioning waveforms have been performed, the address bits 50a and 50b will return to 00, and the system will once again perform one of the four basic functions. For example, if the system is performing a sustain function at address group 4, switching of bits 50a,50b to 10 will address group 12.

Later switching of bits 50a,50b to 11 will address group 16. Finally, switching of bits 50a, 50b to 00 will address one of groups 1 to 4, depending on the state of bits 12a,12b at this time. Thus, the address group used for the first or last 20 microseconds of distributed conditioning depends upon the state of this 1 2a and 1 2b, but is irrelevant, since groups 9-12 are identical, as are groups 1 3-1 6.

Returning again to Figure 5, it may be seen that the waveform ROM 40 has six logic signal outputs; these outputs are the standard four outputs XS, YS, XAP' and YAP', and two additional outputs: DCON' and SYNC. The DCON' logic signal output is a distributed conditioning signal, and it is supplied to the circuit of Figure 4.

The SYNC is a synchronizing pulse, going to a suppressor 36, preventing X-address information and Y-address information from being supplied to the driver circuits 250 and 1 50 (Fig. 4) during the distributed conditioning process.

Past practice of driving the plasma panel 70 has been to supply information to the plasma panel in columns. This would mean that a vertical column of information would be written at a time, rather than writing a horizontal line of information. Since it is customary in western cultures to write horizontally rather than vertically, if the plasma panel is to be used to display text, it is desirable to write information horizontally rather than vertically. Referring to Figure 4, the present system makes this change by switching the X-axis driver chips and the Y-axis driver chips. The X-axis driver chip, used for the driver 250, is a Texas Instruments SN75501 chip, and the Y-axis driver chip, used for the driver 150, is a Texas Instruments SN75500 chip.By making this change, a line of information may be written much more quickly than before, since, in vertical writing panels, the entire panel would have to be written in order to change a single line of text.

Here, only one line need be written.

Figure 8 shows the X-axis driver chips XD-1 to XD1 6 of X axis driver circuit 250, and the level shift circuit 200 used to supply the distributed conditioning signal DCON to the driver chips.

Other inputs to the driver chips include line 254, the high voltage input, line 252, the floating Vcc, power supply, line 258, the X-address pulse XAP input, and line 260, the floating ground. Xaddress information is supplied through the level shift circuit 93 (Figure 4) on line 96 to the driver chips. Information concerning the operation of these inputs to the driver chips may be obtained from out above referenced European Patent Application No. 81303065.7.

The distributed conditioning signal DCON is supplied on line 256 to the driver chips. In bordersustained circuits, line 256, which is the sustain pin of the SN75501 chips, is simply tied high to the floating voltage Vcc. This pin, in the present system is connected by line 256 to a level shift circuit 200, the output of which is based on the floating ground at line 260. The input to the level shift circuit 200 is, of course, the inverse distributed conditioning signal DCON' supplied from the waveform ROM 40. The level shift circuit 200 is well known, and may comprise, for example, an optical isolator or a transformer.

The logic level of the distributed conditioning signal DCON, as well as that of the other four logic signals, for the distributed conditioning function are shown in Figure 3. It may be seen that pulse II of the distributed conditioning function is generated by the distributed conditioning signal DCON dropping to 0 from its normal logic level 1.

The voltage output of the X-axis driver circuit 250 (SN75501) is described by the chart in Figure 9 for various DCON, XS, and XAP inputs.

The chart in Figure 10 describes the voltage output of the Y-axis driver circuit 1 50 (Figure 4, SN 75500) for various YS and YAP inputs. The outputs listed in Figure 9 and Figure 10 are the voltages which are supplied to the electrodes, the outputs of Figure 9 being supplied to the X-axis electrodes 72 (Figure 1) and the output of Figure 10 being supplied to the Y-axis electrodes 74 (Figure 1). A comparison of the logic levels YX, XS, DCON, YAP and XAP in Figure 3 with the charts of Figures 9 and 10 will show that the voltages Y driver and X driver, Figure 3, are produced to execute the distributed conditioning function.

The distributed conditioning circuit 52 (Figure 5) is shown in the schematic diagram of Figure 7.

This circuit supplies the most significant address bits 50a and 50b to the waveform ROM 40 (Figure 5). During normal operation of the plasma panel, bits 50a and 50b will be at a logic signal of 00. In order to perform the distributed conditioning function, the address bits 50a and 50b must go to 10 for 20 microseconds, and then to 11 for an additional 20 microseconds, and finally return to 00, as described above.

Since bits 50a and 50b are to be controlled by the same clock controlling the waveform ROM 40, bits 50a and 50b change logic levels only at the time the waveform ROM 40 completes sequencing through an address group. The distributed conditioning circuitry 52 has two main components: a monostable multivibrator 53 and a counter 54. The multivibrator 53 is typically an SN 54121, and basically acts as a time delay.

When the input to the multivibrator 53 goes from a logic level of 1 to a logic level of 0, the multivibrator 53 will begin timing. When the multivibrator 53 times out, it will output a low pulse, its output normally being high.

The counter 54 is typically a 54L51 61, and will supply the address bits 50a and 50b to the waveform ROM 40 (Figure 5). Before the multivibrator 53 times cut and outputs a low level pulse, the address bits 50a and 50b are at 00 level. When the low level pulse of the multivibrator 53 is output, it will cause the counter 54 to output as bits 50a and 50b a 10 signal, as soon as the clock input 57 indicates the waveform ROM 40 has completed an address group. When bits 50a and 50b switch to 10, one of the address groups 9 to 12 (Figure 6) will be accessed.

When bit 50a switches to 1, the 1 logic level is supplied to the enable P input of the counter 54, causing the counter to begin sequencing at this point, on the same time base as the waveform ROM. The counter 54 therefore will not change states for 20 microseconds, while the waveform ROM 40 sequences through one of the address groups 9 to 12. At this point, the clock input 57 will increment the counter chip 54 and bits 50a and 50b will switch to 11, causing one of the address groups 13 to 1 6 (Figure 6) in waveform ROM 40 to be accessed. After 20 microseconds, the counter 54 will increment again, causing bits 50a and 50b to switch to 00, and causing one of ROM address groups 1 to 4 (Figure 6) to again be accessed. When bits 50a goes to 0, it will supply the 0 logic level to the enable P lead of the counter 54, causing it to stop incrementing.Bit 50a is also input to the multivibrator 53, and when it switches to 0, it will cause the multivibrator 53 to again begin timing. The time delay provided by the multivibrator 53 is 8.3 milliseconds so that the entire sequence will be repeated at a rate of 120Hz.

The present invention eliminates the need for separate border sustainer circuitry, and the logic circuitry for controlling the border sustainers.

Elimination of this circuitry results in savings in cost and size, and significantly reduces power dissipation problems. Implementation is accomplished by adding only two chips 53 and 54, and by expanding the storage capability of the waveform ROM 40 if necessary.

Since all of the cells in the plasma panel viewing area are periodically discharged, condensation will not collect in those cells which are not written and sustained. Contamination of the surface of these cells is also eliminated by the periodic discharging of the cells by the distributed conditioning operation.

The plasma panel update rate and the contrast ratio are degraded only to a minimal extent, and this degradation is substantially outweighed by the advantages of the distributed conditioning system. The annoying light from the border electrodes has been completely eliminated, thus eliminating the light reflection and scattering within the panel caused by the illumination of the border electrodes.

The entire viewing area of the plasma panel is used to generate the free particles used in the writing operation, so the characteristics of the plasma panel will be more uniform than they were with the border discharge system. Uniform characteristics of the plasma panel enable write, sustain, and erase operations to be undertaken under the constant conditions required to ensure that these operations will be carried out with complete accuracy.

It can therefore be seen that the distributed conditioning technique results in considerable cost savings in the manufacture of the panel, and in much improved overall operating characteristics of the panel, with a cost of only an infinitesimal degradation in a few operating characteristics of the system.

Claims (8)

Claims

1. A plasma panel system, comprising a plurality of electrodes which form panel cells in a display area; a memory storing digital data defining a first group of waveforms for application to said electrodes to cause selected ones of said cells to generate light of a higher intensity than the other ones of said cells and a second group of waveforms for application to said electrodes to cause the generation of free particles in said panel without affecting the light generation state of said cells; a circuit for selectively accessing digital data defining said first and second groups of waveforms from said memory; and a drive circuit coupled to said memory for generating said first and second groups of waveforms.

2. A plasma panel system, as claimed in claim 1, wherein said memory additionally generates a synchronizing signal and wherein said system additionally includes a circuit for addressing the plasma panel, the latter circuit being responsive to said synchronizing signal and causing addressing of the panel to cease while said second group of waveforms are being applied to the panel.

3. A plasma panel system, as claimed in claim 1 or 2 wherein said second group of waveforms applied to said panel comprises a first pulse performing half of a sustain function on all of said selected ones of said codes, a second pulse causing all of said other ones of said cells to be discharged, and a third pulse performing the other half of a sustain function on all of said selected ones of said cells.

4. A plasma panel system, as claimed in claim 1, wherein said second group of waveforms periodically discharges said cells.

5. A plasma panel system, as claimed in claim 1 , wherein said first group of waveforms places an electrical charge on said selected ones of said cells.

6. A plasma panel system, as claimed in claim 1, wherein said second group of waveforms twice reverses the charge plurality on said selected ones of said cells.

7. A plasma panel system, as claimed in claim 1, wherein said second group of waveforms charges and later discharges said other ones of said cells.

8. A plasma panel system substantially as hereinbefore described with reference to Figs 3 to 10 of the accompanying drawings.