GB2103404A - Communication system - Google Patents

Abstract

The system comprises a master station, which generates and transmits a waveform (Figure 2) including synchronising pulses followed by a stream of alternate clock and data pulses, and a number of sender and receiver stations. Each sender station (Figure 3) counts the clock pulses from a synchronising pulse and can modify the waveform by suppressing the data pulse following a clock pulse associated with at least one operator-selected or predetermined address count of clock pulses. The receiver stations (Figure 8) also count the clock pulses and can recognise a suppressed data pulse associated with one or more address counts and produce an appropriate indication. The system is powered solely by power supplied to the master station, the receiver and sender stations being powered by power derived from the transmitted waveform. <IMAGE>

Description

SPECIFICATION Communication system The invention relates to a communication system such as can be used for monitoring and/or control of remote events.

Such communication systems find application for example in hotels to enable staff to known in which rooms service is required, or in security installations, to enable a watchman orsupervisorto monitor remote events perhaps from more than one location, and to take appropriate action. Such systems can be applied domestically to allow remote switching of lights and/or appliances, and industrially in connection with plant comprising separated co-operating units whose performance has to be checked and adjusted. It is desirable that such systems be low in cost and easy to install.

The invention accordingly provides a communication system comprising a master station connected to sender and receiver stations, the master station being arranged to continuously generate and transmit to the sender and receiver stations a waveform comprising synchronizing intervals spaced apart by predetermined numbers of clock and associated data pulses, the or each sender station being arranged to recognise the synchronizing intervals, to count the clock pulses, and to modify the data pulse(s) associated with a respective address count of clock pulses, and the or each receiver station being arranged to recognise the synchronizing intervals, to count the clock pulses, and to detect any modification of data pulse associated with the said address count of clock pulses.

Conveniently, the synchronizing intervals are spaced apart by a string of alternate clock and data pulses and each clock pulse and the subsequent data pulse are conveniently constituted by adjacent portions of a single pulse. The pulses may for example extend on either side of zero volts. The data pulse modification could be effected by increasing the pulse amplitude, but conveniently the modification is effected by a decrease, amounting preferably to suppression of the data pulse.

The system can include a considerable number of sender and receiver stations and at least one sender station may be arranged to modify data pulses associated with a selected plurality of address counts of clock pulses and at least one receiver station may be arranged to detect modification of data pulses associated with a selected plurality of address counts of clock pulses. Thus each sender can be arranged to signal to one or more receiver stations and each receiver arranged to identify signals from one or more sender stations, the particular stations being predetermined, and/or condition responsive and/or selectable by an operator of the sender station.

The stations can be connected together by two wires and the power necessary for operation can be derived from the waveform carried by these wires from the master station. Low voltages only need be employed, and the number of sender and receiver stations, which can be readily increased or decreased after initial installation, is limited only by the losses associated with the wires.

A communication system embodying the invention is described below, by way of example, with reference to the accompanying drawings, in which: Figure lisa schematic circuit diagram of a master station included in the communication system; Figure 2 is a waveform generated by the master station of Figure 1; Figure 3 is a schematic circuit diagram of a sender station included in the communication system; Figure 4, 5 and 6 show respective waveforms generated within the station of Figure 3; Figure 7 shows how the sender station can modify the waveform of Figure 2; Figure 8 is a schematic circuit diagram of a receiver station included in the communication system; Figure 9 schematically shows how the stations of the communication system can be connected together.

The illustrated system comprises a single master station (Figure 1) connected by a pair of wires 4,5 to a plurality of sender stations (Figure 3) and to a plurality of receiver stations (Figure 8).

As schematically shown in Figure 1,the master station comprises voltage supply sources 1,2 respectively providing voltages, five volts in the present system, which are positive and negative with respect to the COMMON wire 4. The positive voltage source 1 is connected to LINE wire 5 through a resistor R, and the negative voltage source is connected to LINE through a transistor T which acts as a low impedance switch controlled by a signal applied to its base by a microprocessor control unit 6 powered from the negative voltage source. The signals applied by the unit 6 to the base of the transistor T produce on LINE the waveform shown in Figure 2, comprising square pulses 8 of relatively long duration separated by a train comprising a fixed number, one hundred in the present system, of like, narrower, square pulses 9.Each of the pulses 8 and 9 extends between the plus and minus 5-volt levels, and for the purpose of the following discussion, the part of each pulse 9 between 0 and -5 volts will be regarded as a clock pulse, and the part of the pulse between 0 and +5 volts is regarded as a data pulse. Thus each clock pulse is followed integrally by a data pulse. The resistor R and the positive voltage source 1 could be replaced by a current source which is constant or approximately so.

The sender station schematically illustrated in Figure 3 is connected between the LINE and COM MON wires 4,5. Negative supply Vss for use by associated electronic circuitry is obtained at terminal 11 from the clock pulses by rectification effected by a diode D1, a resistor R1 and a capacitor C1, and terminal 12 provides the voltage Vdd on COMMON to such circuitry.

The clock pulses are also received by an inverting Schmitt trigger G1 through a high frequency filter, comprising resistor R2 and capacitor, C2, which serves to minimize the effects of electromagnetic interference. The threshold of the trigger circuit G 1 is substantially symmetrical about 1/2 Vss, so that the circuit responds only to the clock waveform and not to the associated data waveform.

The waveform at the output of the trigger G1 is the reverse of that supplied by the master station, so that the synchronizing pulse produces a long negative pulse as shown in Figure 4. A circuit comprising a diode D2, a resistor R3 and a capacitor C3 supplies to the input of an inverting Schmitt trigger device G2 the waveform shown in Figure 5, because of the unequal charge and discharge time constants of this circuit. The output of the trigger circuit G2 is shown in Figure 6. It comprises pulses within the duration of each input synchronisation pulse going from approximately Vss to approximately 0. These pulses are employed as re-set to empty two decade counters N1 and N2.

The inverted clock pulses appearing at the output of the trigger circuit G1 are arranged to increment the decade counter No, the CARRY output of which increments the second counter N2. The two decade counters are reset to zero during each synchronizing pulse as described above, and, between the synchronizing pulses, the counters maintain a continuous record of the number of clock pulses which follow the previous synchronizing pulse, the least significant digit being in counter N1 and the most significant digit being counter N2.

Each count of the counters Nl ,N2 can represent an address of a respective receiver station and the sender station includes means associated with the counter for modifying the data pulse subsequent to the clock pulse which completed the count representing a receiver station when it is desired to signal to that station. Thus, an AND gate G3 has its inputs connected selectively to decoded outputs of the two counters N1,N2, the connections being shown as to the output representing "3" in the counter N2, and, by means of a switch SWA, to one or other of the outputs of the counter N1 representing respectively "6" and "7". Resistor R4 is included to inhibit activity when the switch SWA is momentarily open between its two positions. The output of the gate G3 is connected to an inverter G4.

With the switch SWA in the position shown, the inputs to the AND gate G3 are both high only in the interval between the 36th and 37th clock pulses.

Thus during that interval, the inverter G4 provides an output through a resistor R5 which turns on a transistor T1. The effect of this is to sink the positive current received from the master station through a diode D3 and a resistor R6. The current clock pulse thus makes no substantial positive excursion to produce a data pulse, which would have been the 36th data pulse, and the output waveform is consequently modified as shown in Figure 7. A diode D4 is connected from between the diode D3 and COM MON to ensure that the clock waveform is not pulled substantially negative.

Usually, means will be provided to permit selection from a larger range of addresses than from only addresses represented by counts of 36 and 37, and it will be evident that the simple arrangement shown in Figure 3 for purposes of explanation can be appropriately enlarged for this purpose. Thus, by selecting appropriate decoded outputs from the counters N1 and N2, by way of selector means such as the switch SWA, it is possible for a sender station to modify the data pulse train, by substantially removing data pulses at desired positions in the train which can be identified by counting from a given synchronizing pulse.

The receiver station shown schematically in Figure 8 will be seen to resemble the sender station of Figure 3 in many respects which therefore will not be now described. The receiver station is however arranged not to suppress data pulses, but to detect the presence or absence of a data pulse following one or more particular clock pulses in the train, which completes a count corresponding to the or an address of the receiver station.The station of Figure 8 is arranged to give a visual indication when either or both of the 36th or 37th data pulses have been modified by a sender station as described above in connection with Figure 3, but it will be evident that the station can readily be modified to respond to any desired number or address counts, which may be selectable or predetermined, and that the output used to supply a visual indication can be used instead or as well for control and/or recording purposes.

Decoded outputs from the counters N 1 ,N2 for the number 36 as shown, are taken to an AND gate G4, which supplies an output to a flip-flop FF2. The other input to this flip-flop is obtained from LINE through a transistor Tri, which acts in conjunction with resistors R4 and R5 as a "level shifter" to give a voltage at its collector substantially equal to Vdd whenever LINE is positive. The data input of flip-flop FF2 is thus close to zero volts when data pulses are present on line and close to Vss when a data pulse has been suppressed by a sender station as described above.

Until the 36th clock pulse of the pulse train is reached flip-flop FF2 receives a voltage close to Vss at its clock input. When the 36th pulse arrives the output of AND gate G4 goes positive towards Vdd and the output of flip-flop FF2 is clocked to assume the state of the data input present at this time. The clock pulses at the inverting Schmitt trigger G1 are delayed by a resistor-capacitor network R2,C2, to ensure that this instant coincides with the subsequent data pulse present on LINE. If the 36th data pulse is active, that is suppressed, the output of flip-flop FF2 goes low and current flows through an LED2 to cause this to be illuminated. The output of flipflop FF2 remains high, so that LED2 is not illuminated, as long as data pulses continue to be present.

Provision is also made for indicating an active condition, that is, a suppressed data pulse at the 37th clock pulse, byway of an AND gate G3, a flip-flop FF1 and an LED 1. The operation, on arrival of a suppressed data pulse directly after clock pulse 37 corresponds to that described above with reference to arrival of a suppressed data pulse after clock pulse 36.

The invention thus provides a communicaton system which makes it possible for any one of a plurality of sender stations to communicate with any one or more of a plurality of receiver stations, wherever located, over a single pair of wires in a simple, inexpensive and versatile way. Figure 9 shows schematically how a system can be arranged, or developed by addition of sender and receiver stations. Each station is represented by U; only one is a master station but the others can be either sender or receiver stations as desired.

The invention can be embodied in a variety of different ways, for example, as regards the way in which the functions of the three kinds of station are carried out. The system illustrated can be modified.

For example, the clock pulses are negative and the data pulses positive, but it will be evident that the polarities can be reversed, or unipolar positive or negative signals employed, the clock and data pulses being distinguished from one another at an appropriate intermediate voltage.

Claims (11)

1. A communication system comprising a master station connected to sender and receiver stations, the master station being arranged to continuously generate and transmit to the sender and receiver stations a waveform comprising synchronizing intervals spaced apart by predetermined numbers of clock and associated data pulses, the or each sender station being arranged to recognise the synchronising intervals, to count the clock pulses, and to modify the data pulse(s) associated with a respective count of clock pulses, and the or each receiver station being arranged to recognise the synchronizing intervals, to count the clock pulses, and to detect any modification of a data pulse associated with the said address count of clock pulses.

2. A communication system according to claim 1, in which the synchronizing intervals are spaced apart by a string of alternate clock and data pulses.

3. A communication system according to claim 2, in which each clock pulse and the subsequent data pulse are constituted by adjacent portions of a single pulse.

4. A communication system according to any one of claims 1 to 3, in which the data pulse modification is effected by a change in data pulse amplitude.

5. A communication system according to claim 4, in which the data pulse modification is effected by suppression of the data pulse amplitude to zero.

6. A communication system according to any one of claims 1 to 5, in which at least one sender station is arranged to modify data pulses associated with a selected plurality of address counts of clock pulses.

7. A communication system according to any one of claims 1 to 6, in which at least one receiver station is arranged to detect modification of data pulses associated with a selected plurality of address counts of clock pulses.

8. A communication system according to claim 6 or 7, in which the address counts of the said plurality of counts are predetermined.

9. A communication system according to claim 6 or 7, in which the address counts of the said plurality of counts are selectable by an operator.

10. A communication system according to any one of claims 1 to 9, in which the sender and receiver stations are powered by power derived from the waveform transmitted by the master station.

11. A communication system substantially as hereinbefore described with reference to Figures 1 to 8 of the drawings.