GB2103442A - Output-linearizing system for a dual slope analog-to-digital converter - Google Patents

Abstract

Digital linearization of the output of a dual slope analog-to-digital converter 12 is provided by using a programmed micro-computer 25 reading a programmable-read-only- memory (PROM) 28 to run a variable frequency clock 30. The clock is regulated during the fixed time period of the converter at a frequency comprising an even multiple of the power line frequency, and during the variable time period at various frequencies in accordance with deviation from linearity of the analog input.

Description

(112)UK Patent Application (1,,) GB (11) 2 103 442 A (21) Application No

80203839 (22) Date of filing 27 Jul 1979 Date lodged 10 Feb 1982 (30) Priority data (31) 939315 (32) 5 Sep 1978 (33) United States of America (US) (43) Application published 16 Feb 1983 (51) INT CL3 H03K 13120 (52) Domestic classification H3H 13D 14B 14D 14X 1 F 1G 23F 3G 6A 613 6F 713 7F 7G 8E AD (56) Documents cited GB 1238305 GB 1213634 GB 1153201 (58) Field of search H3H (60) Derived from Application No 7926181 under Section 15(4) of the Patents Art 1977 (71) Applicant Dresser Ir (LISADel The Dresi Elm and i PO Box 7 Dallas, Texas 75: United S.

(72) Inventor Francis h (74) Agents A. A. The Northun 303-306 tlign London WC1 V 7LE (54) Output-linearlizing system fora dual slope analog-to-digital converter (57) Digital linearization of the output of a dual slope analog-to- digital converter 12 is provided by using a programmed micro-computer 26 reading a programmable - read - only memory (PROM) 28 to run a variable frequency clock 30. The clock is reguiated during the fixed time period of the converter at a frequency comprising an even multiple of the power line frequency, and during the variable time period at various frequencies in accordance with deviation from linearity of the analog input.

ERRATUM SPECIFICATION No. 2103442 A

Front page Heading (2 1) Application Nofor 80203839 read 8203839 THE PATENT OFFICE, April Ist, 1983 1W ERRATA SLIP ATTACHED C) W r\j ---1 0 W -P-Ith -PS NJ 1 GB 2 103 442 A 1 SPECIFICATION

Output-linearizing system for a dual slope analogto-digital converter This invention relates to the art of dual slope analog-to-digital converters for effecting a digital output signal of a measure analog signal being supplied to the converter and relates in particularto a system for linearizing the digital output of such a converter.

The dual slope type analog-to-digital dual slope converter for effecting a digital output signal from a measured analog input signal is well known as dis- closed, for example, in U.S. patents 3 061 939, 3 316 546,3 458 803,3 660 834 and 3 566 397. Briefly, the method of conversion involves integrating a current directly related to an unknown voltage for a fixed period of time, followed by the integration of a stan- dard current related to a reference voltage of opposite polarity until the integrator output returns to zero. The total time period required to null the integrator is directly proportional to the ratio of the measured current to the standard current, and, therefore, to the measured voltage. The integrator, therefore, is a circuit producing a linearly changing output with time (usually a ramp) when the input is some constant voltage and the rate of integrator output voltage increase is directly proportional to the mag- nitude of the input voltage. When input voltage is zero, output voltage is not subject to change but remains zero at whatever output value was achieved at the beginning of the time period.

Standard operation for such prior art converters has included integration of the unknown in the same 100 direction of polarity as the input signal, e.g. pos itive-to- positive which is then switched to a reference signal of opposite polarity that is integrated at zero. This is then detected by a comparator of the integrated signals and for large analog inputs 105 prolonged time periods are required to effect the zero integration. The digital counts are then accumulated in a register proportional to the time factor associated with the unknown integration.

While this basic arrangement has functioned well with a high order of accuracy, it requires reference switching and polarity detection which becomes difficult atvery low inputs leading to switching uncertainties. Also, bias currents associated with these prior devices have added and substracted from the slopes in each of its changed directions. For overcoming these deficiences, it has been necessary to utilize precision low offset amplifiers. Despite recognition of the foregoing, means for effecting their elimination has not heretofore been known.

Our application 7926181, from which this application is divided, described and claims an improved dual slope analog-to-digital converter.

In accordance with the present invention, there is provided a system for linearizing the digital output of a dual slope analog-to-digital converter, comprising a variable frequency clock and means operative to drive said clock during the fixed time period of said converter at a frequency comprising an even multi- pie of the power line frequency at which the conver- ter is to be used and to drive said clock during the variable time period at controlled changes in frequencies per unit of time in accordance with deviation from linearity of the analog signal being received by the converter.

In an embodiment to be described herein, a programmed microcomputer reads a PROM to run a variable frequency clock via the PROM programming. The clock frequency is regulated to effect a first phase converter time that corresponds with an even multiple of the power line frequency. Accumulated counts then vary directly with clock frequency.

Said embodiment of the invention will now be described, by way of example only, with reference to the accompanying drawings, in which:

FIGURE 1 is a block diagram of a system incorporating a converter in accordance with the invention of our application 7926181; FIGURE 2 is an electronic schematic of the conver- ter of Figure 1; FIGURE 3 is a timing diagram of the dual slope converter of Figure 2 at zero and non-zero signal levels; and FIGURE 4 is a diagram of a linearizing system in accordance with the present invention and applied to the dual slope converter of Figure 2 for affording digital linearization of the output thereof.

Referring first to Figure 1, there is disclosed a transducer 10 adapted to continuously emit an analog signal Va correlated to the measured value of a condition being measured by the transducer. Transducer 10 can typically be any suitable type measuring instrument from which an analog output can be obtained and in a preferred use may constitute a pressure ortemperature transducer as disclosed, for example in U.S. patents 3 742 233 or 4 109 147. Analog signal Va from the transducer, along with a reference signal Vr of a known regulated voltage as will be explained are both supplied to A/D converter 12 in accordance herewith to in turn emit a count signal Vd for any of a variety of application such as for operating a digital display 14.

Referring now to Figure 2, the modified A/D dual slope converter 12 hereof is comprised of a sum- ming amplifier 16, an integrator 18, a comparator and auto-zero amplifier 20, a samplelhold amplifier 22 and a logic and accumulator module 24 which for the embodiment being described is of a commercially available type similar to National Semiconduc- tor MM5330 A/D Building Block operative as will be explained below. Analog signal Va, being supplied from transducer 10 in correlation to its measured parameter, is of negative polarityfor connection directly through switch SW-1 to summing amplifier 16, while reference voltage Vr, being supplied from a regulated voltage source, is of negative polarity for connection through switch SW-2 to comparator and auto-zero amplifier 20. The output of amplifier 16 is provided through switch SW-3 to the positive termi- nal of integrator 18 while a Vm,, voltage is derived from Vr through dividers R, and R2 forfeeding the negative terminal of integrator 18. By way of example, if maximum positive voltage at Va = 1.9999 volts, V... would arbitrarily be set at 2.2000 volts and at Va =zero measurement would be based on 2 GB 2 103 442 A 2 2.2000 volts. Logic and accumulator module 24 provides the logic for sequencing the aforementioned switches.

With reference also to Fig. 3, the complete AID conversion cycle of transducer signal Va is shown in which Va = 0 volts is the solid slope and Va i4 0 volts for a measured value not equal to zero has a dashed slope. The cycle from left to right (Fig. 3) consists of three phases being auto-zero phase Ill, the integrator reference phase 1 for a predetermined fixed time period T, and the integrated unknown phase H for a variable time period Tx. During phase Ill, comparator and auto-zero amplifier 20 functions as a high gain zeroing amplifierthat with switch SW-4 closed drives samplelhold amplifier 22, capacitor CA and inverting summing amplifier 16 through switch SW-3 to restore the integrator capacitor C-2 voltage to zero volts. Switches SW-1, SW-2 and SW-5 during this phase are all in grounded position. Also, because of the characteristics of amplifier 22, all amplifier voltage offsets are stored on capacitor CA where they remain through the integration cycle serving to eliminate even large offset voltages.

During phase 1, in response to a received power line sync signal, switches SW-4 and SW-5 are opened. Reference voltage Vr is applied through switch SW-2 to amplifier 20 for simultaneously establishing V,,, via divider R, and R2. VM, is chosen based on the full scale counts desired. At the same time, Va is connected to the input integrator 18 via summing amplifier 16 and switch SW-3. The output of integrator 18 then slews to Va for integration to begin for a reference period Tr during which time integration occurs for a signal value based on the differential between (Vr,,.,,-Va). Time Tr is preferably selected to be of some even multiple of the local power line frequency for increasing the normal mode noise rejection of the converter.

On completion of phase 1, phase 11 is initiated dur- ing which reference voltage Vr is applied to integrator 18 for the unknown period Tx until the threshold of comparator 20 is crossed in its comparison between the signal levels of Vr and the integrator output. At such time, coincident with the com- parator output, the digital counts which accumulated 110 during integration period Tx are transferred from the counter to the latches, the parallel output signal of which V,, is applied to display unit 14 or transmitted elsewhere as desired. The latter can be understood by the following example in which:

Tr = C.

C, Where Q, = counts overflow Cf = clock frequency (HZ) assuming third harmonic of 60HZ =.050 sec. and Q, = 18000 then Cf = 36000 HZ Where Va equal zero and Vmax is measured, a complete conversion will occur on the basis of:

Te = Tr + Tx (Fig. 3) TI: = 18000 + 22000 = 0.111111 sec. j_60000 360000 with + 0000 displayed.

For any positive Va less than V,,,,, the code converter 9's complements the counter to display the measured value. In this manner, display 14 yields a linear conversion for Va less than V....

For effecting digital linearization usable with AID converter 12 orwith any dual slope standard system, reference is made to Fig. 4 in which there is shown a schematic circuit therefor including a microcomputer 26, a PROM 28 and a variable frequency clock source 30 connected to logic and accumulator module 24. During phase 1 (Fig. 3), microcomputer 26 reads PROM 28 for receipt of programmed information to drive clock 30 at a frequency such that Tr is an even multiple of the power line frequency Phase 11 is sensed by the microcomputer on the convert line Co and based on information received from PROM 28 drives the frequency of clock 30 at various rates per unittime as programmed into PROM 28. In this manner, clocking frequencies that are different between phases 11 and 1 do not affect the conversion time which instead remains constant for a given input voltage Va. Integrator 18 functions in the same manner as described above while the counts accumulated during time period Tx will vary more directly dependent on the frequency of clock 30. Should Va be a nonplinear response of some linear function being measured, the final accumulated counts are therefore adjusted in that manner to yield a linear digital representation of the measure- ment.

If, for example, different clocking frequencies are utilized during phase 11 than Phase 1, the conversion time nevertheless remains the same for a given input voltage Va since integrator 18 makes the same excursion. The counts accumulated during Tx will be more or less depending on the frequency of clock 30 such that the accumulated counts over the course of Tx can be varied in di rect relation to the value of Va. Using the previous example and varying the clock- ing frequency a number of times (n) then when n = 5 TX Tn = 5 0122222and Nt = Tn (FJ + Tn (F3) + Tn (F4) + Tn (F5) + Tn (F6) where F, = clock frequency during Tr 360 KHZ F, = clock frequency du ri ng Tx 350 F.3 = clock frequency during Tx 340 F4 = clock frequency during Tx 300 F5 = clock frequency during Tx 360 F6 = clock frequency during Tx 450 Nt = 21997 and if the dual slope converter hereof reaches crossover Tx =.0366666 seconds, three corrections have occurred and the display will read: 22000 - Tn (F, + F2 + F3) = 9902 counts In the same example with a constant clocking frequency Tx=.0611111 Tn=.0122222 giving an Nt = 21999 and Linear Display = 22000 13200 = 8800 counts Comparison of the above examples shows that in both cases the total number was essentially the same but the non-linear accumulation resulted in a 1102 count increase for a given Va = Tx.

By the above description there is disclosed a novel modification of an analog-to-digital dual slope type k -3 t 3 GB 2 103 442 A 3 is converter able to give a linear digital representation of a non-linear analog signal representing the measured output of a condition responsive element. By use of relatively inexpensive non-critical components, the precision elements required for eliminating the inherent problems of standard dual slope systems are thereby avoided. When employing linearization in accordance herewith, greater flexibility is afforded as compared to analog summing techniques previously utilized. Moreover, the linearization attains the precision of a digital correction that is highly repeatable and inherently temperature stable with the ability to tailor the response from one instrument to the other. Whereas the linearization has been described in combination with the modified dual slope converter hereof, it is not intended to be so limited since it could be readily utilized with such standard unmodified dual slope converters of the prior art.

Claims (3)

2G, CLAIMS

1. A system for linearizing the digital output of a dual slope analog-todigital converter, comprising a variable frequency clock and means operative to drive said clock during the fixed time period of said converter at a frequency comprising an even multiple of the power line frequency at which the converter is to be used and to drive said clock during the variable time period at controlled changes in frequencies per unit of time in accordance with devia- tion from linearity of the analog signal being received by the converter.

2. A system according to claim 1 including a programmable - read - only memory (PROM) programmed for effecting said clock frequency changes during the variable time period.

3. A system for linearizing the digital output of a dual slope analog-to-digital converter, said system being substantially as herein described with reference to the accompanying drawings.

Printed for Her Majesty's Stationery Office by The Tweeddale Press Ltd., Berwick-upon-Tweed, 1983. Published atthe PatentOffice, 25 Southampton Buildings, London, WC2A lAY, from which copies may be obtained.

3. A system for linearizing the digital output of a dual slope analog-todigital converter, said system being substantially as herein described with reference to the accompanying drawings.

New claims or amendments to claims filed on 27.9.82. Superseded claims 13. New or amended claims:- 1. A system for linearizing the digital output of a dual slope analog-to- digital converter, comprising a variable frequency clock and means operative to drive said clock during the fixed time period of said converter at a frequency comprising an even multiple of the power line frequency at which the conver- ter is to be used and to drive said clock during the variable time period at a frequency which is controlled to change at regular intervals of time in accordance with deviation from linearity of the analog signal being received by the converter.

2. A system according to claim 1 including a programmable - read - only memory (PROM) programmed for effecting said clock frequency changes during the variable time period.