GB2107145A

GB2107145A - D/A converter

Info

Publication number: GB2107145A
Application number: GB08129437A
Authority: GB
Inventors: Philip Joseph Elce
Original assignee: Standard Telephone and Cables PLC
Current assignee: STC PLC
Priority date: 1981-09-29
Filing date: 1981-09-29
Publication date: 1983-04-20
Also published as: GB2107145B

Abstract

A digital-to-analogue converter arrangement, for digital signals in the form of a succession of m-bit digital words, includes plurality of individual (m-n)-bit digital-to-analogue converters 1-4 the outputs of which are summed 5 to provide the analogue output, means for feeding the (m-n) least significant bits of the m-bit digital words to the individual converters in parallel, means for decoding 12 the n most significant bits of the m-bit words to enable one or more of said individual converters such that when more than one converter is enabled all but one of the enabled converters are automatically set to provide a maximum analogue output, and means for modifying 6-7 the (m-n) least significant bits according to the decoding of the n most significant bits. <IMAGE>

Description

SPECIFICATION D/A converter This invention relates to a digital-to-analogue converter arrangement, such as may be used with digital transmission systems for speech.

High speed digital-to-analogue converters which are available at present usually rely on thin-film resistors for their accuracy. Therefore they are limited in accuracy by the matching of these resistors, and at the present time the best matching which can be obtained in production is of the order of .01%, which would be sufficient for a 12-bit converter. Time and/or temperature could cause the accuracy to fall by a factor of 2 or 4, such that the 12 bit D/A converter would have errors in its transfer characteristic which would be of the order of +1 or even +2 least significant bits (LSBs). These errors can occur such that one point on the transfer characteristic has an error of +2 LSB and the next adjacent point can have an error of -2 LSB.This type of effect, called differential non-linearity, can cause non linear distortion and noise in the signal being processed. The effect can be even worse when a D/A converter is used as part of an A/D converter in which case the transfer characteristic of the A/D has 'missing codes'.

According to the present invention there is provided a digital-to-analogue converter arrangement for digital signals in the form of a succession of m-bit digital words, the arrangement including a plurality of individual (m - n)-bit digital-to-analogue converters the outputs of which are summed to provide the overall analogue output range of the arrangement, means for feeding the (m - n) least significant bits of the m-bit digital words to the individual converters in parallel, means for decoding the n most significant bits of the m-bit words to provide selection control signals, selection means responsive to said selection control signals to enable one or more of said individual converters such that when more than one converter is enabled all but one of the enabled converters are automatically set to provide a maximum analogue output, and means for modifying the (m - n) least significant bits according to the decoding of the n most significant bits.

An embodiment of the invention will now be described with reference to the accompanying drawings, in which: Fig. 1 llustrates in block schematic form a D/A converter arrangement according to the invention, and Figs. 2a and 2b illustrate graphically a comparison of the effect of errors in a conventional D/A with those of the arrangement of Fig. 1.

For the sake of example it is assumed that the digital input is in the form of conventional binary encoded 12-bit words.

Four 10-bit individual D/A converters 1-4 have their outputs fed to a summing network 5. The 10 least significant bits of the 12-bit words are fed, via adders 6, 7 and input selectors 8-11 1 to the D/A converters 1-4 in parallel. The two most significant bits of the 12-bit words are fed to a decoding logic 12, which controls the selectors 8-11 The output voltage of the arrangement of Fig. 1 is in the range 0 to 4092 mV. The digital input words range from 000 000 000 000 to 111 111 111 111, i.e.

from code zero to code 4092. (None that the range is slightly reduced compared to a normal 12-bit D/A converter).

For codes in the range 0 to 1023 the 10 least significant bits (LSB) of data are presented to the inputs of the first D/A converter, and the inputs to the others are set to all ZEROS.

For codes in the range 1024 to 2046 one LSB is added to the digital data word and the resulting modified 10 LSBs are presented to the inputs of the second converter 2 the inputs to the first converter 1 are set to all ONES and the inputs to the third and fourth converters are set to all ZEROS.

For codes in the range 2047 to 3069 two LSBs are added to the 10 LSBs of the input and the 10 LSBs of the result are presented to the inputs of the third converter 3. The inputs to the first and second converters are set to all ONES and the inputs to the fourth converter are set to all ZEROS.

For codes in the range 3070 to 4092 three LSBs are added to the data word and the 10 LSBs of the result are presented to the inputs of the fourth converter with all inputs to the other converters set to ONES.

The method is summarized in the table CODES D/A 1 D/A 2 D/A3 D/A 4 3070 to 4092 ONES ONES ONES LSBs + 3 2047 to 3069 ONES ONES LSBs + 2 ZEROS 1024 to 2046 ONES LSBs + 1 ZEROS ZEROS O to 1023 LSBs ZEROS ZEROS ZEROS Notice that the numbering of the converters is arbitrary but once it has been chosen the same numbering is always used.

The method by which the input codes are determined to be greater than 1023 or greater than 2046 or greater than 3069 is not part of this patent application and could be implemented in several ways. An example is given here.

The two most significant bits (MSB) are decoded. If they are both ZERO the input code is in the range 0 to 1023. If the MSB is zero and the 2nd MSB is ONE, one LSB is added to the input code and if no carry is generated at the 3rd MSB position in adder 6 the input code is in the range 1024 to 2046. If a carry is generated at the 3rd MSB position a further LSB is added and the input code is known to be 2047. If the MSB is ONE and the 2nd MSB is ZERO two LSBs are added and if no carry is generated at the 3rd MSB the input code must be in the range 2047 to 3069. If there is a carry produced at the 3rd MSB a further LSB is added and the code is known to be either 3070 or 3071. If the first two MSBs are ONES the input is known to be in the range 3072 to the maximum limit which has been set at 4092 by previous circuitry.

Thus it can be seen that by using the arrangement of the invention two or more individual D/A converters of given resolution can be used in parallel to obtain a converter of higher resolution. It is not necessary for all the individual D/A converters to be identical. For example the converters may be deliberately different to obtain an overall transfer characteristic of a desired non-linear shape.

Conversely, if the individual converters are prima facia identical then errors in the matching between the individual converters do not cause large discontinuities in the transfer characteristic, but instead cause the average slope of the transfer characteristic to take on two or more different values over different segments of its range. The change from one value of average slope to the next is smooth.This is desirable for good noise performance. Fig. 2a shows how a single error in a conventional D/A converter, say on the second LSB when the code transition from 100 000 000 000 to 011 111 111 111 111 occurs, results in a constant error in the actual characteristic of 2 amplitude levels in all the higher code conversions. in contrast, a single error in any one of the individual D/A converters of the present invention has maximum on only the higher levels being outputted from that converter and, as succeeding converters are enabled, this error will become less and less significant. Fig. 2b illustrates the effect of an error in the second LSB in an arrangement according to the invention.

If special purpose D/A converters are designed with an "extra LSB" input then the invention can be imptemented without the need for the adders of Fig. 1. The selection logic now feeds the converters directly with appropriate extra inputs ELSB as indicated by the dotted lines. Otherwise the arrangement of Fig. 1 is unaltered. The use of such purpose designed D/A converters aliows the overall range to be increased to the conventional value, i.e. 4096 levels in the present case since each converter can now handle codes ranging from 0 to 1024. The method table then becomes:- CODES D/A 1 D/A 2 D/A 3 D/A4 3072 to 4095 ONES + ELSB ONES + ELSB ONES + ELSB D 2048 to 3071 ONES + ELSB ONES + ELSB D ZEROES 1024 to 2047 ONES + ELSB D ZEROES ZEROES Oto 1023 D ZEROES ZEROES ZEROES In other words the 10 LSB's of the 12-bit digital input are applied directly to whe LD/A's without the addition stage previously required.

Claims

1. A digital-to-analogue converter arrangement for digital signals in the form of a succession of m-bit digital words, the arrangement including a plurality of individual (m - n)-bit digital-to-analogue converters the outputs of which are summed to provide the overall analogue output range of the arrangement, means for feeding the (m - n) least significant bits of the m-bit digital words to the individual converters in parallel, means for decoding the n most significant bits of the m-bit words to provide control signals, and selection means responsive to said control signals to enable one or more of said individual converters such that when more than one converter is enabled all but one of the enabled converters are automatically set to provide a maximum analogue output.

2. An arrangement according to claim 1 wherein all the individual (m - n)-bit digital-to-analogue converters are substantially identical.

3. An arrangement according to claim 1 or 2 including means for modifying the irn - n) least significant bits comprising means for adding one or more least significant bits to the (m - n) least significant bits according to the value of the n most significant bits.

4. An arrangement according to claim 3 wherein the means for adding comprises first and second (m - n)-bit adders, the (m - n) least significant bits of the m-bit digital words being fed to the first adder together with the least significant bits to be added thereto, the output of the first adder being fed to the second adder together with a carry output generated in the first adder, said carry output being fed to the second adder in the form of a further least significant bit to be added to output of the first adder.

5. A digital-to-analogue converter arrangement substantially as described with reference to the accompanying drawings.

6. A method of converting a digital signal in the form of a succession of m-bit digital words into an analogue signal comprising feeding the m - n least significant bits of each word in parallel to a plurality of substantially identical (m - n)-bit digital-to-analogue converters, decoding the n most significant bits of each word to derive control signals for the converters, enabling one or more of the converters in accordance with the control signals whereby at least one enabled converter decodes the m - n least significant bits to produce an analogue output and the other enabled converters, if any, each produce a maximum analogue output, and summing the analogue outputs of the plurality of converters.