GB2108342A - Power-on reset circuit - Google Patents

Abstract

A voltage responsive circuit provides a logic high output signal when a supply voltage is below a predetermined value and a logic low signal when the supply voltage is above the predetermined value. The circuit includes an input switching stage (T1 to T6) and an output buffer stage (T7 to T10), the input switching stage being such that, on power-up, a logic high output signal is produced until the supply voltage rises above the predetermined level. A reference voltage for the circuit is provided, e.g. by a Zener diode (ZD1). The circuit samples the supply voltage periodically in response to a clock pulse signal. This provides a very low power dissipation. <IMAGE>

Description

SPECIFICATION Reset circuit This invention relates to reset circuits such as are employed to ensure correct operation of logic cir cuitry following an initial application of power.

Existing power-on reset circuits generally make use of current mirrors or flip-flop circuits designed to come up in a known state when power is applied.

Current mirrors have the disadvantage of relatively high power consumption, as a standing current must flow in at least one arm of the mirror. Assymetrical flip-flop circuits whilst providing the advantages of very low power consumption (in CMOS circuits) after triggering, have the disadvantage that the turn-over pointforthe circuit may be varied only by changing the geometrical parameters of the transistors, and is in any case rather too low for convenient usage, being of the order of the sum of the p and n transistor threshold voltages. Also, the assymetrical flip-flop circuit, once set, is incapable of being reset and this cannot be used as a power-fail detector.

The object of the present invention is to minimise or to overcome these disadvantages.

According to the invention there is provided a voltage responsive circuit adapted to provide a first output condition when a supply voltage is below a predetermined value, and a second output condition when the supply voltage is above the predetermined value, said circuit comprising comparator means whereby the supply voltage is compared with a reference voltage, switching means operable via said comparator means whereby the circuit is switched between its first and second conditions, and means whereby said supply voltage is periodically sampled when the circuit output is in its second output condition.

The reset circuit arrangement achieves a well-defined and adjustable circuit turn-over point, operates with low power dissipation and can be used to generate both power-on and power-fail reset signals.

An embodiement of the invention will now be described with reference to the accompanying drawings in which: Fig. lisa schematic circuit diagram of the reset circuit; and Fig. 2 illustrates various waveforms produced by the circuit of Fig. 1 during the resetting process.

Referring to the drawings, the reset circuit, which is advantageously fabricated in the form of a CMOS integrated circuit, comprises an input switching stage (transistors T1 to T6) and an output buffer stage (transistors T7 to T10). A voltage reference for the circuit is provided by Zener diode ZD1 and resistor R1 which, advantageously, are discrete components external to the reset circuit. Timing signals may be applied via a clock input IP1.

On the system level, the operation of the circuit is as follows: 1. When power is applied to the circuit the reset signal output OP goes high, indicating that the supply voltage VDD has not yet reached its defined value.

2. When VDD reaches the defined value the reset signal output goes low.

3. The reset signal output remains low while VDD is above the defined value. If at any point VDD falls below that value, the reset output goes high and remains high until VDD has once again risen above the defined value, whereupon the output will once again go low.

Operations 1. and 2. provide the POWER-ON RESET function of the circuit and operation 3, the POWER-FAIL RESET function.

It is essential for the correct operation of the circuit that the set-reset flip-flop formed by the transistors Ti, T4 and T5 comes up with a high level at node C when power is first applied to the circuit. Assuming that power has been removed from the circuit for a sufficiently long period to ensure that all nodes are near or at the Vss level, the charging currents through Ti and T5 must be adjusted so that node C charges at a faster rate then node B when power is applied in orderto satisfy the required circuit function. The changing current to node B, delivered by T1, is restricted to the leakage current of T1 as T1 gate - source voltage remains near zero until VDD reaches the region of the external reference voltage.

Thus this voltage at node B rises only very slowly; T5 switches on, pulling up the reset signal output line and charging node C which in turn causes T4 to turn-on, initiating regenerative action in the flip-flop so firmly establishing the output high state.

Two additional safeguards have been built into the ci rcuit to ensure correct initial operation: i) A saturated transistorT2 is inserted between T1 and T4. This transistor is a long channel device and the consequent large gate area provides a large capacitive load on node B, further impeding initial voltage rise at that node.

ii) The operation of the circuit as described above is the worst-case condition assuming that no clock is present at the gate of T3. Regenerative action in the flip-flop is initiated when a clock pulse arrives at that point.

The turn-over voltage for the reset circuit is set by the external Zener +. The Zener voltage Viz at node A is a function of the Zenervalue and the current through the load resistor R, which in turn depends on the supply voltage VDD. V may be adjusted by selection of Zener value and by variation in the value of R. T1 provides current to charge mode B when T1 goes into weak inversion, i.e. when: VDD - V= The Ferni level F is a function of the process parameters and of temperature.The voltage to which node B may be charged is dependent upon the potential-divider effect of transistors T1, T2 and T4, further complicated by the change in channel conductances, especially ofT1, as VDD rises. In practice, all that is required to realise the requisite circuit function is to set the inverter point of T5, T6 such that the voltage at node B rises above that point when VDD reaches the required level. This is most easily achieved using a circuit analysis program.

When the voltage at node B rises above the inverter threshold of T5, T6, T5 will begin to turn off and T6 to turn on. This will cause node C to be discharged, initiate regenerative action in the flip flop and cause the output line to go low.

In order to detect a POWER-FAIL condition (VDD below the required level) a clock pulse is periodically applied to the gate T3. This causes T3 to switch on, and if T1 is off due to a depression of VDD, will discharge node B, set the flip-fiop and bring the output line high. The output line will remain high until VDD rises above the required level. If, however, VDD is above the minimum defined level, T1 will be on and all that will happen will be that the node B voltage will be depressed slightly, but not below the inverter threshold of T5, T6. A current will flow between VDD and Vss in the path T1, T2, T3 and this results in the sampling node power dissipation.Two actions can be taken to minimise this current and hence the power dissipation: i) The sampling clock mark-space ratio should be kept as low as possible, consistent with any maximum-delay-to-power-fail-detection criteriu m. By this means the average power dissipation over the clock cycle may be brought to a very low figure.

ii) The resistance in the T1, T2, T3 path may be increased (so reducing current flow) by lengthening the channel length of T2. Care must be taken that the RC time constant of node B is not increased to such an extent that T3 is unable to discharge node B belowtheT5,T6 inverterthreshold before the end of the sampling clock high period.

The switching portion of the circuit comprising T1 -T6 provides: Positive and reliable assymetrical flip-flop action on power switch on, and A flip-flop reset point which is adjustable and set by external components.

The arrangement also provides a sampling mode for power-fail detection which permits a considerable reduction in power dissipation to be attained.

The inverter pair T7, T8 and T9, T10 buffers the POR output signal, ensuring fast signal slewing and good output logic levels into the remainder of the chip. The circuit is not of course limited to this particular form of output buffering and it will be clear to those skilled in the art that alternative output stages can be employed.

Claims (7)

1. A voltage responsive circuit adapted to provide a first output condition when a supply voltage is below a predetermined value, and a second output condition when the supply voltage is above the predetermined value, said circuit comprising compa rator means whereby the supply voltage is com pared with a reference voltage, switching means operable via said comparator means whereby the circuit is switched between its first and second condition, and means whereby said supply voltage is periodically sampled when the circuit output is in its second output condition.

2. A circuit as claimed in claim 1, and comprising a CMOS integrated circuit.

3. A circuit as claimed in claims 1 or 2, and incorporating an output buffer stage.

4. A circuit as claimed in claim 3, wherein said buffer stage comprises first and second inverters.

5. A voltage responsive circuit substantially as described herein with reference to the accompanying drawings.

6. A logic device provided with a reset circuit as claimed in any one of claims 1 to 5.

7. A method of voltage measurement substantially as described herein with reference to the accompanying drawings.