GB2136170A - Method and apparatus for accessing a memory system - Google Patents

Abstract

The method comprises establishing the number of address locations needed to comprise a significant amount of data, that is, an amount constituting intelligible information, one of which addresses is to be regarded as a reference address and the remainder as pointer addresses; and accessing a corresponding number of address locations in the memory system by moving the reference address to each of the locations in turn by instructions expressed as a sequence of pointer addresses.

Description

SPECIFICATION Method and apparatus for accessing a memory system The present invention relates to a method and apparatus for accessing a memory system.

In existing methods of accessing a memory system, either a large number of address locations are used or multiple addressing operations are required to access a single address location.

It is an object of the present invention to provide a more efficacious method and apparatus for accessing a memory system in order to limit the number of address locations that need to be employed and the addressing operations needed to access a single address location of the memory.

There is provided by the present invention, a method of accessing a memory system, comprising establishing the number of address locations needed to comprise a significant amount of data - i.e. an amount constituting intelligible information, one of which addresses is to be regarded as a reference address and the remainder as pointer addresses; and accessing a corresponding number of address locations in the memory system by moving the reference address to each of the locations in turn by instructions expressed as a sequence of pointer addresses.

The chosen number of addresses may be given sequential designations e.g. consecutive numbers.

In most applications it is considered that 9 addresses will be sufficient. Conveniently, these may be numbered consecutively say, 0 to 8. It is implicit in the present invention that one of the addresses represents the start of the sequence e.g. location 0, and that, when the reference address is moved to a location as determined by a pointer address, the pointers themselves are changed in order to maintain the same relationship to the newly positioned reference address so that the reference address is always associated with its predetermined number of pointer addresses.This has the effect of creating what might be called for convenience a "scanning frame" containing the predetermined number of addresses but displaceable in relation to a different set of memory address locations so that, although all the chosen number of addresses always maintain the same relationship to one another, they have no fixed absolute address.

The present invention is considered to be especially useful for image processing and graphic drawing operations, and the invention will be further described by way of example only, by reference to a presently preferred embodiment for use in such work and as illustrated in the accompanying drawing, in which:~ Fig. 1 is a diagram of a block of addresses used in the embodiment, and Fig. 2 is a diagram of an address sequence effected by the embodiment.

It is customary in this work to divide up a display screen into national unit areas called pixels. In the embodiment, the "scanning frame" consists of nine pixels each representing an address and, for convenience, consecutively numbered 0 to 8, arranged in the form of a rectangular block A consisting of an upper row Al of three pixels, a middle row A2 of three pixels and a bottom row A3 of three pixels with the pixels being numbered, reading from left to right of the block, respectively as 4, 3 and 2 in the upper row, and 5, 0 and 1 in the middle row and 6, 7 and 8 in the bottom row. It will be understood in this connection that a pixel on the display screen corresponds to an address location in the memory.

For the purpose of,exempiifying the manner in which the present invention may be used to access a memory, let it be imagined that it is required to draw a square on a display screen of three pixels by three pixels. The square is drawn starting from the bottom left-hand corner thereof and proceeding round back to that corner. In this case, th address sequence B shown in Fig. 2 (using the above-numbering) is 1, 1, 3, 3, 5, 5, 7, 7,. This means that pixel 0 is being used as the reference address and that in the first .nstance pixel 1 is being used as a pointer address. Moving the reference pixel in this manner has the effect of moving the entire block of pixels one address to the right. Since the square must be of three pixels length each side, it follows that pixel 1 is again used as the pointer address to which the reference address is moved.It also follows from this that by accessing the remainder in the sequences given above the result will be to draw the square.

The present invention preferably provides a facility to read the absolute address of the reference address and change the absolute address thereof at any time. This can be provided for by using an additional number of addresses.

Conveniently, some seven additional addresses are used which, in hexadecimal notation, may be referred to respectively as 9, A, B, C, D, E and F.

This means that at the most the present invention requires only 1 6 address locations of the memory system at any one time.

For the purpose of displacing the reference address, with its pointer addresses, two counters may be employed, one for vertical displacement of the reference address and one for horizontal displacement thereof. Depending on the address specified by a predetermined instruction, these counters may be incremented or decremented to effect the displacement of the reference address.

Thus, addressing pointer address 8 in the block arrangement of the pixels shown above, could be effected by incrementing both counters while, for instance, addressing pointer address 3 could be effected by causing a decrement in the vertical counter whilst leaving the horizontal counter unchanged.

The counters may also be used for translating the reference address with its associated pointer addresses to another and remote part of the screen. For this purpose, the counters may be such that they can be instantaneously set to any given value so that the required translation can be effected substantially instantaneously. Preferably, the counters are programmable.

Claims (19)

1. A method of accessing a memory system, comprising establishing the number of address locations needed to comprise a significant amount of data, that is, an amount constituting intelligible information, one of which addresses is to be regarded as a reference address and the remainer as pointer addresses; and accessing a corresponding number of address locations in the memory system by moving the reference address to each of the locations in turn by instructions expressed as a sequence of pointer addresses; the pointer addresses themselves being changed in location on each move of the reference address in order to maintain the same relationship to the newly positioned reference address so that the reference address is always associated with its predetermined number of pointer addresses.

2. A method according to claim 1, wherein the chosen number of addresses are given sequential designations.

3. A method according to claim 2, wherein the sequential designations are consecutive numbers.

4. A method according to any of the preceding claims, wherein there are 9 addresses.

5. A method according to claim 4 as dependent on claim 3, wherein these are numbered consecutively 0 to 8.

6. A method according to any of the preceding claims, whenever used for image processing and graphic drawing operations on a display screen.

7. A method according to claim 6, wherein said addresses are established to represent a corresponding number of pixels on a display screen arranged contiguously in a predetermined relationship.

8. A method according to claim 7, wherein said pixels represented by said addresses are arranged in a block of rows and columns of the pixels.

9. A method according to claim 8, wherein nine pixels are represented; the pixels being arranged in the form of a rectangular block consisting of an upper row of three pixels, a middle row of three pixels and a bottom row of three pixels.

10. A method according to claim 9, wherein the pixels are numbered, reading from left to right of the block, respectively as 4, 3 and 2 in the upper row, and 5, 0 and 1 in the middle row and 6, 7 and 8 in the bottom row.

1 1. A method according to any of the preceding claims, using a facility to read the absolute address of the reference address and to change the absolute address thereof at any time.

12. A method according to claim 1 1, wherein for the purpose thereof, an additional number of addresses is chosen.

13. A method according to claim 12, wherein 7 additional addresses are used.

14. A method according to any of the preceding claims 7 to 12 wherein, for the purpose of displacing the reference address, with its pointer addresses, two counters are employed, one for vertical displacement of the reference address and one for horizontal displacement thereof.

15. A method according to claim 14, wherein said counters are used for translating the reference address with its associated pointer addresses to another and remote part of the screen.

16. A method according to claim 15, wherein said counters are such that they can be instantaneously set to any given value so that the required translation can be effected substantially instantaneously.

17. A method according to claim 16, wherein said counters are programmable.

18. A method of accessing a memory system substantially as hereinbefore described with reference to the accompanying drawing.

19. Apparatus for accessing a memory system, substantially as hereinbefore described with reference to the accompanying drawing.