GB2137018A - A Semiconductor Memory Device - Google Patents

Abstract

In a dynamic random access memory comprising memory cells, each of which includes a MISFET and a memory cell capacitor having first and second electrodes, and dummy cells, each of which includes a MISFET and a dummy cell capacitor having third and fourth electrodes and having a capacitance equal to half that of the memory cell capacitor, the dummy cell capacitor 4 is shaped so that the magnitude of fluctuation of its area due to deviation of the fourth electrode 5 relative to the third electrode curing fabrication is one half of the magnitude of fluctuation of area of the memory cell capacitor due to a corresponding deviation of the second electrode relative to the first electrode. In this way the effects of capacitance variation due to misregistration during fabrication are minimised. Also the resistances of the word lines for driving dummy and memory cells are made equal. <IMAGE>

Description

SPECIFICATION A Semiconductor Memory Device The present invention relates to a semiconductor memory device, and more particularly to the memory and dummy cells of a semiconductor memory device, such as a dynamic random access memory (hereinafter referred to as a DRAM).

In a DRAM, information is stored in the capacitor Cs of a memory cell as quantities of charge corresponding to either of binary signals "0" and "1". A capacitor CDS is used as a reference for sensing whether the stored information is "O" or "1". The capacitor CDS forms together with two n-channel MISFETS a dummy cell. The potential difference which is produced by the difference between the quantities of charge in the capacitors Cs and CDS may be as small as a few tens of millivolts.

It is desirable that the quantities of charges q5 and qD5 ofthe respective capacitors Cs, CDS respectively obey the following relation: q5 qDs= (1) 2 By fulfilling Equation (1), the difference between the quantity of charge qD5 of the dummy cell and that of a memory cell having a signal "0", is the same as the difference between the quantity of charge qD5 of the dummy cell and that of the memory cell having a signal "1". For both signals "0" and "1", the maximum margins in signal reading operations may be achieved.

When the differences between the quantities of charge are unequal, the margin of either signal becomes narrow. Since the absolute value of the quantity of stored charge is small, the read-out of the signal is prone to a malfunction, which lowers the reliability of the semiconductor memory device.

The shape of the capacitor portion of a conventional dummy cell 1 is shown in Figure 1 of the accompanying drawings. A capacitor electrode 5 forms one electrode of the capacitor CDS of the dummy cell 1. The capacitor CDS is formed in a region 4 where a thin insulator film, which is formed within the region of the major surface of a semiconductor substrate 2 demarcated by an insulator film 3, and the capacitor electrode 5 overlap each other. The capacitance of the capacitor CDS is proportional to the area of the overlap. Since the overlap is formed of the combination of squares, no fluctuation develops in the capacitance of the capacitor CDS even when mask misregistrations in X and Y-directions have occurred.

As shown in Figure 2, the capacitor portion of a memory cell 6 is defined substantially in the shape of a pentagon by an insulator film 3A which is formed on the semiconductor substrate 2 simultaneously with the insulator film 3. A capacitor electrode 5A forms an electrode of the capacitor Cs of the memory cell 6. This capacitor electrode 5A is formed simultaneously with the capacitor electrode 5. As for the capacitor CDS, the capacitor Cs is formed in a region 7 where a thin insulator film, which is formed within the region defined by the insulator film 3A, and the capacitor electrode 5A overlap each other. The capacitance of the capacitor Cs is proportional to the area of the overlap.The capacitance of the capacitor Cs is affected slightly by a mask misregistration in the Y-direction, but it fluctuates greatly when a mask misregistration in the Xdirection occurs.

Thus, the prior-art DRAM includes within the same chip a capacitor CDS whose capacitance does not fluctuate due to the mask discrepancy of registration involved in the manufacturing process, and a capacitor Cs whose capacitance fluctuates due to such mis-registration. Therefore, the relation of Equation (1) is not satisfied.

Moreover, the differences of the quantities of charge of the signals "0" and "1" in the signal reading operations become unequal, and the margin of either signal is reduced. Malfunctions are liable to occur in signal reading operations, to disadvantageously lower the reliability of the memory device.

One aspect of the invention seeks to overcome, or at least ameliorate the problem of mask misregistration. It does this by ensuring that the fluctuation of area of a capacitor of a dummy cell is a fixed proportion, e.g. substantially half of the fluctuation of area of a capacitor of a corresponding memory cell.

Another aspect of the present invention concerns the substantial equalization of resistances of word lines for driving switching MISFETs of the memory cells and of the dummy cells. This may be achieved by ensuring that substantially the same number of steps exist under each word line. These steps are due to layers under the word lines and the resistance in a step is greater than that in a flat region.

In either aspect one electrode of the capacitor of a memory cell and the corresponding electrode of the capacitor of a dummy cell may each be formed by a part of the semiconductor substrate defined by an insulator film. The other electrodes of the capacitors of the memory and dummy cells are formed by a polycrystaline silicon layer. This permits that the electrodes of the capacitors of the memory and dummy cells to be formed simultaneously, so that any deviation of the electrodes will be the same for both the memory and dummy cells.

Embodiments of the invention will now be described in detail, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a plan view of parts of a conventional dummy cell.

Figure 2 is a plan view of parts of a conventional memory cell.

Figures 3A, 3B and 4 are diagrams for explaining the principles of the present invention.

Figure 5 is an outline diagram of a DRAM being a first embodiment of the present invention.

Figure 6 is a circuit diagram of the parts of the DRAM in Figure 5.

Figures 7 and 8 are plan view of parts of a dummy cell during the manufacturing of the DRAM shown in Figure 5.

Figure 9 is a plan view of parts of the dummy cell of the DRAM shown in Figure 5.

Figure 10 is a plan view of parts of a memory cell of the DRAM shown in Figure 5.

Figures 1 1, 13 and 15 are plan views of parts of dummy cells during manufacture, for explaining the layout of the DRAM in Figure 5.

Figures 12, 14 and 1 6 are plan views of parts of memory cells during manufacture for explaining the layout of the DRAM shown in Figure 5.

Figure 17 is a graph illustrating the effects of the first embodiment of the present invention.

Figure 18 is a plan view of the essential portions of a dummy cell of a second embodiment of the present invention.

Figure 1 9 is a plan view of the essential portions of a memory cell of the second embodiment of the present invention.

The reason why the present invention can exclude the influences of mask misregistrations in a manufacturing process will now be described.

The reason is essentially that the fluctuation of the areas of memory and dummy cells due to a misregistration the same magnitude and in the same direction for both cells is proportional, e.g.

has a ratio of 2:1.

Referring to Figures 3A and 3B, consider two base lines a-a and b-b. Oblique lines c-e and d-f extend at an angle 0 from points c and don the base lines a-a and b-b respectively. The angle O is 450. A line h-h orthogonally intersects the base line a-a at a point g. The intersection point between the line h-h and the oblique line c-e is a point i, the height of which from the base line a-a is H. A line k-k orthogonally intersects the base line b-b at a pointj, which line h-h bends at a predetermined position.The line k-k and the oblique line d-f orthogonally intersect at a point I, the height of which from the base line b-b is chosen to be H 2 Assume now that the line h-h and the line k-k move from their respective positions by equal magnitudes of displacement Ax, in the same direction.

The area ASa swept out by a movement of the line h-h is: Ax2 ASa=AS1+AS2=Ax.H+ (2) 2 The area ASb swept out by a movement of the line k-k is: H Ax2 ASb=AS3+A84=Ax.- + (3) 2 4 The first term of the right-hand side of Equation (2) and the first term of the right-hand side of Equation (3), and the second term of the right-hand side of Equation (2) and the second term of the right-hand side of Equation (3) are in the ratio 2:1, respectively.Thus, the area ASa and the area A8b for equal magnitudes of displacement in the same direction can have a ratio of 2:1 Figures 3A and 3B illustrate schematically the situations of the fluctuations of the capacitance values of the capacitor Cs of a memory cell and the capacitor CDS of a dummy cell, respectively.

This will be described in more detail later.

Figure 4 is a diagram for explaining how the ratio of areas of the memory and dummy cells changing in correspondence with the same magnitude of displacement in the same direction may be rendered 2:1.

Referring to Figure 4, consider a base line mm, with an oblique line n-o extending at an angle O from a point n on the base line m-m. The angle 0 is 450. A line q-q orthogonally intersects the base line m-m at a point p, which line q-q bends at a predetermined position. The line q-q and the oblique line n-o intersect orthogonally at a point r, the height of which from the base line m-m is H.In addition, a line m,~m, extends parallel to the base line m-m and at a height of H 2 A line q,-q, orthogonally intersects the base m-m at a point p and the point of intersection of which with the line m1-m1 is a point r,.

It is now assumed that the line q-q and the line q1q1 move from their respective positions by equal magnitudes of displacement Ax in the same direction.

An area ASm, swept out by a movement of the line q-q is: Ax2 A8m=AS5+AS6=Ax.H+ (4) 4 The area ASm swept out by a movement of the line q1-q1 is: H ASm1=Ax.- (5) 2 Assuming here that the area ASm1 is negative relative to the y ASm total ASt of the area ASm and the area ASm1 is: H Ax2 ASt=ASm+ (-ASm1)=Ax.- + (6) 2 4 Equation (6) is the same as Equation (3) discussed above. Thus the area ASa and the area ASt can have an areal ratio of 2:1 for equal magnitudes of displacement in the same direction.

Figure 4 illustrates the fluctuation of the capacitance of the capacitor CDS of a dummy cell, and Figure 3A that of the capacitor C5 of the memory cell.

Now, embodiments of the present invention will be described in detail.

In the drawings, corresponding parts have the same symbols, and repeated description of those corresponding part will not be given.

Figure 5 is a diagram of a DRAM which is first embodiment of the present invention, and shows the layout pattern of the 8-mat type DRAM.

Eight memory arrays M-ARY, each of which has a plurality of memory cells, are arranged in an IC chip so that they are isolated from one another.

A column decoder C-DCR for selecting data lines and dummy arrays D-ARY corresponding to the memory arrays M-ARY are provided between the memory arrays M-ARY.

Also a row decoder R-DCR for selecting word lines is provided between the memory arrays M ARY and a column/row change-over switch C/R SW is provided in a position surrounded by the column decoders and the row decoders.

A sense amplifier SA is provided at the end of each memory array M-ARY remote from the column decoder C-DCR.

The bit lines extend in the memory array M ARY in the direction of coupling the column decoder C-DCR and the sense amplifier SA. The word lines extend in the memory array M-ARY and the dummy array D-ARY in a direction orthogonally intersecting the bit lines. The bit lines are connected to the column decoder C-DCR and the sense amplifier SA, and the word lines to the row decoder R-DCR.

Peripheral circuitry PC is provided in the upper part of the IC chip, which circuitry includes e.g.

data input and output buffers, various signal generator circuits, a main amplifier, and a substrate bias generator circuit.

Bonding pads P are arranged in the upper and lower parts of the IC chip.

Figure 6 is a circuit diagram of the parts of the memory array M-ARY and dummy array D-ARY of the DRAM having a chip layout corresponding to Figure 5. The present embodiment adopts the folded bit line type in which two bit lines extend from one side of each sense amplifier SA.

Referring to Figure 6, two bit lines (being a pair of complementary data lines) BL, and BL2 extend from one sense amplifier SA towards the dummy cells. Other bit lines extend in columns over the semiconductor substrate in parallel with the bit lines BL1 BL2. The bit lines BL1 and BL2 serve to read information out of and write information into dummy cells and memory cells. The sense amplifier SA serves to amplify the small potential difference between the bit lines BL1 and BL2.

The memory cells M11,M12,M21andM22are each formed by switching Metal Insulator Semiconductor Field Effect Transistors (hereinafter referred to as MISFETS) Q11, Q12, Q21 and Q22, and capacitors Cs11, Cs12, Cs21 and Cs22. One terminal (the source or drain) of the MISFET Q11 or Q12 is connected to a predetermined position on the bit line BL1. One side of the capacitors Cs11 or C512 is connected to the other terminal of the MISFET Q11 or 42, while the other side thereof is connected to a power source terminal at voltage Vss. The voltage V55 is set at earth, which acts as a reference voltage.One terminal (the source or drain) of the MISFET Q21 or Q22 is connected to a predetermined position on the bit line BL2. One side of the capacitor Cs21 or Cs22 is connected to the other terminal of the MISFET Q21 or Q22, while the other side thereof is connected to the power source terminal at voltage V55.

Word lines WL1l, WL12,WL21 and WL22 apply voltages to the gate electrodes G1l, G12, G21 and G22 of the MISFETs Q11, Q12, Q21 and Q22, respectively. A plurality of other word lines extend in rows over the semiconductor substrate in parallel with the word lines WL1l, WL,2 etc. The memory cells form rows and columns corresponding to the intersection points between the word lines and the bit lines.

The dummy cells D", D12, D21 and D22 are each formed by switching MISFETs QD11' QD12 QD21 and QD22 capacitors CDS11 CDsi2, CDS21 and CDS22 having a capacitance value equal to half that of the capacitors Cs11, Cs12, Cs21 and C522 of the memory cells, and clearing MISFETs Qc11 Qc12, Qc21 and Qc22 clear charges stored in the capacitors CDS11' CDsl2, CDS21 and CDS22. One terminal (the source or drain) of the MISFET QD11 or QD12 is connected to a predetermined position on the bit line BL1.One side of the capacitor CDS or CDS12 is connected to the other terminal of the MISFETODIl orODi2, while the other side thereof is connected to the power source terminal at voltage Vss. One terminal (the source or drain) of the MISFET QD21 or QD22 is connected to a predetermined position on the bit line BL2. One side of the capacitor CDS21 or CDS22 is connected to the other terminal of the MISFET QD21 or QD22 while the other side thereof is connected to the power source terminal at voltage V55.

Word lines DWL11, DWL12, DWL21 and DWL22 apply voltages to the gate electrodes GD11, GDi2, GD21 and GD22 of the MISFETs QD11E QDt2 QD21 and QD22.-These word lines extend over the semiconductor substrate in parallel with the word lines WL1l, WL12 etc. and in the form of rows.

One terminal of each clearing MISFET Qc11 Qcr2 Qc21 and Qc22 is connected between the switching MISFET QD1 1 QD11, QD21 and QD22 respectively and the corresponding capacitor CDS11, CDsi2, CDS2 and CDS22, while the other terminal thereof is earthed at G. The gate electrodes GC11, Gci2, GC21 and GC22 of the clearing MISFET Qc11 Qc12 Qc21 and 0c22 respectively are connected to corresponding clearing signal-applying çdc lines fdc1l, dc12, fdc21 and dc22.

In accordance with the embodiment of the present invention, two dummy cells D are provided for each bit line BL. This is intended to exclude the influence of mask misregistration arising in the same direction as the direction in which the bit line BL extends. A DRAM of the folded bit line type includes a memory cell M whose capacitance C5 increases due to mask misregistration in the bit line direction, and a memory cell M whose capacitance C5 decreases due to such misregistration. In order to hold constant the relationship between the capacitances of the two sorts of memory cells M and the dummy cell D, two dummy cells D are provided per bit line.

Also, according to this embodiment of the present invention, the word line WL and the word line DWL desirably have substantially equal resistance values. The resistance of the word line WL or DWL is determined, not only by the resistitivity of a material used, but also by the number of steps attributed to layers underlying the word line WL or DWL, for example, a field insulator film and a capacitor electrode. The resistance in the step is higher than that in a flat region. The resistance of the word line DWL is raised so as to be substantially equal to the resistance of the word line WL. To achieve this, the number of steps under the word line DWL is increased so as to be equal to the number of steps under the word line WL. In equalizing the numbers of steps, the dummy cells numbering two per bit line are used.That is, steps caused by the formation of the capacitors CDS of the adjacent dummy cells are used.

Figures 7 and 8 are plan views showing parts of the dummy cell during the manufacture of the DRAM in Figure 5.

As shown in Figure 7, a field insuialor film (SiO2 film) 3 is formed on a silicon semiconductor substrate 2 by selective thermal oxidation of the major surface thereof. The capacitor portion 4 of a dummy cell 1 is shaped to be vertically symmetric with respect to a base line m-m. An angle Q defined between the base line m-m and an oblique line n-o is 450. The base line m-m and line m1-m1 are parallel, and are separated by a distance H 2 The shape of the capacitor portion 4 is similar to that of the capacitor portion of a memory cell. The gate electrode (GD) of a MISFET is formed in a region 9, and the gate electrode (Gc) of a clearing MISFET is formed in a region 10.

After the step illustrated in Figure 7, a capacitor electrode 5 is formed over the capacitor portion 4 of the semiconductor substrate with a thin insulator film intervening therebetween as shown in Figure 8. One part of the capacitor electrode 5 near to the region 9 for forming the gate electrode of the MISFET is cut away or notched. This causes a line q-q bending at points u, to intersect orthogonally the base line m-m at a pont p and to intersect orthogonally the oblique lines n--o at points r. The height from the base line m-m to the point r is H. The position of the point u can be chosen in dependence upon the capacitance of the memory cell, the degree of mask misregistration, etc.

Another part (line q1-q1) of the capacitor electrode 5 intersects orthogonally the base line m-m and the line m1-m1. The intersection points between the lines mamma and the line q1-q1 are points r,.

Figures 9 and 10 are respectively a plan view, showing the parts of the dummy cell of the DRAM in Figure 5, and a plan view showing parts of the memory cell thereof. A field insulator film formed on a semiconductor substrate defines the shapes of the capacitor portions of the dummy cell and memory cell, that is, the shapes of the lower-layer electrodes of the capacitors of the dummy cell and memory cell (hereinafter referred to as the underlying patterns). The fluctuations of the capacitances of the capacitors in the case of misregistration of the underlying patterns will now be described.

Figure 9 shows the dummy cell 1 which has been formed on the basis of Figure 8. It is assumed that the capacitor electrode 5 has a misregistration Ax within an allowable error on the base line m-m relative to the underlying pattern of the dummy cell 1.

Applying Equations (4), (5) and (6), the areas ASm and ASm1 produced by the mask misregistration Ax are: Ax2 ASm=2(Ax.H+ ) (4-1) 4 H ASm1=2(Ax.-) (5-1) 2 The area ASm causes a decrease in the capacitance, whereas the area ASm1 causes an increase in the capacitance. The total area ASt becomes: Ax2 ASt=ASm+ASm1=-(Ax.H+ 2 (6-1) The variation of capacitance due to the mask misregistration is proportional to ASt indicated by Equation (6-1).

Figure 10 shows the capacitor portion of the memory cell 6 which has been formed in the region demarcated by the field insulator film 3A, on the basis of Figure 3A.

The distance between points í which are the intersection points between the oblique lines c-e of the memory cell 6 and the line h-h of the capacitor electrode 5A, is 2H.

The field insulator films 3 and 3A, and the capacitor electrodes 5 and 5A are formed simultaneously, so that any misregistration Ax of the capacitor electrode 5A on the base line a-a is the same as that of the capacitor electrode 5.

When the area ASa produced by the mask misregistration is evaluated by applying Equation (2), it is: Ax2 ASa=2(Ax.h+ ) (2-1) 2 The area ASa causes a decrease in the capacitance of the memory cell 6. Therefore the area ASa of Equation (2-1) becomes: ASa=-(2.Ax.H+Ax2) (2-2) The variation in capacitance due to the mask misregistration is proportional to ASa indicated by Equation (2-2).

As indicated by Equation (2-2) and Equation (6-1), due to the formation of the dummy cell 1 and the memory cell 6 the variation of the capacitances of the dummy cell 1 and memory cell 6 due to the mask misregistration can be made 1:2 at all times. The respective capacitance values are set substantially at 1:2 in advance, and also the variations can be 1:2. Thus, Equation (1) is met. Therefore, the absolute values of the difference between the quantity of charge in the dummy cell 1 and the quantity of charge in the memory cell 6 at signal "0" and the difference between the former and the quantity of charge in the memory cell 6 at signal "1" are always equal.

In this way, the maximum margins in signal reading operations are obtained for both the signal "0" and "1". Thus malfunctions in the signal reading operations may be prevented, and the reliability of the DRAM can be enhanced.

Figures 1 1, 13 and 15 are plan views showing parts of the dummy cells during manufacture, the dummy cells being arranged on a semiconductor substrate. These figures illustrate in more detail the layout of the dummy cells of the DRAM in Figure 5. Similarly, Figures 12, 14 and 16 are plan views showing parts of the memory cells during manufacture, the memory cells being arranged on the semiconductor substrate. These Figures also illustrate in more detail the layout of the memory cells of the DRAM in Figure 5. For brevity, interlayer insulator films between conductors, e.g.

wiring, are not shown.

Figures 1 1 and 12 show the state in which the field insulator films have been formed in the regions of the dummy array and memory array.

As shown in Figure 1 1, a field insulator film (SiO2 film) 3 formed on one major surface of a ptype silicon semiconductor substrate 2 by selective thermal oxidation thereof defines regions to form dummy cells 1 and regions to form wiring regions 11 for connecting MISFETs 0c to earth. Pairs of dummy cells 1 are arrayed in the form of rows (in the vertical direction as viewed in the figure) with predetermined equal pitches. In each row, the dummy cells 1 extend in alternate directions, while in an adjacent row, the directions are opposite to the corresponding cell in the first row. Thus a regular dummy array is formed. The shape of the region of the semiconductor substrate serving as the lower-layer electrode of the capacitor CDS of each dummy cell 1 is defined by the field insulator film 3.

As shown in Figure 12, regions forming memory cells 6 are defined by a field insulator film 3A which is formed simultaneously with the field insulator film 3. The memory cells 6 forming the memory array are arranged in pairs, the cells of each pair extending in opposite directions. In order to achieve enhancement in the density of integration, etc., adjacent memory cells 6 are in the row have alternate directions. The shape of the region of the semiconductor substrate serving as the lower-layer electrode of the capacitor C5 of each memory cell 6 is defined by the field insulator film 3A.

Capacitor electrodes made of a polycrystalline silicon, being a first conductor layer and serving as the upper-layer electrodes of the capacitors, are formed as illustrated in Figures 13 and 14. As shown in Figure 13, the capacitor electrodes 5 extend in the form of rows over the dummy cells 1 and which are common in the row direction. One end of each capacitor electrode 5, at the side of a gate electrode forming region 9 is formed into a notch and the other end at the side of a gate electrode forming region 10 is formed by a straight line, as described before. The capacitor electrode 5 has a deviation Ax in the direction of data lines with respect to the underlying pattern due to a mask misregistration.

Capacitor electrodes 5A are formed over the parts of the memory cells 6 other than gate electrode portions and bit line connecting portions 8 as shown in Figure 14 in the same manufacturing step as that illustrated in Figure 13. Similarly to the capacitor electrode 5, the capacitor electrode 5A has a deviation Ax with respect to the underlying pattern. A voltage Vss is applied to the capacitor electrodes 5 and 5A.

Then wiring leads, such as word lines, made of a second conductor layer are formed as illustrate; in Figures 15 and 16. As shown in Figure 15, a word line 12 (DWL") and dc line 13 which correspond to the dummy cell 1 (D") are formed as a row. Likewise, the word lines DWL,2, DWL and DWL22 and fdc lines Xdc12, Xdc21 and doc22 are formed as rows. The word lines DWL", DWL,2, DWL21 and DWL22 serve as gate electrodes Gull, Gel2, GD21 and GD22, respectively.

The fdc lines 0dc1l, doc12, ~dc2l and fdc22 serve as gate electrodes Gc11,Gc12, GC21 and Go22, respectively.

A polycrystalline silicon layer; a layer of a highmelting metal such as molybdenum, tungsten tantalum or titanium; a layer of silicide of a highmelting point metal; or a double-layer structure which consists of a polycrystalline silicon layer and a high-melting point metal layer or highmelting point metal silicide layer overlying it may be used to form the second conductor layer.

An impurity is introduced into the regions of the semiconductor substrate 2 in which the capacitor electrodes 5, word lines 12, fdc lines 13 and field insulator films 3 are not formed, thereby to form n±type semiconductor regions.

Thus, the dummy cells 1 each consist of MISFETs QD and QC In addition, wiring leads 1 1 A(G) made of n±type regions which connect the MISFETs Qc to earth are formed. Thereafter, the bit lines 14 made of aluminium are formed as columns and are connected to the dummy cells 1 through contact holes 16. The bit line 14 which is connected to the dummy cells D11 and D12 is shown at BL" while the bit line 14 which is connected to the dummy cells D2, and D22 is shown at BL2. The bit lines are those shown in Figure 6.

In the same manufacturing step as that illustrated in Figure 15, a word line 15 (WL1) corresponding to the memory cell 6 (M") is formed as a row as shown in Figure 16. Similarly rows of word lines WL12,WL21 and WL22 are formed as rows. The word lines WL", WL12, WL and WL22 serve as gate electrodes G", G,2, G21 and G22, respectively. Thereafter, an impurity is introduced into the regions of the semiconductor substrate 2 in which the capacitor electrodes 5A, word lines 15 and field insulatorfilm 3 are not formed, thereby to form n±type semiconductor regions.Thus, the memory cells 6 each consist of MISFETs O. Thereafter, the bit lines 14 are formed as rows and are connected to the memory cells 6 through contact holes 17. The bit line 14 which is connected to the memory cells M11 and M12 is again shown at BL, while the bit line 14 which is connected to the memory cells M21 and M22 is again shown at BL2. The bit lines are the same as those shown in Figures 15 and 6, and they extend straight between the sense amplifier and the dummy cells as shown in Figure 6.

In the present embodiment, the resistances of the word lines WL and DWL are substantially equal. The reason for this will be now explained with reference to Figures 15 and 16.

The four bit lines 14 in Figure 1 5 are the same as those in Figure 16. This is apparent when note is taken of the bit lines BL1 and BL2. The bit lines extend straight in the memory array and the dummy array. In other words, the distances between the bit lines are equal in Figures 15 and 16.

Now, note is taken of the word lines WL1l and DWL11. The numbers of steps underlying the word lines WL,, and DWL12 between the bit lines BL, and BL2 are equal. The steps are formed by the field insulator films 3, 3A and the capacitor electrodes 5, 5A. As seen from Figures 15 and 1 6, whichever word lines WL and DWL are noted, the numbers of the steps due to the underlying field insulator films and the numbers of the steps due to the underlying capacitor electrodes are equal.

In order to equalize the numbers of the steps due to the field insulator films, the field insulator film of the dummy cells is laid out as shown in Figure 1 1. In order to equalize the numbers of the steps due to the capacitor electrodes, the capacitor electrodes of the dummy cells are laid out as shown in Figure 13. From this viewpoint, whether or not the region which adjoins in the extending direction of the word line DWL and in which the field insulator film is not formed acts as the capacitor CDS is not relevant.

A thin deposit of material forms the word line.

Therefore, the cross-sectional area of the word line decreases and the resistance becomes higher than in a flat region. It is accordingly important to equalize the numbers of the steps.

Whether the step is large or small, and whether it is steep or gentle are also important. Thus, the numbers of the steps need to be equalized for the corresponding field insulator films and capacitor electrodes.

The present invention is particulariy effective when the material of the word line, is at least partially a high-melting metal or a silicide thereof.

In the step, the high-melting metal layer becomes thinner than the polycrystalline silicon layer. This holds whatever method of deposition is employed. The use of polycrystalline silicon is effective for enhancing the reliability of the device.

The present invention results in an increase in the resistance of the word line DWL relative to the prior art so that it is substantially equal to the resistance of the word line WL. The present invention, however, does not reduce the operating speed in spite of the increase of the resistance and therefore a significantly more reliable device may be achieved.

To widen the margin of the read-out of information from the memory cell, the dummy cell needs to be driven later than the memory cell. On the other hand, transient phenomena on the word lines WL and DWL are approximate. When the resistance of the word line DWL is lower than that of the word line WL, the dummy cell is driven earlier than the memory cell. In consequence, when the information is at the low level "0" signal), it is difficult to set the timing of the read out and the margin of the read-out narrows.

When the information is at the high level ("1" signal), there is no problem. Since the resistances of the word lines WL and DWL are substantially equal, the margin at the read-out of the information can be widened, and the timing of the read-out can be set easily.

The operation of the DRAM in Figure 5 will now be described with reference to Figures 6, 15 and 16. In particular, explanation will be given of how signal reading operations are affected where capacitor electrodes have involved mask mis registrations relative to the underlying patterns of dummy cells and memory cells formed on an identical semiconductor substrate.

Assume the "0" (low level) signal is written into the memory cell 6 (M"). A voltage of OV is applied to the bit line 14 (BL1), and a voltage Vcc is applied to one word line 15 (WL1l). Then, the MISFET Q11 is turned "on", and charge corresponding to the voltage of the bit line 1 4 (BL1) is stored in the capacitor portion 7 (C") of the memory cell 6 (M1l). Simultaneously, when the voltage Vcc is applied to one dummy word line 12 (DWL22), the MISFET QD22 is turned "on", and charge corresponding to the voltage of the bit line 14 (BL2) is stored in the capacitor portion 4 (CD22) of the dummy cell 1(D22). The voltage VCc=5V is applied to the bit line BL2.In the dummy cell 1 and the memory cell 6, the respective capacitor electrodes 5 and 5A have mask misregistrations of equal magnitudes in the same direction from their design values with respect to the thin insulator film which is formed in the region enclosed with the field insulator film 3. However, the capacitance values of the dummy cell 1 (D22) and the memory cell 6 (my,) are at 1:2 at all times. In the reading operation of the "0" signal written in the memory cell 6 (M,1), the voltage Vcc is applied to the bit lines 14 (BL1 and BL2), and also the voltage Vcc is applied to the word line 15 (WL"). The charge stored in the capacitor portion 7 (C") is discharged to the bit line 14 (BL). Simultaneously, the voltage Vcc is applied to the word line 12 (DWL22).Charge stored in the capacitor portion 4 (CD22) is discharged to the bit line 14 (BL2). The small potential difference between the bit lines 1 4 (BL1 and BL2) is amplified by the sense amplifier SA, whereby the "0" signal can be read out.

Likewise, the dummy cell D2, corresponds to the memory cell M12, the dummy cell D12 to the memory cell M21, and the dummy cell D to the memory cell M22. The reading operation of the "1" (high level) signal can be similarly executed.

The memory cells include ones in which the areas of the capacitors C5 increase due to mask misregistration in a column direction (in Figures 7 to 12, the lateral direction), and ones in which they decrease. In order to hold the capacitance ratio at a predetermined value at all times, the dummy cells correspondingly include ones whose capacitances CDS increase due to misregistration in the column direction and ones whose capacitances decrease. The memory cell and dummy cell having the same direction of misregistration are selected, and are connected to the same sense amplifier by a pair of data lines (complementary data line pair). There are four dummy cells per sense amplifier. They are arranged as shown in the figure for enhancement in the density of integration, etc.

The capacitance of the dummy cell 1 fluctuates at a fixed proportion in correspondence with the fluctuation of the capacitance of the memory cell attributed to mask misregistration, so that the absolute values of the small potential differences in all signal reading operations are equal. That is, the maximum margins in the signal reading operations can be obtained at all times, and it is possible to prevent malfunctions in the signal reading operations and to enhance the reliability of the DRAM.

Figure 17 is a graph showing how the capacitance ratios between the dummy cells and memory cells fluctuate due to mask misregistrations within an allowable error (+ 1.2 ,um) in the DRAM of the present invention and the DRAM of the prior art.

The abscissa axis represents the magnitude of mask misregistrations (um) of the capacitor electrodes in the column direction (in Figures 7 to 16, the lateral direction) relative to the underlying pattern of dummy cells and memory cells.

The ordinate axis represents in % the degree to which the capacitance ratios (CDs/Cs) between the dummy cells and memory cells fluctuate due to mask misregistrations. Curve D-1 indicates data from the DRAM according to the present invention where no mask misregistration has occurred in the row direction (in Figures 7 to 16, the vertical direction. Curve D-2 indicates data from a DRAM according to the present invention, where a mask misregistration of +1.2 ym has occurred in the row direction. Curve D-3 indicates data from a prior-art DRAM where no mask mis registration has occurred in the row direction.

Curve D-4 indicates data from the prior-art DRAM where a mask misregistration of +1.2 jum has occurred in the row direction.

According to the present invention, even when the mask misregistration in the column direction has been involved, the capacitance ratio between the dummy cell and the memory cell may have a fixed value. In addition, even when the mask misregistrations in the column direction and row direction occur, the capacitance ratio between the dummy cell and the memory cell is fixed. The capacitance ratio between the dummy cell and the memory cell in the prior-art DRAM fluctuates greatly due to mask misregistrations in the column direction. In particular, the fluctuation of the capacitance in the part of the maximum allowable error is particularly significant.

Figures 18 and 19 are plan views of parts of one memory cell and one dummy cell for explaining a second embodiment of the present invention.

As shown in Figure 18, the capacitor CDS of a dummy cell 1 is bounded by a field insulator film 3 formed on a semiconductor substrate 2. The capacitor portion 4 of the dummy cell 1 is square.

A part for connection to a bit line protrudes from one end of the capacitor portion 4, and a region 9 for forming the gate electrode of a MISFET each have a width H and a pane for connection to earth protrudes from the other end and a region 10 for forming the gate electrode of a clearing MISFET each have a width of H/2. A capacitor electrode 5 forms the capacitor of the dummy cell 1. One side of the capacitor electrode 5 is disposed over the portion of the gate electrode forming region 9 of the MISFET, while the other side is disposed over the portion of the gate electrode forming region 10 of the clearing MISFET. The increase and decrease of area due to a mask misregistration are within the parts protruding from the capacitor portion 4.

As shown in Figure 19, the capacitor C5 of a memory cell 6 is bounded by a field insulator film 3A formed on the semiconductor substrate 2. The capacitor portion 7 of the memory cell 6 is pentagonal. A gate electrode and bit line connecting part 8 which protrudes from a part of the capacitor portion 7 each have a width H. A capacitor electrode 5A forms the capacitor Cs of the memory cell 6, and which extends over the part of a memory array other than the gate electrode and bit line connecting portion 8. The capacitor electrode 5A is arranged over a region which has the same width as that of the region forming the gate electrode and bit line connecting portion 8. The increase and decrease of area due to a mask misregistration occur within the region defined by the parallel parts of the insulator film 3A.

Since the dummy cell 1 and the memory cell 6 are formed in the same manufacturing step, the capacitor electrodes 5 and 5A have deviations of equal magnitude in the same direction. When mask misregistration in the row direction (x) occurs, the capacitance ratio between the dummy cell 1 and the memory cell 6 remains 1:2 as seen from Figures 18 and 19. As in the foregoing embodiment, the DRAM can enhance the margins in signal reading operations and can enhance the reliability thereof.

According to the present invention, when capacitor electrodes have deivated relative to underlying patterns in a DRAM, the ratio of the capacitances of a dummy cell and a corresponding memory cell can be held constant.

Thus, the maximum margins in signal reading operations can be attained. It is thus possible to reduce malfunctions in the signal reading operations and to enhance the reliability of the semiconductor device.

The shape of the underlying pattern of the part of the dummy cell causing the fluctuation of the capacitance ratio is made similar to that of the underlying pattern of the part of the memory cell causing the fluctuation of the capacitance ratio, whereby even when the capacitor electrodes have developed mask misregistrations relative to the underlying patterns, the capacitance ratio between the dummy cell and the memory cell can be held constant at all times.

An angle defined between the edge of the underlying pattern of the part of the dummy cell causing the fluctuation of the capacitance ratio and that of the capacitor electrode, and an angle defined between the edge of the underlying pattern of the part of the memory cell contributive to the fluctuation of the capacitance ratio and that of the capacitor electrode are rendered any of 450, 900, 1350, 2250,2700 and 3150, whereby even when the capacitor electrodes have developed mask misregistrations, the capacitance ratio between the dummy cell and the memory cell may be constant at all times.

According to the present invention, in a DRAM, the resistance of a word line for driving the switching MISFET of a memory cell may be made substantially equal to that of a word line for driving the switching MISFET of a dummy cell.

The present invention is not restricted to the foregoing embodiments.

In the foregoing embodiments, the electrodes of all capacitors consist of semiconductor substrate parts defined by field insulator films and a polycrystalline silicon layer. The electrode of the capacitor may be constructed with upper and lower layers of polycrystalline silicon. If the capacitor electrode is formed by the use of the two polycrystalline silicon layers, the capacitor can be partly disposed on the field insulator film and/or over the gate electrode of a switching MISFET. A conductor other than polycrystalline silicon may also be used.

The capacitor can be formed within a moat formed in a semiconductor substrate. In this case, the electrodes of the capacitor consist of the major surface of the semiconductor substrate as well as the surface of the semiconductor substrate within the moat, and a conductor layer, e.g., polycrystalline silicon layer over them.

The present invention is also applicable to a DRAM of the open bit line type. The shape of the capacitor of a dummy cell is determined from consideration of the shape of the capacitor of a memory cell and the magnitude of fluctuation of area due to a mask misregistration. Two dummy cells are provided for each bit line. Word lines are formed of aluminium, and the numbers of steps under them are equalized. The steps under the word line are due to a field insulator film, capacitor electrodes, and the gate electrodes of switching MISFETs. The same steps in the equal numbers exist under the respective word lines.

It is to be understood that the above-described arrangements are simply illustrative of the application of the principles of this invention.

Numerous other arrangements may be readily devised by those skilled in the art.

Claims (23)

1. A semiconductor memory device comprising: a semiconductor substrate; memory cells in rows and columns on the semiconductor substrate each of which includes a first MISFET and a first capacitor connected in series with the first MISFET, the first capacitor having first and second electrodes; dummy cells on the semiconductor substrate, each of which includes a second MISFET and a second capacitor connected in series with the second MISFET, the second capacitor having third and fourth electrodes and having a capacitance substantially half that of the first capacitor; bit lines in columns over the semiconductor substrate and which are connected to the first and second MISFETs; word lines in rows over the semiconductor substrate and which intersect the bit lines;; wherein the magnitude of fluctuation of area of the second capacitor due to a deviation of said fourth electrode relative to said third electrode being a fixed proportion of the magnitude of fluctuation of area of the first capacitor due to a corresponding deviation of the second electrode relative to the first electrode.

2. A device according to Claim 1 , wherein the magnitude of fluctuation of area of the second capacitor is substantially half that of the magnitude of fluctuation of area of said first capacitor.

3. A device according to Claim 1 or Claim 2, wherein the shape of the third electrode is substantially similar to that of the first electrode.

4. A device according to any one of Claims 1 to 3, wherein the first electrode is a part of the semiconductor substrate defined by an insulator film on the semiconductor substrate, and the second electrode is formed by a polycrystalline silicon layer extending over the semiconductor substrate.

5. A device according to Claim 4, wherein the third electrode is a part of the semiconductor substrate defined by the insulator film on the semiconductor substrate, and the fourth electrode is formed by the polycrystalline silicon layer extending over the semiconductor substrate.

6. A device according to any one of the preceding claims, wherein an angle at which the third electrode and the fourth electrode intersect on a side of the second MISFET is in a fixed relation to an angle at which the first electrode and the second electrode intersect on a side of the first MISFET.

7. A device according to Claim 6, wherein the angle of intersection of the third electrode and the fourth electrode is 900, and that of the first electrode and the second electrode is 450.

8. A device according to any one of the preceding claims, wherein each bit line is connected to two dummy cells.

9. A device according to Claim 8, wherein the fluctuation of area of the second capacitor of one of the dummy cells connected to each bit line is in the opposite sense to that of the second capacitor of the other dummy cell connected to each bit line, for the same deviation of the fourth electrode relative to the third electrode.

10. A semiconductor memory device comprising: a semiconductor substrate; memory cells in rows and columns on the semiconductor substrate, each of which includes a first MISFET and a first capacitor connected in series with the first MISFET, the first capacitor having first and second electrodes; dummy cells on the semiconductor substrate, each of which includes a second MISFET and a second capacitor connected in series with the second MISFET, the second capacitor having third and fourth electrodes; bit lines in columns over the semiconductor substrate and which are connected to the first and second MISFETs; and word lines in rows over the semiconductor substrate, which intersect the bit lines and which consist of first word lines connected to the first MISFETs and second word lines connected to the second MISFETs, the first and second word lines having substantially equal resistances.

1 1. A device according to Claim 10, wherein equal numbers of steps exist under the first and second word lines.

12. A device according to Claim 10 or Claim 11, wherein substantially the same steps exist under the first and second word lines.

13. A device according to any one of Claims 10 to 12, wherein a part of each first word line extends over the first capacitor.

14. A device according to any one of Claims 10 to 1 3, wherein a layer formed simultaneously with the first electrodes and a layer formed simultaneously with the second electrodes exist under the second word lines.

15. A semiconductor memory device according to Claim 13, wherein a part of each second word line extends over the second capacitor.

16. A semiconductor memory device according to any one of claims 10 to 15, wherein the first and third electrodes are formed simultaneously, and the second and fourth electrodes are formed simultaneously.

17. A semiconductor memory device according to any one of Claims 10 to 16, wherein the first and third electrodes are formed by the semiconductor substrate, and the second and fourth electrodes are polycrystalline silicon layers.

18. A device according to any one of claims 10 to 17, where first and second word lines are made of the same material.

19. A device according to Claim 18, wherein the material of the word lines includes a highmelting point metal.

20. A device according to Claim 18, wherein the material of the word lines includes a silicide of a high-melting point metal.

21. A semiconductor memory device according to any one of Claims 10 to 20, wherein the first electrode is a part of the semiconductor substrate defined by an insulator film on the semiconductor substrate, the second electrode is formed by a polycrystalline silicon layer on the semiconductor substrate, a part of the first word line extends on the first capacitor, and steps formed by the insulator film and steps formed by the polycrystalline silicon layer exist under the first word line.

22. A device according to Claim 21, wherein the second electrode is a part of the semiconductor substrate defined by the insulator film formed on the semiconductor substrate, the fourth electrode is formed by the polycrystalline silicon layer on said semiconductor substrate, a part of the second word line extends on the second capacitor, and steps formed by the insulatorfilm and steps formed by the polycrystalline silicon layer exist under the second word line.

23. A semiconductor device substantially as any one herein described with reference to and as illustrated in Figures 3 to 19 of the accompanying drawings.