GB2149245A - A.G.C. system - Google Patents

Abstract

A frequency hopping radio receiver is arranged to hop from channel to channel within a predetermined frequency band in a pseudo random fashion and has an a.g.c. system comprising a controllable gain amplifier 1 connected in the RF or IF signal path of a radio receiver, an a.g.c. voltage generator 2 responsive to received signal levels for producing a control voltage which is applied via an a.g.c. line 4 to the controllable gain amplifier thereby to effect an automatic gain control function, memory means 15 effective before each hop to store data appertaining to the a.g.c. voltage which obtains, and to update this data from hop to hop, and comparator means 14a operative to compare data appertaining to the current a.g.c. voltage with stored data appertaining to the a.g.c. voltage which obtained for reception of a previous channel and a.g.c. control voltage modifying means 14, 21, 18, effective to modify the a.g.c. voltage in dependence upon the result of the comparison, so that it approximates to or is derived from the stored a.g.c. voltage whereby prolonged maintenance of the a.g.c. voltage at an unduly high level is obviated. <IMAGE>

Description

SPECIFICATION A.G.C. system This invention relates to a.g.c. (automatic gain control) systems and more especially it relates to a.g. c. systems for frequency hopping radio receivers adapted to hop in a pseudo random fashion from channel to channel within a predetermined frequency band.

For conventional non-hopping radio receivers an a. g. c. system normally comprises a controllable gain amplifier connected in the RF or IF signal path and a control voltage generator operative to produce a feed-back control voltage in accordance with the amplitude, of a signal received, the control voltage being fed back on an a.g.c. line to reduce the gain of the controllable gain amplifier whereby the gain of the radio receiver is controlled automatically in dependence upon the amplitude of a received RF signal.

The time constants associated with the a.g.

c. line are normally arranged to facilitate a rapid rise of the control voltage whereby a.g.c. operation is arranged to be effective with little delay after the reception of a large signal whereas decay of the control voltage is arranged to be slow so that the a.g.c. voltage is maintained during brief reductions of signal level as may occur during amplitude modulated speech transmissions for example.

in frequency hopping radio systems however, known a.g.c. systems of the kind just before described, are not suitable because with a hopping rate involving a channel change about every 100 m.secs., reception of an interfering signal which is larger than the wanted signal on one channel would cause the production of a correspondingly large a.g.c. control voltage which would be maintained due to the long decay time constant, so as to suppress the subsequent reception of wanted signals on other channels hopped to immediately thereafter. In practical terms enough channels are found to be blocked by interfering signals in the HF (High Frequency Bands) for conventional a.g.c. to be unsatisfactory. Moreover a.g.c. is necessary for single sideband modulation which is employed at HF, and therefore the principal field of application for the invention is H.F. S.S.B. frequency hopping receivers.

It is an object of the present invention to provide an a.g.c. system which will operate satisfactorily in a frequency hopping radio receiver.

According to the present invention in a frequency hopping radio receiver adapted to hop from channel to channel within a predetermined frequency band in a pseudo random fashion, an a.g.c. system comprises a controllable gain amplifier connected in the RF or IF signal path of a radio receiver, an a.g.c.

voltage generator responsive to received signal levels for producing a control voltage which is applied via an a.g.c. line to the controllable gain amplifier thereby to effect an automatic gain control function, memory means effective before each hop to store data appertaining to the a.g.c. voltage which obtains, and to update this data from hop to hop, and comparator means operative to compare data appertaining to the current a.g.c.

voltage with stored data appertaining to the a.g.c. voltage which obtained for reception of a previous channel and a.g.c. control voltage modifying means, effective to modify the a.g.c. voltage in dependence upon the result of the comparison, so that it approximates to or is derived from the stored a.g.c. voltage whereby prolonged maintenance of the a.g.c.

voltage at an unduly high level is obviated.

The memory means may be coupled to the a.g.c. line via an A to D converter whereby digital signals appertaining to the a.g.c. control voltage are made available for storage in the memory.

Automatic gain control voltage modifying means may comprise a signal processor, which includes the comparator, the processor being operatively associated with a counter, which is incremented successively, by successive comparisons in which the current a.g.c.

control voltage significantly exceeds the stored a.g.c. control voltage, until a predetermined limit count is reached which is effective to reset the counter, and to which limit count the processor is responsive for allowing the a.g.c.

control voltage to settle freely to a new level.

The comparator may operate to compare the stored data with the current data by subtracting the a.g.c. voltage as represented by the current data from the a.g.c. voltage as represented by the stored data so as to provide data indicative of a difference voltage, and by providing an output to increment the counter if the difference voltage exceeds a predetermined constant value.

In addition to the signal processor, the automatic gain control modifying means may include a D to A converter. This accepts an input from the signal processor representing the desired a.g.c. voltage. The output of the D to A converter is enabled by the signal processor when it is required to modify the a.g.c.

voltage.

One embodiment of the invention will now be described by way of example with reference to the accompanying drawings in which: Figure 1 is a somewhat schematic block diagram of an a.g.c. system for a frequency hopping radio receiver; Figure 2 is a flow diagram illustrating operation of the a.g.c. system shown in Figure 1; Figure 3 is a wave form diagram showing the wave forms which obtain during operation of a conventional a.g.c. system, and Figure 4 is a wave form diagram showing the wave forms which obtain during operation of the a.g.c. system shown in Figure 1.

Referring now to Figure 1, an a.g.c. system comprises a variable gain amplifier 1 and an a.g.c. voltage generator 2 connected in a feedback loop. In operation of the system an input signal is fed via an input line 3 to the variable gain amplifier 1 and the a.g.c. voltage generator 2 is adapted to provide a feedback a.g.c. control voltage on a line 4 in dependence upon the signal amplitude present on an output line 5 from the variable gain amplifier 1. The system thus far described is well known and the time constants of the system are usually arranged such that the a.g.c. voltage generator 2 responds promptly to reduce the gain of the variable gain amplifier 1 when a large signal 3 suddenly appears but responds only slowly to restore conditions if the input signal on the line 3 is suddenly reduced.

It will be appreciated that with the a.g.c.

system just before described operation of the system in a frequency hopping radio would be virtually impossible since with a receiver which is arranged to hop from channel to channel every 100 m. sec., the reception of a large interfering signal on one channel would impair the subsequent reception of a wanted signal on a number of following channels immediately thereafter hopped to. The reason for this is that the a.g.c. voltage developed on the interfering signal would serve to suppress the gain of the receiver on the following channels which require a lower a.g.c. voltage appropriate to the level of the wanted signal.

The foregoing disadvantage is clearly illustrated in Figure 3 wherein an input signal shown by a wave form 6 is hopped from channel to channel every 100 m.secs. At the 200 m. sec. hop, a large interfering signal 7 is received which causes the a.g. c. voltage as represented by a wave form 8 to rise sharply at the point 9. The audio output from the receiver briefly responds to provide an output signal peak 10 but since the a.g.c. rise time constant is short the a.g.c. very quickly takes over and the audio output signal quickly returns to a normal level 11. At the 300 m.

sec. hop, the next channel is hopped to whereat the signal level 7a is normal, but since the a.g.c. voltage decay time constant is long, the a.g.c. voltage stays high and accordingly the gain of the receiver is suppressed so that the audio output signal level is undesirably suppressed to a level 1 2.

In order to overcome this problem, additional apparatus is provided as shown within the broken line 1 3 in Figure 1.

The apparatus comprises a signal processor 14, a data memory 15, a counter 16, an A to D converter 17, and a D to A converter 18.

The memory 1 5 serves to store data appertaining to the a.g.c. level present during channel reception preceding the last hop. The stored a.g. c. voltage is herein referred to as VM. The a.g.c. level is sensed by the A to D converter 1 7 and presented in digital form to the memory 15 via a line 19. The A to D converter 1 7 also provides the processor 14 with data appertaining to a currently received channel and signifying the currently received a.g.c. level VR.The processor 14 includes a comparator 1 4a which serves to compare the currently received a.g.c. voltage level VR with the stored a.g.c. voltage level VM and if the currently received level is substantially higher than the previously received level then the processor provides a signal representing the desired a.g.c. voltage via a line 21 to the D to A converter 18, and a signal to enable the output of the D to A converter 1 8 on line 25.

The a.g.c. voltage present on the a.g.c. line 4 is then forced down to a more appropriate level which corresponds to the level stored less a small offset voltage VO. If a comparison indicates that VR-VM > VD where VD is the small constant voltage, the channel is assumed to be 'blocked'.

Each time a 'blocked' channel is detected as the result of a comparison, the counter 1 6 is incremented via a line 22 but reset via a line 23 consequent upon reception of an unblocked channel i.e. VR-VM < VD. If the counter 1 6 is incremented a predetermined consecutive number of times such that a predetermined limit count is reached, then the counter 1 6 is arranged to provide a limit detection signal on an output line 24 for the processor 14; the counter is reset to zero and the a.g.c. voltage is adjusted to a new level.

The sequence of operations just before described are necessary since reception by the system of more than a predetermined number of 'blocked' channels would tend to indicate that a new high level transmission is being received and accordingly the a.g.c. voltage must be allowed to settle to a (higher) level appropriate to the new transmission so that it can be received successfully.

Operation of the system as just before described with reference to Figure 1 will be better understood from the flow diagram shown in Figure 2 which will now be discussed. The system operates as follows assuming one hop every 100 m.secs. At a time TR, say 70 m.secs. after the last hop, the processor operates to read the a.g. c. voltage VR. VR is compared with VM which is the a.g.c. voltage stored in the memory 1 5 and appertaining to a previously received channel.

If VR is greater than VM by the constant factor VD then a 'yes" path 25b in Figure 2 is followed and it is assumed that the currently received channel is 'blocked' by a new transmission or an interfering signal. If however the currently received a.g.c. level is substantially the same as, or smaller than the previously received a.g.c. level, a 'no' path 25a will be followed and it will be assumed that the channel is clear. If a channel is deemed 'clear' an a.g.c. flag in the processor 14 will be set to '0' and the counter 1 6 will be reset to zero if it is not already at zero. The memory 1 5 will be reset to the a.g.c. voltage VR measured such that VM = VR. At a time TW after the next hop which might be about 10 m.secs. the state of the a.g.c. fflag is acted upon.Since the a.g.c. flag was set to 'O' no a.g.c. signal will be applied via the D to A converter 18 to the a.g.c. line 4.

If the 'yes' line 25b were followed, indicating that an interfering signal or a new transmission was being received, then provided the counter 1 6 hadn't reached its limit count then the branch line 25c would be followed; the counter 1 6 would be incremented, and the a.g.c. flag would be set to '1'. Then at the time TW after the next hop, which is about 10 m.secs., since the a. g.c.

flag was set to '1', the processor will enable the output of the D to A converter 18 such that an appropriate a.g.c. level of VM-VO, where VO is a small offset voltage, is imposed for say 5 m.secs. on the a.g.c. line 4, such that the voltage on a.g.c. line 4 is forced down whereby a wanted signal could be received.

If however following the line 25b the counter had been incremented to its limit count, then the branch 25d would be followed; the counter 1 5 would be set to zero and the a.g.c. fflag set to 'O'. Since the state of the a.g.c. flag was '0' at the time TW after the next hop i. e. about 10 m.secs. the write a.g.c. sequence would not be implemented and thus the new high level of a.g.c. on the a.g.c. line 4 would be allowed to be maintained, and stored in the memory 1 5. This is because it would be assumed that the new high level of a.g.c. would be appropriate and due to a new high level wanted received signal.

Operation of the system just before described will be better understood from a consideration of the wave form diagram shown in Figure 4 wherein a received input signal wave form 26 is shown which corresponds with the wave form 6 shown in Figure 3. In Figure 3 it was shown that the reception of the input signal wave form was interfered with by a.g.c.

operation whereas it will now be demonstrated with reference to Figure 4 that the same input signal wave form can be successfully received due to operation of the a.g.c.

control system just before described with reference to Figures 1 and 2.

At the 100 m. sec. hop a new channel is hopped to. 70 m.secs. later, at a point 27, the a.g.c. voltage VR is read at the point 28 and compared with a stored value which obtained at a point 29, 70 m.secs. after the 100 m.sec. hop. Since these two values of a.g.c. voltage are substantiallv the same, their difference will not exceed the constant voltage VD and so the left hand path 23 will be followed in Figure 2 and a channel clear situation will be deemed to obtain. Accordingly the counter 1 6 will be set to zero and the a.g.c. flag set to 'O'. The memory 1 5 will be updated to the voltage which obtains at the point 28. At the 200 m.sec. hop 30, a new channel will be hopped to and a high level signal 31 will be received.Accordingly the a.g.c. voltage will rise to a level 32 and the output audio signal will rise briefly to a point 33 until the a.g.c. takes control and then fall to a more normal level due to a.g.c.

operation. At a point 34, 10 m.secs. after the 200 m.sec. hop, no action will be taken by the D to A converter 1 8 to modify the a.g.c.

voltage on the line 4 since the write a.g.c.

flag will have been set to 'O'. At a point 35, 70 m.secs. after the 200 m.sec. hop 30, the a.g.c. voltage VR will be read and compared with the previously recorded and stored a.g.c.

voltage at the point 28. Since the a.g.c.

voltage at the point 35 is substantially higher than the a.g.c. voltage at the point 28 the right hand line 25b in Figure 2 will be followed, the counter 1 6 will be incremented; path 25c will be followed and the write a.g.c.

flag will be set to '1'. At the 300 m.sec. hop which is a point 36, a new channel will be hopped to and a new low input signal level 37 will be received which is substantially lower than the previously received signal level 31. The gain will initially be turned hard down because the a.g.c. voltage will initially be high in the region 38, but 10 m.secs. after the channel hopping point 36, the D to A converter 1 8 will be constrained to turn the a.g.c. voltage on the line 4 down to a level 33 and accordingly the audio output signal will fall correspondingly whereby a.g.c. 'blocking' is obviated.

The rest of wave forms of Figures 3 and 4 are believed to be self-explanatory and it can be seen that a substantial difference obtains between operation without apparatus according to the invention and shown in Figure 3 and with apparatus according to the invention as shown in Figure 4. Thus it can be seen from Figure 4 that a.g.c. 'blocking' is substantially obviated and reception facilitated in a frequency hopping radio receiver.

Claims (8)

1. In a frequency hopping radio receiver adapted to hop from channel to channel within a predetermined frequency band in a psuedo random fashion an a.g.c. system comprising a controllable gain amplifier connected in the RF or IF signal path of a radio receiver, an a.g.c. voltage generator responsive to received signals levels for producing a control voltage which is applied via an a.g.c. line to the controllable gain amplifier thereby to ef fect an automatic gain control function, memory means effective before each hop to store data appertaining to the a.g.c. voltage which obtains, and to update this data from hop to hop, and comparator means operative to compare data appertaining to the current a.g.c.

voltage with stored data appertaining to the a.g.c. voltage which obtained for reception of a previous channel and a.g.c. control voltage means, effective to modify the a.g.c. voltage in dependence upon the result of the comparison, so that it approximates to or is derived from the stored a.g.c. voltage whereby prolonged maintenance of the a.g.c. voltage at an unduly high level is obviated.

2. An a.g.c. system as claimed in claim 1 wherein the memory means is couplied to the a.g.c. line via an A to D converter whereby digital signals appertaining to the a.g.c. control voltage are made available for storage in the memory.

3. An a.g.c. system as claimed in claim 1 or claim 2 wherein the automatic gain control voltage modifying means comprises a signal processor which includes a comparator the processor being operatively associated with a counter, which is incremented successively by successive comparisons in which the current a.g.c. control voltage significantly exceeds the stored a.g.c. control voltage, until a predetermined limit count is reached which is effective to reset the counter, and to which limit count the processor is responsive for allowing the a.g.c. control voltage to settle freely to a new level.

4. An a.g.c. system as claimed in claim 3 wherein the comparator operates to compare the stored data with the current data by subtracting the a.g.c. voltage as represented by the current data from the a.g.c. voltage as represented by the stored data so as to provide data indicative of a difference voltage, and by providing an output to increment the counter if the difference voltage exceeds a predetermined constant value.

5. An a.g.c. system as claimed in claim 3 or claim 4 wherein in addition to the signal processor the automatic gain control modifying means includes a D to A converter which accepts an input from the signal processor representing the desired a.g.c. voltage.

6. An a.g.c. system substantially as herein before described with reference to the accom panying drawinqs.

7. A frequency hopping radio receiver including an a.g.c. system as claimed in any preceding claim.

8. Radio communication apparatus includ ing a frequency hopping radio receiver as claimed in claim