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GB2149574A - Semiconductor device and process of manufacture thereof - Google Patents
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GB2149574A - Semiconductor device and process of manufacture thereof - Google Patents

Semiconductor device and process of manufacture thereof Download PDF

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Publication number
GB2149574A
GB2149574A GB08428394A GB8428394A GB2149574A GB 2149574 A GB2149574 A GB 2149574A GB 08428394 A GB08428394 A GB 08428394A GB 8428394 A GB8428394 A GB 8428394A GB 2149574 A GB2149574 A GB 2149574A
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United Kingdom
Prior art keywords
electrically
wiring
conductive layer
semiconductor device
regions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB08428394A
Other versions
GB8428394D0 (en
Inventor
Izumi Tezuka
Shigeo Ishii
Tohru Inaba
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Hitachi Ltd
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Hitachi Ltd
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Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of GB8428394D0 publication Critical patent/GB8428394D0/en
Publication of GB2149574A publication Critical patent/GB2149574A/en
Withdrawn legal-status Critical Current

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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/10Containers or parts thereof
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/40Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44Conductive materials thereof
    • H10W20/4403Conductive materials thereof based on metals, e.g. alloys, metal silicides
    • H10W20/4405Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H10W20/4407Aluminium alloys
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/019Manufacture or treatment of bond pads
    • H10W72/01951Changing the shapes of bond pads
    • H10W72/01955Changing the shapes of bond pads by using masks
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/075Connecting or disconnecting of bond wires
    • H10W72/07551Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H10W72/07553Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting changes in shapes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • H10W72/536Shapes of wire connectors the connected ends being ball-shaped
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • H10W72/5363Shapes of wire connectors the connected ends being wedge-shaped
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/541Dispositions of bond wires
    • H10W72/5449Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/551Materials of bond wires
    • H10W72/552Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/59Bond pads specially adapted therefor
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/931Shapes of bond pads
    • H10W72/932Plan-view shape, i.e. in top view
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/931Shapes of bond pads
    • H10W72/934Cross-sectional shape, i.e. in side view
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/951Materials of bond pads
    • H10W72/952Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/981Auxiliary members, e.g. spacers
    • H10W72/983Reinforcing structures, e.g. collars
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

At least one of nickel, molybdenum, palladium and platinum is selectively introduced into wiring regions 6, excluding wire contact regions, of an electrically-conductive layer 3 composed chiefly of aluminum which is formed over a semiconductor substrate 1 of a semiconductor device. This ensures that the wiring exhibits an increased resistance against corrosion and electromigration, while preventing poor bonding of bonding wires, The wire contact regions may comprise layer portions formed separately from, and over, layer portions providing wiring regions. <IMAGE>

Description

SPECIFICATION Semiconductor device and process of manufacture thereof The present invention relates to a semiconductor device and a process of manufacturing such a device.
In recent years, integrated circuits have become smaller and more densely integrated, and stricter requirements have been imposed on them. However, the following problems have arisen with this trend.
(1)As integrated circuits have become smaller, the depth of their diffusion junctions decreases.Therefore junctions are often penetrated and breakdowns often develop because of alloy pits that stem from mutual diffusion between the wiring material and the silicon which forms the semiconductor substrates.
(2) As the wiring becomes finer, the current density therein increases, giving rise to the occurrence of electromigration.
(3) Reliability decreases because of corrosion of wiring due to the infiltration of water.
A variety of methods can be proposed to solve these problems. However, it is very difficult to solve these problems without increasing the chip area, making the manufacturing process more complex, and increasing the cost.
The applicants have conducted various studies into these problems, and has contrived the countermeasures described below.
(1) The diffusion of aluminum into the silicon substrate results in the formation of alloy pits in the junction portions. To solve this problem, use is made of an Al-Si alloy which is composed of aluminum with several percent silicon added.
(2) To solve the problem of electromigration and improve the resistance against humidity, use is made, as a wiring material, of an Al-Si-Cu alloy composed of aluminum, silicon and copper, or an Al-Ni alloy composed of aluminum and nickel. The copper and nickel contained as impurities in the aluminum wiring, help suppress the development of electromigration and intercrystalline corrosion that are caused by the infiltration of water.
To form an Al-Ni alloy, nickel ions are implanted into the surface of aluminum wiring, followed by a heat treatment. This Al-Ni alloy exhibits a resistance against corrosion which is several times that of aluminum. However, the inventors have found that if impurities such as nickel ions are introduced, the wiring exhibits an increased hardness and is liable to oxidize easily. This causes poor bondability in the wire bonding step.
An object of the present invention is to provide a semiconductor device in which these problems are absent or mitigated, which can have a high performance and which can be manufactured inexpensively.
Another object of the present invention is to provide a process of manufacturing such semiconductor devices, which process need not be very complicated.
The invention deals with a semiconductor device in which wiring chiefly composed of aluminum is formed on a silicon substrate, and portions of the wiring form wire-bonding pads. Nickel or other metal ions are implanted into the aluminum wiring, except for the areas of wire-bonding pads, to prevent electromigration and increase resistance against corrosion. Thereby a good bondability can be maintained for the wire-bonding pads, and resistance against corrosion and humidity is increased in other portions.
Embodiments of the invention will be described below by way of example with reference to the accompanying drawings, in which: Figure l is a section through a portion of a first semiconductor device embodying the invention having a one-layer wiring structure; Figures 2, 3(a) and 3(b) are sections illustrating steps in manufacture of the device of Fig. 1; Figure 4 is a section through a portion of a second semiconductor device embodying the invention, also having a one-layer wiring structure; Figure 5 is a section through a portion of a third semiconductor device embodying the invention having a two-layer wiring structure; Figure 6 is a section through a portion of a fourth semiconductor device embodying the present invention;; Figure 7 is a section through major portions of a semiconductor device, illustrating in detail the embodiment of Fig. 5; Figure 8 is a plan view of the semiconductor device of Fig. 5; and Figure 9 is a section through a portion of a fifth semiconductor device embodying the present invention.
Figure 1 shows a silicon crystal substrate 1 whose surface is provided with semiconductor element regions formed by selective diffusion of impurities (not shown). On the substrate 1 are a surface oxide film 2 (SiO2), aluminum wiring 3 ends of which are connected to the semiconductor elements (not shown), and an insulating film 4 providing passivation, which is composed, for example, of a polyimide-type resin. Portions of the insulating film 4 are removed, and the exposed aluminum surfaces act as wire-bonding pads to which gold wires 5 are bonded.
To prevent the diffusion junction being penetrated as described earlier, the wiring 3 is composed of an Al-Si alloy containing 2 to 5% by weight silicon, rather than pure aluminum. An Al Si-Ni layer 6 is formed at the surface of the wiring 3, excluding the location of each wire-bonding pad positioned just beneath the gold ball formed from the gold wire 5.
Figures 2 and 3 show the process of introducing nickel into the surface of the aluminum wiring.
Figure 2 shows aluminum wiring (here aluminum-silicon wiring) formed by vaporizing aluminum and then pattern-etching using a photoresist.
A photoresist mask 7 is formed over the regions which will act as the bonding pads, and then nickel ions are implanted to selectively introduce nickel into the surface of the aluminum wiring.
The next step is the bondinq of the qold wire. In this bonding step, a temperature of between 350 to 400 C is applied for about 10 seconds. By utiliz ing a heat treatment (or by providing a simple heat treatment later), the nickel selectively introduced into the aluminum wiring (or in this case alumi num-silicon wiring) is made to diffuse through the aluminum, so that an Al-Ni alloy (or Al-Ni-Si alloy) is formed (Fig. 3(a)). With this method, in which nickel is diffused by utilizing the heat applied in the bonding step, there is no need to provide a heat treatment step. Therefore the Al-Ni wiring (containing 2 to 3% by weight nickel) (or Al-Ni-Si wiring) can be formed by conventional process steps, without any need to change the process.
It is also possible to locally form the Al-Ni alloy layer (or Al-Si-Ni alloy layer) 6 by annealing, to diffuse the nickel into the aluminum wiring (see Fig.
3(b)), instead of by the above method. The wires are then bonded.
Thus in this first embodiment of the present invention, the aluminum wiring (or aluminum wiring containing silicon) is composed of an Al-Ni alloy, except for the areas of the wire-bonding pads.
Therefore, even if water does infiltrate, the wiring does not corrode much, and exhibits an increased resistance against humidity. On the other hand, nickel has not been introduced into the portions of the bonding pads beneath the gold balls. Therefore the strength of the wiring is increased, and no thick oxide film is formed on the surface of the wiring, so that bondability is not reduced, and the formation of defective bonding is prevented.
The inventors have conducted PCTs (high temperature high-humidity tests) to determine the period before an IC fails to operate properly under conditions of a temperature of 121 C and a relative humidity of 100%. These periods were 60 hours for an IC using pure aluminum, 200 hours for an IC using aluminum containing silicon, and 1000 hours for an IC using aluminum containing nickel (or aluminum-silicon containing nickel).
Thus, the effect of increasing resistance against the humidity was confirmed.
The development of defective bonding in the wire-bonding step could also be prevented almost completely.
It has also been clarified through experiments performed by the inventors that similar effects can be obtained when palladium (Pd), platinum (Pt), or molybdenum (Mo) is used as the impurity, instead of or in addition to the nickel (Ni) used in this embodiment.
Referring now to Fig. 4, here is shown wiring 8 composed of an Al-Ni alloy or composed of an Al Pd, Al-Pt, or Al-Mo alloy (or wiring composed of an Al-Ni-Si alloy, Al-Pd-Si alloy or Al-Mo-Si alloy). On the wiring 8 is a pure aluminum film 9 (or an Al-Si film) which acts as a bonding pad and which is locally vaporized onto the wiring 8.
The bonding pad 9 can thus be formed by a liftoff technique, according to which, for example, a passivation film 4 is formed, an opening therein corresponding to the bonding pad region is formed by etching, portions other than the bonding pad region are covered with a photoresist mask, alumi num or the like is vaporized thereonto, and then the photoresist mask and unwanted aluminum thereon are removed.
In this embodiment all the wiring 8 is composed of, for example, an Al-Ni (or Al-Ni-Si) alloy which exhibits an increased resistance against humidity.
The gold wire is bonded to the bonding pad con sisting of the pure aluminum film (or Al-Si film) 9, and defective bonding of gold wire is prevented.
Figure 5 shows a third embodiment in which a first wiring layer 10 is composed of, for example, an Al-Ni alloy (or Al-Ni-Si alloy), and on it there is an intermediate insulating film 11 which is com posed of, for example, a polyimide resin and of which a portion is removed by etching. A second layer of wiring 12 composed of pure aluminum (or aluminum containing silicon) is formed over the insulating film 11 An Al-Ni alloy layer 13 is formed in the second-layer wiring 12 by selectively im planting nickel ions thereinto, except for a portion which is to form a bonding pad to which a gold ball is to be brought into contact. A passivation film is formed over second-layer wiring 12, which is composed of, for example, a polyimide resin.A through hole is formed in the passivation film by etching so that the bonding pad is exposed, and the gold wire 5 is bonded to the bonding pad.
Figure 7 shows this structure in more detail. A semiconductor substrate 1 in which npn-type transistors are formed is secure by soldering (not shown) to a tab lead 23, and the bonding pad 12 and a lead 25 are connected together by a gold wire 5. The whole assembly is sealed within resin 24.
Figure 8 is a plan view of Fig. 5. As can be seen in Fig. 8, no impurities have been introduced into the region (or the vicinity thereof) of the bonding pad to which the gold ball 26 is to be connected.
With this structure, the region without impurities does not corrode much since it is covered by the gold ball 26, and its reliability does not decrease.
Figure 6 shows an embodiment in which nickel, palladium, molybdenum or the like are introduced into the region 13, except for the bonding pad area of the first-layer wiring 10 and the second-layer wiring 12.
Figure 9 shows an embodiment in which the present invention is adapted. In this embodiment, use is made of an inexpensive Al-Ni alloy (or Al Mo, Al-Pd, etc.), instead of expensive gold, as wires 5 connecting the bonding pads 12 to the leads. Impurities are introduced into the wire, except for the portion which comes into contact with the wiring 12 composed of an Al-Si alloy. With this embodiment, the manufacturing cost can be reduced, while maintaining reliability.
From the description of the above five embodiments, various advantages obtainable with the present invention are apparent, viz: (1) The wiring is resistant against electromigration and corrosion, and hence the semiconductor device exhibits good reliability.
(2) No impurity is introduced into at least the region to which a gold ball will be connected, i.e. the bonding pads. Therefore, bondability is not reduced, and poor bonding of the bonding wires is prevented.
(3) As a result of (1) above, an inexpensive, readily-available polyimide resin, or the like, which has a good flatness can be employed as a passivation film or an intermediate insulating film, without reducing reliability.
(4) Impurities such as nickel ions can be selectively introduced relatively easily into the wiring layer composed of aluminum. Therefore, the manufacturing process does not become too complex.
(5) Because of (1) to (4) above, semiconductor devices can be manufactured while maintaining a high yield and a high reliability.
The present invention can be applied to any semiconductor devices provided with aluminum wiring. In particular, the invention can be effectively adapted to semiconductor devices which have a multi-layer aluminum wiring structure, and which employ a polyimide type of organic resin as a passivation film or as an intermediate insulating film.
The above description has mainly dealt with cases in which the invention accomplished by the inventors is adapted to techniques for forming electrodes of semiconductor devices, which served as a background to the present invention. The invention, however, should not be limited thereto, but can also be adapted to, for example, a technique of forming electrodes on a wiring substrate.

Claims (10)

1. A semiconductor device comprising: (1) a semiconductor substrate; (2) an insulating film formed over said semi-conductor substrate; (3) an electrically-conductive layer composed chiefly of aluminum, which is formed on said insulating film and which consists of wiring regions and wire contact regions, there being at least one of nickel, molybdenum, palladium, and platinum present in said wiring regions of said electricallyconductive layer, excluding said wire contact regions; and (4) metal wires electrically connected to said wire contact regions of said electrically-conductive layer.
2. A semiconductor device according to claim 1 wherein said wire contact regions are layer portions formed separately from and over layer portions providing said wiring regions.
3. A semiconductor device according to claim 1 or claim 2, wherein said wiring regions of said electrically-conductive layer are composed of an alloy that consists of aluminum containing a small quantity of silicon (Si).
4. A semiconductor device according to any one of claims 1 to 3, wherein said electrically-conductive layer is covered with a resin film and is sealed within resin.
5. A semiconductor device comprising: (1) a semiconductor substrate; (2) an insulating film formed over said semiconductor substrate; (3) a first electrically-conductive layer formed on said insulating film and which is chiefly composed of aluminum that contains at least one of nickel, molybdenum, palladium and platinum; (4) a second electrically-conductive layer composed chiefly of aluminum which is electrically connected to said first electrically-conductive layer, and which consists of wiring regions and wire contact regions, there being at least one of nickel, molybdenum, palladium, and platinum present in said wiring regions of said second electrically-conductive layer, excluding said wire contact regions; and (5) metal wires electrically connected to said wire contact regions of said second electrically-conductive layer.
6. A semiconductor device according to claim 5, wherein said wiring regions of said first and second electrically-conductive layers are composed of an alloy which consists of aluminum containing a small quantity of silicon.
7. A semiconductor device according to claim 5 or claim 6, wherein said electrically-conductive layers are covered with a resin film and are also sealed within resin.
8. A process of manufacturing a semiconductor device comprising: (1) forming an electrically-conductive layer composed chiefly of aluminum over a semiconductor substrate; (2) introducing at least one of nickel, molybdenum, palladium, and platinum into wiring regions of said electrically-conductive layer, excluding wire contact regions thereof; and (3) connecting metal wires to said wire contact regions of said electrically-conductive layer.
8. A process according to claim 7 wherein the wire-contact regions of said electrically conductive layer are conductive portions formed in a second wiring step, subsequent to a first wiring step which forms said wiring regions.
9. A semiconductor device substantially as herein described with reference to and as shown in Fig. 1, Fig. 4, Figs. 5,7 and 8, Fig. 6 or Fig. 9 of the accompanying drawings.
10. A process according to claim 7 substantially as any herein described with reference to the accompanying drawings.
GB08428394A 1983-11-11 1984-11-09 Semiconductor device and process of manufacture thereof Withdrawn GB2149574A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58210811A JPS60103655A (en) 1983-11-11 1983-11-11 Semiconductor device and manufacture thereof

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Publication Number Publication Date
GB8428394D0 GB8428394D0 (en) 1984-12-19
GB2149574A true GB2149574A (en) 1985-06-12

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GB08428394A Withdrawn GB2149574A (en) 1983-11-11 1984-11-09 Semiconductor device and process of manufacture thereof

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KR (1) KR850004175A (en)
GB (1) GB2149574A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2262347A (en) * 1991-12-09 1993-06-16 Polar Electro Oy Measuring heartbeat rate
EP3882965A1 (en) * 2020-03-17 2021-09-22 Kabushiki Kaisha Toshiba Semiconductor device with an electromigration reducing area

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02105418A (en) * 1988-10-14 1990-04-18 Mitsubishi Electric Corp Resin-sealed type semiconductor device
JP2806538B2 (en) * 1988-12-09 1998-09-30 日本電気アイシーマイコンシステム株式会社 Integrated circuit device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2262347A (en) * 1991-12-09 1993-06-16 Polar Electro Oy Measuring heartbeat rate
GB2262347B (en) * 1991-12-09 1995-11-15 Polar Electro Oy A device for measuring heartbeat rate
EP3882965A1 (en) * 2020-03-17 2021-09-22 Kabushiki Kaisha Toshiba Semiconductor device with an electromigration reducing area
US12040303B2 (en) 2020-03-17 2024-07-16 Kabushiki Kaisha Toshiba Semiconductor device and inspection device

Also Published As

Publication number Publication date
GB8428394D0 (en) 1984-12-19
JPS60103655A (en) 1985-06-07
KR850004175A (en) 1985-07-01

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