GB2152249A - Video signal processor - Google Patents

Abstract

In a signal processor wherein data of a video signal (VI) is processed by a computer (CPU) in a real-time mode according to programs, an exclusive bus (11 or 12) is provided between the computer and a peripheral equipment such as a main memory (7) or the like, thereby transmitting the video signal data direct between peripheral equipments. With this equipment, real-time processing of the video signal can be realized in parallel with an input processing of a picture signal to the computer. <IMAGE>

Description

SPECIFICATION Signal processor This invention relates to a signal processor for processing video signals data.

For indicating moving pictures on a picture display, it is required that a predetermined picture processing can be executed within each field (60 fields/sec. normally) at least. A system shown in Fig. 1 is known to work as a processor of this kind. In the drawing, 1 denotes an input line for a video signal V1 including horizontal and vertical synchronizing signals and an encoded colour signal: 2 denotes a decoder to separate the video signal V1 into colour signals R,G,B; 3 denotes an analog-to-digital (A/D) converter to convert the colour signals R,G, B into a digital signal format: 4 denotes a frame memory to store digitized colour signals R, B, G for each frame: 5 denotes an interface for transmitting data D in the frame memory 4 on DMA (direct memory access): 6 denotes a computer (CPU): 7 denotes a (main) memory to store programs and data of the computer 6: 8 denotes a disk controller to store the data of the computer 6: 9 denotes a disk to store the data of the computer 6: 10 denotes an input/output unit for the data of the computer 6: 11 denotes a bus to connect the interface 5 through the disk 9: 12 denotes a program control channel (PCCH) to connect the interface 5 through the disk 9: 13 denotes a digital-to-analog (D/A) converter of the data D of the frame memory 4, and 14 denotes an encoder of outputs from the D/A converter 13.

The video signal VI is decoded first on the decoder 2 and separated into red, blue and green colour signals R, B, G. Next, the colour signals R, G, B are converted into digital colour signals F, B, G on the A/D converter 3, inputted to the frame memory 4 and then stored for one picture (1 field or 1 frame). The data D of the frame memory 4 is transmitted to the memory on DMA by way of the interface 5 under control of the computer 6. The data transmitted to the memory 7 is subjected to a picture processing thereafter on the computer 6. The result of the processing is sent to the disk 9 by way of the disk controller 8 and stored therein.The data stored in the disk 9 is transmitted to the frame memory 4 by way of the bus 11 and the interface, converted then into an analog level colour signal on the D/A converter 13, encoded further to a video signal VO on the encoder 14 and then outputted therefrom. The input/output unit 10 outputs a transmission request (command) to the A/D converter 3, the frame memory 4 and the D/A converter 13 at the time of read and output of data, and also has a function to grasp these statuses.

The conventional system is constituted as above, therefore in the case of NTSC signal, for example, if a resolution of displayed picture comes in 480 pieces vertically and 512 pieces horizontally, a bit number of the A/D converter is 8 bits, and a transmission speed of DMA bus interface is 64 K bytes/sec., a time T required for inputting one picture to the computer will be:

Further, a reverse operation to the input takes place at the time of display, therefore a similar period of time will be required. Accordingly, such input/output processing carried out simultaneously requires a time of 20 sec. or over. On the other hand, since the computer outputs a picture data direct to the D/A converter from the frame memory by way of a common bus while the picture is subjected to an on-line processing, other processings cannot be executed while this is happening.An object of the invention is to provide an improved signal processor.

Accordingly this invention provides a signal processor which is functional to execute a real-time processing of a video signal and an input processing of a picture to a computer in parallel by removing the above-mentioned defects prevailing hitherto and also by providing an exclusive bus for transmitting a video signal data direct between peripheral equipments.

In one embodiment of this invention, a novel signal processor is provided with a second bus for real-time processing of a video signal between peripheral equipments in addition to a first bus for input processing to a computer, a controller for accessing data between peripheral equipments by way of the second bus, and an interface for the second bus and the controller with a picture memory.

In another embodiment, the signal processor of this invention is provided with a second bus for real-time processing between peripheral equipments including a picture memory, and a controller for accessing data between peripheral equipments synchronously with a video signal.

Embodiments of the invention will now be described by way of example only, with reference to the accompanying drawings in which: Figure 1 is a block diagram of a conventional signal processor; Figure 2 is a block diagram of a signal processor in accordance with one embodiment of this invention; Figure 3 is a block diagram of a signal processor in accordance with another embodiment of this invention.

In Fig. 2 like reference characters denote like parts to these in Fig. 1 and 15 represents a bus controller, which inputs a data of the video signal VI converted on the A/D converter 3 and sends it onto a bus B. 16 denotes a bus controller for controlling a transmission of the data on the bus B synchronously with the video signal through the line 1, 17 denotes a bus controller for controlling a cyclic transmission of the data on the bus B to the D/A converter 13, and 18 denotes a bus interface for transmitting the data of the bus B on to the bus 11 or the data on the bus 11 to the bus B.The bus B is connected in common with the bus controllers 1 5. 16, 17 and the interface 18, and includes a line for transmitting data signals to send and receive mutually, a line for transmitting horizontal and vertical synchronizing signals detected from the video signal VI, and a line for transmitting a timing signal for strobing a data signal synchronously with the synchronizing signals. The horizontal and vertical synchronizing signals and the timing signal are sent onto the bus B from the bus controller 16.

In the operation, the video signal VI is controlled by the bus controller and thus transmitted to a picture display (not illustrated) by way of the decoder 2, the A/D converter 3, the bus controller 15. the bus B.

the bus controller 17, the D/A converter 13 and the encoder 14 to a display means.

Similarly, the data registered in the memory 7 and the disk 9 is transmitted to the bus controller 17 by way of the bus 11 or 12 which is not used by the computer 6, the bus interface 18 and the bus B, and also the data of the bus controller 15 is transmitted to the memory 7 and the disk controller 8 by way of the bus B, the bus interface 18 and the bus 11 or 12 which is not used by the computer 6. While such data transmission is carried out, the computer 6 is capable of simultaneously executing a data processing wherein data is sent and received between the memory 7 and the disk controller 8 by way of the bus 11 or 12 in use by the computer. A background processing for animation display which requires much time therefor may thus also be included in the data processing.

Fig. 3 is a block diagram representing another embodiment of this invention, which indicates a signal processor provided with a controller for accessing data direct between peripheral equipments synchronously with a video signal through a bus provided for connecting peripheral equipments. In Fig. 3, like reference characters represent like parts in Fig. 1 and Fig. 2 and 19 denotes a bus for transmitting a data for display cyclically synchronously with the video signal VI. The bus 19 is connected with the computer 6, the memory 7, the disk controller 8, the bus controllers 15 and 17, and includes a line for transmitting data signals sent and received mutually among them, and a line for transmitting a timing signal for strobing data signals synchronously with the horizontal and vertical synchronizing signals detected from the video signal VI.The horizontal and vertica! synchronizing signals and the timing signal are sent onto the bus B from the bus controller 16.

In the operation. the video signal Vi is controlled by the bus controller 16 and thus transmitted to a picture display (not illustrated) by way of the decoder 2. the A/D converter 3. the bus controller 1 5. the bus 9, the bus controller 17, the D/A converter 13 and the encoder 14 to a display means.

Similarly. the data registered in the memory and the disk 9 is transmitted to the bus controller 17 by way of the bus 1 9. and also the data of the bus controller 15 is transmitted to the memory 7 and the disk controller 8 by way of the bus 19. Since the above transmissions are carried out through the bus 19 which is independent from the buses 11 and 1 2. the computer 6 is also capable of executing a data processing wherein data is sent and received between the memory 7 and the disk controller 8 by way of the buses 11 and 12. A background processing for animation display which requires much time therefor is also included in the data processing.

Although. in the above embodiments. the video signal is represented by a colour video signal the invention is equally applicable to a signal for displaying a cyclic picture such as black-and-white video or the like. Further in Fig. 2 or Fig. 3, an apparatus other then the bus controller 16 and the computer 6 can be connected plurally and so utilized.

As described above, according to this invention, a bus and a controller for a video signal synchronized with the video signal are provided within the signal processor, therefore video signal data can be processed for registration, retrieval and the like on real-time mode without suspending a processing on the computer.

Claims (5)

1. A signal processor provided with a computer arranged for reading data of a consecutive video signal from a picture memory storing said data, by way of a first bus and executing a predetermined picture processing on real-time mode according to programs stored in a main memory, including a realtime processing means for video signals which operates for another processing simuitaneously and in parallel with an input processing of the computer.

2. The signal processor as defined in Claim 1, said real-time processing means comprising a second bus for connecting said computer and a peripheral equipment including said main memory, an interface tor connecting said first and second buses with said picture memory, a controller for accessing data direct with another peripheral equipment by way of either the first or second bus while said computer transmits data to one of said peripheral equipment by way of the other of said first or second bus.

3. The signal processor as defined in Claim 1, said real-time processing means comprising a second bus for connecting said picture memory and the peripheral equipment including the main memory and a controller for accessing data direct with said peripheral equipment synchronously with said video signal by way of the second bus.

4. A signal processor substantially as described herein with reference to or as illustrated in Fig. 2 or Fig. 3 of the accompanying drawings.

5. A method of processing signals substantially as described herein with reference to Fig. 2 or Fig. 3 of the accompanying drawings.