GB2158997A - Phased array antenna - Google Patents

Description

1 GB 2 158 997 A 1

SPECIFICATION

Phased array antenna This invention relates to antenna systems and more 70 particularlyto phased array antenna systems.

As is known in the art, an array antenna includes a plurality of individually radiating elements. In some systems the individual radiating elements are coupled to a transmitter through a transmitter elementfor controlling the phase and amplitude of the transmit ted signal. Similarly, the individual radiating elements are coupled to a receiverthrough a receiver element, for controlling the phase and amplitude of the received signal. In other systems the individual 80 radiating elements are coupled to both thetransmitter and receiverthrough a single element here referred to as a transceiverfor controlling the phase and ampli tude of both transmitted and received signals. The relative phase and amplitude of the microwave 85 frequency signal passing between the plurality of radiating elements and a corresponding plurality of individual transceiver elements are controlled to obtain a desired radiation pattern. The pattern obtained is a result of the combined action of all the 90 individual transceiver and radiating elements. Many devices such as ferrite phase shifters are used to control the phase of the microwave frequency signal.

Many of such phase shifters are reciprocal, that is, the phase shift of a signal passing through one of such 95 devices is independent of the direction which the signal passes through. In some applications it is desirable to provide an active phase shifterto provide gain to a signal passing there through. Such a phase shifter is generally inherently nonreciprocal. Thus, the 100 use of an non reciprocal phase shifter in a transceiver would require the use of two of such phase shifters. A developing trend in phased array antenna systems is toward production of the transceiver elements in monolithic integrated circuitform. This is desired in orderto reduce cost and size factors generally associated with phased array antenna systems and to provide phased array antennas adapted forcertain applications where size and cost are critical such as airborne or space based radar systems.

In accordance with the present invention, a transceiverforcoupling a microwave signal between an antenna elementand a radar system, is provided. Such a transceiver includes a plurality of switching means arranged to steer a microwave frequency signal provided bythe radar system through an nonreciprocal phase shifterto the phased array antenna during a transmit mode, and to steer a microwave frequency signal provided from the phased array antenna through the nonreciprocal phase shifterto the radarsystem during a receive mode. The microwave frequency signal passes through the phase shifter in the same direction during both the transmit and receive mode. A set of control signals is fed to such switching means to control the steering of the microwave frequency signal between the radarsystem and the phased array antenna. With such an arrangement, two signal paths through an active nonreciprocal phase shifter are provided. This arrangement reduces the cost and size of the trans- ceiver element by permitting the use of a sing le active nonreciprocal phase shifter. Further, since each of the elements of the transceiver element may be realized as monolithic microwave integrated circuits this structure results in a co m pact transceiver element, modular in form and less expensive to produce.

The invention will now be described by way of example with reference to the accompanying drawings,inwhich:

FIG. 1 is an overall block diagram of a radar system coupled to a phased array antenna system through a plurality of transceiver elements; FIG. 2 is a block diagram of one of the plurality of transceiver elements shown in Fig. 1; FIG. 3 is a block diagram of the transceiver element, utilizing a five port switch; FIG. 4 is a block diagram of a transceiver using a dual channel phase shifter; FIG. 5 is a block diagram of a 4-bit nonreciprocal phase shifter; FIG. 6 is a diag rammatical view of a 180'phase shift increment stage of a 4-bit nonreciprocal phase shifter used in the one of the transceiver elements; FIG. 6A is an isometric view of a bias line and output line insulated from each other with an air gap plated overlay; FIG. 613 is a cross sectional view of a parallel plate capacitor formed on the substrate; FIG. 7 is a block diag ram of the phase shifter stage depicted in Fig. 5; FIG. 8 is a detailed schematic digram of the phase shifter stage depicted in Fig. 5; FIGS. 9A-91) are plan views of pairs of transmission lines providing electrical pathlength differences used to realize a 4-bit phase shifter.

FIG. 10 is a blockdiagram of a 4-bit dual channel phase shifter; FIG. 11 is a detailed schematic of one stage of a reciprocal phase shifter; FIG. 12 is a diagrammatical view of the stage of a dual channel phase shifter depicted in Fig. 11; FIG. 13 is a detailed schematic of an alternate embodiment of a four bit nonreciprocal phase shifter; FIG. 14 is a block diagram of the nonreciprocal phase shifterof Fig. 13, including reciprocating switches; FIG. 15 is a detailed schematic diagram of a variable phase shifter utilizing a quadrature coupler.

FIG. 16 is a plan view of the variable phase shifter showninFig.15; FIG. 17 isa blockcliagram of one stage of the n-bit variable phase shifter shown in Fig. 16; FIG. 18 is a diagrammatical view of a bidirectional three port switch; FIG. 19 is a schematic diagram of the bidirectional switch shown in Fig. 18; FIG. 20 is a schematic diagram of a preferred field effect transistor FET used in the bidirectional switch of Fig. 18.

Referring nowto FIG. 1, a phased array antenna 10 is coupled to a radar system 11 by a feed network 14, as snown. The phased array antenna 10 includes a plurality of, here n, identical transmitter-receiver (transceiver) elements 12a-1 2n, coupled to a like plurality of corresponding antenna elements 26a-26n, 2 as shown. The feed network 14, here a parallel feed network, provides a signal path for a microwave signal passing from the radar system 11 to the phased array antenna 10 for transmission to a target (not shown), and a signal path for reception of echo signals from the target (not shown) to the radarsystem 11. A plurality of control buses 29a-29n, f5amOn are provided from the radar system 11. Signals on such buses 29a- 29n, T9_a-T9_n are used to control the transceiver elements 12a-1 2n of the phase array antenna 10. The microwave signal from the feed network 14 is coupled to each of the transceiver elements 12a-1 2n, as indicated bythe open arrows 13. The portion of microwave signal coupled to each one of the transceiverelements 12a-1 2n is then coupled to the corresponding one of the antenna elements 26a-26n. Similarly, a portion of the microwave echo signal from the target is coupled to each of the antenna elements 26a-26n, the corresponding transceiver elements 12a-1 2n, and the feed network 14 as indicated by solid arrows 15, for processing by the radar system 11. The control signals on buses 29a-29n, 19-a-19-n during the transmit mode allow the transceiver elements 26a-26n to produce collimated and directed beams of transmit- ted microwave energy and control signals on such buses during the receive mode allow such transceiver elements 26a-26n to produce collimated and directed beams of received microwave energy.

Referring nowto FIG. 2, a representative one of the transceiver elements 12a-1 2n, here transceiver element 12i is shown coupled, via a transmission line 33i, to a portion of the feed network 14 and to an antenna element 26i, via a transmission line 35i, as shown. Transceiver element 12i here includes 50 ohm trans- mission lines 32a to 32h, fou rtransmitter/receiver (T/R) switches 18a- 18d, each having a common port 20a-20d, a pairof branch ports 19a-19d and 2la-21d, and a control input22a-22d. Each one of the control inputs 22a- 22d isfed bya pairof control lines 29il, 29i, of buses 29i,19-i. TheT/R switches 18a-18d are here of a typeto be further explained in conjunction with Figs. 18-19. Suffice itto say here, however, thatcomplementary, binary or logical signals arefedto the control lines 29il, Y9-il, respectively, and such logical signals are used to control the electrical coupling 110 between the common port and the branch ports. Thus, for example, using an exemplary one of the T/R switches 18a-18d, hereTIR switch 18a, such switch 18a has common port 20a coupled to branch port 19a in response to a first pair of logical states of control 115 signals fed to lines 29il, 279i, i.e. a logigal 1 on line 29i, and a logical 0 on line!9-il and such common port 20a is coupled to branch port 21 a in response to the complementary pair of logical states of the control '2- signals fed to line 29il, 9il, i.e. a logical 0 on line29i, 120 and a logical 1 on line 9_il. The common port 20a of T/R switch 18a is coupled to the feed network 14, via the transmission line 33i, as shown. Branch ports 19a and 21 a of T/R switch 18a are coupled to branch ports 19d and 21 b, via transmission lines 32a and 32h, respectively. Branch port 19b of T/R switch 18b is coupled to an input of a transmitter amplifier 24, via the transmission line 32d. The transmitter amplifier24 is hereformed on a semi-insulating substrate, here a gallium arsenside (GaAs) substrate. The output of GB 2 158 997 A 2 transmitter amplifier 24 is coupled tothe branch port 19c of T/R switch 18c,via transmission line 32e.The common port20cof T/R switch 18c is coupledto the antenna element 26i, via transmission line 35i. The branch port 21 c of T/R switch 18c is coupled to an input of the receiver amplifier 28, via transmission line 32f. The receiver amplifier 28, here a low noise amplifier, is hereformed on a semi-insulating substrate (here GaAs).The outputof the receiver amplifier 28 is coupledtothe branch port2ld ofT1R switch 18d, via transmission line32g. The common port20d of T/R switch 18d is coupled to the input of an active phase shifter40, here a nonreciprocal active phase shifter having a plurality of stages (not shown, to be described in detail in connection with Figs. 5,6 and 7), via transmission line 32b. Suffice itto say here, however, that each stage of the active phase shifter includes afield effect transistor suitably biased to provide gain to the radio frequency signal passing through it. Control signals forthe a ctive phase shifter 40 are fed thereto, via buses 29i2, 9i2 of bus 29i. The output of the active phase shifter 40 is cou pled to the common port 23b of T/R switch 18b, via transmission line 32c.

During a transmit mode, the transceiver element 12i couples a microwave frequency signal from the radar system 11 to the antenna element 26i. A transmit signal path for coupling a signal from the radar system 11, via feed network 14, to the antenna element 26i is depicted in FIG. 2 by an open arrow 13, as shown. In the transmit mode, the control signals on lines 29il, T9-il are used to couple each one of the common ports 20a-20d to the corresponding branch ports 19a-19d of the respective T/R switches 18a-1 8d. Thus a portion of the microwave signal is coupled from the radar - system 11 to the input of the active phase shifter40.

The active phase shifter40 is here used to vary the phase shift of the applied microwave frequency signal by a predetermined amount in accordance with control signals on buses 29i2-29i2 which are fed to a control input 42, of the active phase shifter40. The microwave frequency phase shifted signal isthen coupled to the input of the transmitter amplifier 24. The signal atthe output of the transmitter amplifier 24 is coupled to the antenna element 26i.

During a receive mode, a portion of a received echo signal is coupledfrom the antenna element26i to the radarsystem 11. A receive signal path forcoupling the received echo signal from the antenna element26i to the radarsystem 11 is depicted in FIG. 2 by solid arrows 15, as shown. During the receive mode the complementary logical states of the control signals previously on lines 29i,49-il are nowfed to lines 29il, 29il, and such signals are used to couple each one of the common ports 20a-20d to the branch ports 21 a-21 d of the respective T/R switches 18a-1 8d. Thus the echo signal is cou pled from the antenna element 26i to the receiver amplifier 28. The signal at the output of the receiver amplifier 28 is coupled to the input of the active phase shifter element 40. The signal passing through the phase shifter is again phase shifted in accordance with the control signals fed on buses 29i2-29i2. The phase shifted signal produced at the output of the active phase shifter element 40 is then coupled to the radar system 11, via the feed 3 GB 2 158 997 A 3 network 14.Thus itis notedthatthe microwave frequencysignal is coupledthrough the active phase shifter40 in thesame direction forboth thetransmit modeandthe received mode.Thus, referring again to FIG. 1 in a similar manner, each of the plurality of transceiver elements 12a-1 2n are used to couple a portion of a microwave signal between the radar system 11, via the feed network 14 and the plurality of antenna elements 26a-26n, to produce in combination a collimated and directed beam (not shown) during the transmit mode and the receive mode.

Referring nowto FIG. 3 an alternative the embodi ment of a transceiver element 12i'suitable for use in the phased array antenna 10 of FIG. 1 is shown coupled to a portion of the feed network 14 and the antenna element 26i. Transceiver element 12i'here includes a five port switch 310, the active phase shifter 40, the transmitter amplifier 24, the receiver amplifier 28, and the three portT/R switch 18c, as shown. The five port switch 310 is formed on a substrate, (not shown) here semi-insulating gallium arsenide (GaAs) having a ground plane (not shown) here plated gold formed on the bottom surface of the substrate.

Formed in active regions on portions of the top surface of the semi-insulating substrate are FET's 50a-50d here GaAs FETs, each having gate electrodes 52a-52d (Fig. 3), a drain electrode 54a-54d and a source electrode 56a-56d. The gate electrodes 52a, 52d of FET's 50a, 50d, are connected to control line 29il, and the gate electrodes 52b, 52c of FET's 50b, 50c, are connected to control line 19-il, as shown. The FET's are here connected in a common (grounded) source configuration. TheT1R switch 310 further includes transmission lines 60a-60f. Each transmission line 60a-60f has an electrical length, corresponding to one 100 quarter wavelength (A d4), where Ac is the wavelength of the corresponding nominal or operating center band frequency (f.) of the circuit. The feed network 14 is electrically connected to a first end 60a, of hd4 transmission line 60a and a first end 60f, of A d4 105 transmission line 60f, via transmission line 33i. The drain electrode 54c of FET 50c is electrically connected to a second end 60a2 of A j4transmission line 60a. A first end 60b, of h r/4transmission line 60b is electrically connected to the second end 60a2 Of transmission line 60a and drain electrode 54c. A second end 60b2 of,\,/4 transmission line 60b is electrically connected to the input port of the active phase shifter40, via transmission line 32b and to a first end 60d, of A c/4transmission line 60d. The second end 60d2 of transmission line 60d is electrically connected to the output of the receiver amplifier 28 and to the drain electrode 54d of FET 50d. Asecond end 60f2 ofX d4transmission line 60f is electrically connected to a first end 60e, of A /4transmission line 60e, and drain electrode 54a of FET 50a. Asecond end 60e2 of,\,/4 transmission line 60e is coupled to the output of the active phase shifter40, via transmission line 32c and to a first end 60c, ofX d4transmission line 60c. A second end 60c2 of A,/4 transmission line 60c is coupled to the input of the transmitter amplifier 24 and to the drain electrtde 54b of FET 50b. The connections of transmitter amplifier 24 and receiver amplifier 28 to T/R switch 18d are the same, as explained above in conjunction with FIG. 2.

During the transmit mode, as shown by the open arrows 13 a logical control signal on line 29i, of bus 29i is fed to the gate electrodes 52a, 52d of FETs 50a, 50d and the complement of such logical control signal is fed (via line Nil of bus!9-i) to gates 52b, 52c of FETs 50b, 50c. In response to such signals FET's 50a, 50d are placed in a conducting state and FET's 50b, 50c are placed in a nonconducting state. TheX d4 transmission lines 60d, 60e and 60f have ends 60d2,60e, and 60f2 electrically connected to FET's 50a and 50b, as previously described. When FET's 50a, 50d are placed in a conducting state, a short circuit (low impedance path to ground designated by (D) is produced atthe ends 60d2,60e, and 60f2 of transmission lines 60d-60f coupled to the FET's 50a, 50d. One quarter wavelength therefrom (at the second end 60dl, 60e2, and 60f, of each transmission line 60d-60f) the short circuits at ends 60d2,60el, 60f2 appear as open circuits (high impedance paths to ground designated by (D) at ends 60dl, 60e2,60fi, to a microwave frequency signal having a wavelength substantially equal to the wavelength of the corresponding nominal or centerband frequency of operation, forthe transceiver. Thus, no signal path is provided during the transmit mode through line 60f and the transmitted energy passes through lines 60a and 60b. Further because end 60d, appears as an open circuit(D, the transmitted energy passesfrom line 60b through line 32b, through the phase shifter40 and through line 32c. Since end 60e2 appears as an open circuit0the transmitted, and now phase shifted energy passes through line 60c, transmitter amplifier 24, T/R switch 18c and to the antenna 26i, as previously described in conjunction with FIG. 2.

During the receive mode as shown bythe closed arrows 15, the control signals on lines 29i,,19-il are switched (or complemented) in logic state placing FET's 50a and 50d in a nonconducting state, and placing FET's 50b and 50c in a conducting state. The ends 60a2,60bl, and 60c2 of the A d4transmission lines 60a, 60b and 60c which are coupled to the drain electrodes 54b and 54c of FET's 50b and 50d are thus coupled to ground and the other ends 60al, 60IJ2 and 60c, of the transmission lines 60a, 60b, and 60c present impedances corresponding to open circuits.

Thus, a received microwave signal from antenna element26i is coupled to the outputof the receiver amplifier28 as explained in conjunction with FIG. 2. The received signal is then coupled through transmission line 60d to the active phase shifter element 40.

The signal on the output of the active phase shifter 40 is thus coupled to the radar system 10 through transmission lines 60e and 60f.

Referring nowto Fig. 4, an alternative embodiment of a transceiver, heretransceiver 12i" suitablefor use in the phased array antenna 10 of FIG. 1 is shown coupled to a portion of the feed network 14,via transmission line 33i and tothe antenna element 26i, viatransmission line 35i, as shown. Transceiver element 12i" includesT/R switches 18a and 18c, transmitter amplifier24, receiver amplifier28. Here, however, a dual channel active phase shifter44 is provided. Dual channel active phase shifter44 has a plurality of cascade interconnected phase shift stages here 44a-44d of a type to be further described in detail in conjunction with Figs. 10-12. The T/R switch 18a has 4 GB 2 158 997 A 4 common port 20a coupled to the feed network 14 via transmission line 33i. Branch ports 19a and 21 a of T/R switch 18a are coupled to the input 47a of a first channel 47 and the output 49b of a second channel 49 of dual channel phase shifter44, respectively, as 70 indicated. The output 47b of the first channel 47 is coupled to the input of the transmitter amplifier 24, via transmission line 32b. The output of the receiver amplifier 28 is coupled to the input 49a of the second channel 49, via transmission line 32e. The connection 75 of the transceiver 12i"to antenna element26i (FIG. 1) is as previously explained.

During the transmit mode, as shown by the open arrows 13, in response to complementary control signals on lines 29il, Mil a microwave signal fed to 80 common port 20a from the radarsystern 11 is coupled to branch port 19a. Such signal from branch port 19a is coupled to the input 47a of the dual channel phase shifter44. The signal is shifted in phase and coupled to the transmitter amplifier 24 and to the antenna 26, as 85 previously described. During a receive mode, as shown by the closed arrows 15, in response to the complements of the previous control signals on lines 29il, T9-i the microwave signal fed to the common port 20cfrorn antenna 26i is coupled to the branch port 21 c 90 and thusto the receiver amplifier 28. The signal atthe output of the receiver amplifier 28 is fed to the input 49a of the phase shifter44.The signal shifted in phase isthen fed to the T/R switch 18a to the radarsystern 11, as previously described.

Referring nowto FIG. 5, a single channel digitally controlled phase shifter40 suitable for use in trans ceiver element 12i (Fig. 2) and transceiver element 12i' (Fig. 3) is shown to include a plurality of cascade interconnected stages 40a-40d with like parts of each 100 stage being designated by the same n6meral. An - exemplary one of such stages 40a-40d, here stage 40a, is discussed in detail in conjunction with FIGS. 6-8.

Referring now to FIG. 6, the phase shifter stage 40a is formed on a substrate 41 here GaAs having a ground 105 plane 43, as shown. Referring also to FIGS. 7,8 the phase shifterstage 40a includes a microwave trans mission line 512, here having an impedance of 50 ohms, coupled to an input impedance matching circuit 513. Transmission line 512 is here fed by a microwave 110 frequency signal from transmission line 32b (Fig. 2).

Input impedance matching circuit 513 is here used to match the input impedance of the phase shifter stage 40a to the charactertic impedance of the transmission line 512. The input matching circuit 513, here includes 115 a first transmission line section 514, having a react ance which is primarily inductive, coupled in shunt to the input transmission line section 512, via a bottom plate 526c of a capacitor 526. Bottom plate 526c of capacitor 526 is coupled to one end of the shunt 120 mounted transmission line section 514. The upper plate 518a of a second series connected capacitor 518 is coupled to line 516 and the bottom plate of 518 is coupled to ground by a via hole 518b, as shown.

Ground pad 522 is coupled to ground by a via hole 125 connection 522a. As shown in Fig. 6B, capacitor 526 is formed on the top surface of the substrate 41 here includes atop plate 526a which is coupled via an air bridge 526d to the strip conductor portion of a transmission line 528. Aligned underthis top plate is a 130 bottom plate 526c of evaporated gold formed on the substrate 41. The top plate 526a and bottom plated 526c are separated by a 5000 Angstrom (A) layer 526b of silicon nitride (Si3N4). The bottom plate 526c has a finger 526e (Fig. 6) which is used to connectthe second circuit element, here transmission line section 514, to the capacitor 526. The connection is provided by a metal to metal contactwhich couples to the bottom plate 526c. A second transmission fine section 516, here having a reactance which is primarily inductive is coupled in shunt between capacitors 518 and 526. The connection of capacitor 518 to inductor section 516 provides the bias feed 520 forthe gate electrode. The input matching circuit 513further includesthe third transmission line section 528 here also having a reactance which is primarily inductive, connected between thejunction of capacitor 526 with shunt mounted transmission line section 516 and a common inputjunction 532. The phase shifterstage 40a further includes a FETswitch 530 having a dual gate FET, 530a-530b, as shown. FET's 530a and 530b includefirst gate electrodes 532a-532b coupled to the common junction 532, second gate electrodes 534a, 534b, separate drain electrodes 536a, 536b and separate source electrodes 538a, 538b. FETs 530a, 530b are here connected in a common (grounded) source configuration. FET530a, 530b arefabricated such thatthe gains and phases provided by each FET to signalsfed to the gate electrode and coupled to the drain electrode are substantially equal. In other words, IS21 la, the fraction of power coupled to the drain electrode 536a of 530a from a signal on gate electrode 532a substantially equals, IS21 1b, the fraction of power available atthe drain electrode 536b of FET 530b from an incident input signal provided signal gate electrode 532b of FET 530b. Similarily, q) S21 Ja 16e. S21 Jbthat is, the phases of the instantaneous power delivered to each drain electrode of FET 530a, 530b are substantially equal. Control gate efectro des 534a, 534b are fed control signals on lines 29i2a, Oi2a (Fig. 2). These control signals are used to control the coupling of an input signal fed to the gate electrode 532a, 532b to the corresponding drains 536a, 536b of FET's 530a, 530b. High frequency components in the signals on control lines 29i2a, 29i2a are shorted to ground, via capacitors 527a, 527b. The drain electrodes 536a, 536b are electrically connected to identical impedance matching circuits 545a-545b, as shown. The matching circuit 545a (Fig. 8), here includes a first transmission line section 548a coupled in series between the drain electrode 536a and a coupling capacitor 552a. A second transmission line section 549a is coupled in shuntwith the junction of the first transmission line section 548a, the bottom plate of capacitor552a, and an upper plate of a dc blocking capacitor 544. The bottom plate of the dc blocking capacitor 544 is connected to ground by a via hole connection 544a (Fig. 6). The impedance matching circuit 545b is formed in a similar manner on the substrate 41 (Fig. 6) forthe drain electrode 536b. The impedance matching circuit 545b includes a transmission line section 548b, a coupling capacitor 552b, and a second transmission line section 549b, coupled to the drain electrode 536b in a similar manner as the corresponding elements of impedance matching cir- cuit 545a. The common connection of transmission line sections 549a-549b and the de blocking capacitor 544 provides the bias feed 546for drain electrodes 536a, 536b. As shown in Fig. 6A, the bias feed 542 here is insulated from the transmission line section 548b by a conventional air gap plates overlay. In general, such overlays are here used in all embodiments to insulate such crossing siInal path. The upper plates of coupling capacitors 552a-552b of the impedance matching circuits 545a, 545b respectively, are integrally formed with the strip conductor portion of transmission lines 554a and 553, respectively. Transmission line 554a has an electrical length which provides a phase shift (p, +A (p, to an input signal coupled thereto and transmission line 553 has an electrical length which provides a phase shift of q), to an input signal coupled thereto. Such pair of transmission lines 554a, 553 as shown in FIG. 9a and described in more detail hereinafter provides one path having an unique phase shift increment A (Pa. Each second end of transmission 85 line section 554a, 553 is coupled to a corresponding input port 565,567 of a conventional three port coupler, which couples powerfrom two input ports and provides the coupled powerto an output port, via branch arms 564,566. Such a coupler is described in an article entitled "GaAs Monolithic Lange and Wilkinson Couplers" by Raymond C. Waterman Jr. et al, IEEE Transactions on Electron Devices, Vol. ED-28, No. 2, February 1981. The output of the three port coupler is electrically connected to an output port 570.

Capacitors 518,526,544,552a, 552b, 527a and 527b are here formed in a similar manner, as explained for capacitor526.

In operation, an input signal fed to transmission line 512 is coupled to each gate electrode 532a, 532b. Such 100 signal is coupled to one of the drain electrodes 536a, 536b selectively in accordance with the control signals fed on lines 29i2a, T9i2a to the control gate electrodes 534a, 534b. If the input signal in response to such control signals on lines29i2a, ni2a is coupled to drain electrode 536a, the phase of such signal is shifted by an amount 4), + A(p. through transmission line 554a.

Conversely, the electrical path from drain electrode 536b to the coupler 560 provides a pathlength corresponding to a phase shift of (pl. Thus, if in 110 response to the control signals on lines 29i2a, f9i2a, the input signal is coupled to drain electrode 536b, the phase of such signal at the output 570 is shifted by an amount of (p, through transmission line 553. Thus, a phase shiftof an input signal of 4), or 4), + A4)a atthe output 570 is selected in response to control signals on lines 296a,196. A plurality of such stages are cascade interconnected to form the phase shifter40 (Fig. 5). Each stage has two paths which correspond to phase shifts of an input signal of (p, through one path an amount (p, +A q)l through the second path where i is the number of the stage. For, four cascade interconnected stages, the phase shift A (pi for each stage is here A(Pa 180', A(i)b 900Y A(Pc = 45'and Aq)d = 22.50.

Referring again to FIG. 5, with like parts in each stage being designated by the same numeral, the active non reciprocal phase shifter 40 used to produce an output signal at port 570d having a predetermined phase shift relative to an input signal on transmission 130 GB 2 158 997 A 5 line 512 includes four cascaded interconnected phase shifter stages 40a- 40d, as shown. Each phase shifter stage40a-40d realized in accordancewith Figs. 6-8, selectively provides a unique phase shiftto an input signal of A(p, = 180', A(Pb = 90', Aq), = 4Yand A(Pd = 22.5', respectively. Each phaseshiftstage includes a unique length of transmission line between output matching circuit545a and thethree port coupler 560. Each length of transmission line, in conjunction with the length of transmission line 553, provides each stage with a unique pathlength difference corresponding to the unique phase shift. In response to control signals on lines 29i2,,-29i2d, and 29i2a-_f9i2d selective combinations of phase shift increments of 00 or 1800, 0' or 90', O'or450 and 00 or 22.50 are provided by phase shifter stages 40a-40d, respectively of control signals fed by lines 29i2a to 29i2d and f9i2a to 9i2d are represented byAto D and Ato D, respectively. The phase shift (p of an input signal through phase shifter 40 may be represented by the following logical equation as: g) = [(A((pi + A (pJ + A (1)1) + (13(1), + A (Pb) + B((pl)) + (C((pl + A (p,) + C (g),) + (D((pl + A(Pd)+ D(1)1)1. The phase shifter40, thus, is used to varythe phase of a signal fedto transmission line 512 of stage40afrom Oto3601n here 22.5'phase shift increments.

Referring nowto FIGS. 9A-913 transmission line sections 553 and 554a-554d used to provide unique incremental phase shiftsfor stages 40c-40d respectively, of the phase shifter40b shown in FIG. 5, have like parts being designated by the same numeral. The transmission lines 553 and 554a-554d are coupled to the input ports 565,567 of the three port coupler 560, having a thin film load resistor 562 and branch arms 564,566, and to a portion of the impedance matching networks 545a-545b, as shown. The transmission lines 554a-554d are formed on the semi-insulating substrate 41 by strip conductors 555a-555d and 557, respectively, and the ground plane 43, which is separated by a dielectric, here the semi-insulating substrate 41. Strip conductors 555a-555d and 557 are designed to provide the corresponding transmission lines 554a-554d and 553 each with a 50 ohm characteristic impedance. The transmission lines 554a-554d each have an electrical length equal to a corresponding precise fractional wavelength A J2n, with respect to transmission line section 553, where A, is the wavelength of the nominal or centerband operating frequency (fc) forthe active phase shifter n is the total number of stages. Thus, transmission line section 554a has a pathlength (A(p.) equal to A c/2 with respect to transmission line section 553. In a similar manner, the path lengths for segments 554b-554d with respect to transmission line 553 are AJ4, AJ8, and AJ1 6. Thus, the transmission lines 554a-554d, with respeetto transmission fine section 553, here represent pathlength differences corresponding to a phase shift of an applied signal with respect to the phase of such signal of 1800,900,450 and 22.5', respectively.

Referring nowto FIG. 10, a dual channel phase shifter44 having channels 47 and 49 which is suitable for use in the transceiver 12i" shown in FIG. 4 includes four one bit phase shifter stages (P.S. Stages) 44a-44d cascade interconnected together, as shown. The dual channel phase shifter stages 44a-44d are here identic- 6 GB 2 158 997 A 6 al exceptforthe pathlength differences (phase shift increment) (A(pi) forming the phase shift networksof each stage. Each channel ofthe dual channel phase shifter provides one of two signal paths, such path being selected in response to control signals fed on 70 lines 29i2,-29i2d and!9i2a--29i2d- Such paths provide either a phase shift of (p, ora phase shift of q), + Aq)l where i is the number of the stage. The phase shift increments (A q)i) for each of the four stages 44a-44d shown in FIG. 10are A4),, = 18001 A(Pb= 90orWr A(Pc 75 = 450 and A 4)d = 22.5 for stages 44a-44d, respectively as explained in conjunction with Figs. 9a-9d.

Referring nowto FIG. 11, an exemplary one of such phase shifterstages, here phase shifter stage 44a is shown. The phase shifter stage 44a includes FET's 80 530a-530d each having a pair of gate electrodes 532a-532d, and 534a-534d, a drain electrode 536a 536d, and a common source electrode 538. FET's 530a-530d are here realized as a double pole double throw FETswitch 530 of a type disclosed in U.S. Patent 85 No. 4,313,126filed May 21,1979, and assigned to the assignee of this invention. Each of the FET's 530a-530d are here connected in a common (grounded) source configuration, as shown. Each FET 530a-530d is formed on the substrate 41 within close proximity to 90 the other FET's 530a-530d, as shown. FETs 530a-530d arefabricated such that gains and phases provided to an inputsignal are substantially equal, as explained in conjunction with Figs. 6-7.

Thefirst phase shifter channel 47 includes a 95 microwave transmission line 512, here coupled to the transceiver 12i" (Fig. 4), via transmission line 32a providing a signal inputforthe phase shifter stage 44a. The microwave transmission line 512 is electrical- ly connected to an impedance matching circuit 513a previously described in conjunction with FIGS. 6-8. Matching circuit513 is electrically connected to the common inputjunction 532. Inputjunction 532 is coupled to input gate electrodes 532a, 532b of FET's 530a, 530b, respectively. Signals fed on lines 29i2at '296 from the radar system 11 (Fig. 1) are fed to the second gate electrodes 534a, 534b for controlling the conduction of an input signal on input gate electrodes 532a, 532b to the corresponding drain electrodes 536a,536bof FET530a,530b, respectively. High frequency signal components on control signals fed onfines29i2at 29i2a are shorted to ground by capacitors 527a, 527b. An input signal fed equally to input gate electrodes 532a, 532b is selectively cou- pled, to the corresponding drain electrode 536a, 536b, in accordance with the control signals on lines 29i2a, 29i2a fed to the control gate electrodes 534a, 534b. The drain electrode 536a is electrically connected to an impedance matching network 545a as described in conjunction with FIGS. 5-7. The drain electrode 536b is 120 similarly, electrically connected to the impedance matching network 545b, as shown. The impedance matching network 545a is coupled to here, the microwave transmission line 554a. In a similar man- ner, the impedance matching network 545b is coupled 125 to the microwave transmission line 553a. Each second end of transmiusion lines 553a and 554a is coupled to the pair of input ports 545,567 of the conventional three port coupler560.

The second channel 49 of digital phase shifter stage130 44a includes microwave transmission line 512'coupled to transceiver 12i" (FIG. 4) via transmission line 32g (Fig. 2) for providing the signal input for channel 49. The microwave transmission line 512'is electrically connected to an impedance matching circuit 513'as previously disclosed in conjunction with FIGS. 5-7. A second matching circuit 513'is electrically connected to a common junction 532'. Common junction 532'is electrically connected to input gate electrodes 532c, 532d of FET's 530c, 530d. Control gates 534c, 534d of FET 530c, 530d are electrically connected to gate electrode pads 524 and 527, respectively. The control gates 534c, 534d are fed signals on lines 29i2a, 29i2a from the radar system 11 (Fig. 1) for controlling conduction of an input signal on input gate electrodes 532c, 532d to the drain electrodes 536c, 536d of FET's 53pa, 530b, respectively. Drain electrodes 536c-536d are electrically connected to impedance matching networks 545c-545d as disclosed in conjunction with FIGS. 6-8. Transmission lines 553'and 554a', are coupled between the impedance matching networks 545c-545d and the three port coupler 560'. The three port coupler 560'is electrically connected to output port570'.

Thetotal pathlength difference of the connection of drain electrode 536a tothethree port coupler560,for channel 47 isthen selected to provide a corresponding phase shiftequal to (p, + as explained in conjunction with FIGS. 9a-9d.Thetotal pathlength difference of the connection of drain electrode 536bto thethree port coupler for channel 47 is selected to provide a corresponding phase shiftequal to q),. Thus, the phase of a signal appliedto the gate electrodes 532a, 532b is shifted by an amount (p, + A(P,, or 4), selectively in accordancewith control signalsfed to control gate electrodes 534a, 534b. In the same manner, transmission lines 553', 554a'provide pathlengths to channel 49 between drains 536c, 536d of q), + A q), or 4)1.

Referring again to Fig. 10, the dual channel phase shifter44 having channels 47 and 49 has stages 44a-44d, each stage providing a unique phase shiftto an applied signal. Each channel provides selective combinations of phase shift increments A(Pa 1800, Aq)b = 900, A(pc = 45', and A(Pd = 22.5'in response to control signals on lines 296-296dj 29i2a- 29i2dReferring nowto FIG. 12, the phase shifter stage 44a is shown, formed on a semi-insulating substrate 41 having a ground plane 43 on one side thereof, as shown. A low inductance ground connection 537 is here made through the source electrode region 538. Parallel plate capacitors such as 526 are formed on the substrate 41, as previously described in conjunction with FIG. 6B. Crossing signal paths are insulated one from another by conventional air gap plated overlays as described in conjunction with FIG. 6A.

Referring also to FIG. 5, the net overall gain for each four bit phase shifter 40 and 44'is approximately 8 decibels (db) or approximately 2 db per stage. Each stage contributes 3 db of loss from splitting of the input signal and another 3 db of loss due to power recombining atthe three port coupler 560. The total losses dueto parasitic losses and the matching networks are less than 1 db. Allowing for substantial mismatch, a gain of approximately 8 db generally is 7 GB 2 158 997 A 7 realizable from a dual gate FET, operating at X-band, provided by each of the equal electrical length for example. Thus, a net gain of approximately 2 db transmission line sections 1322,1324 and 1326 of per stage or approximately 8 db forthe phase shifters which the output signal passes through from a of FIG. 9 and FIG. 12 is realized. Since onlyfour FETs, selected one of the drain electrodes 1336a-1336d to one perstage, at any given time are operating for each 70 the output port 1331.

phase shifter, 40,44the d.c. power consumption will In operation, an input signal is coupled or decou be fourtimes thatfor one FET. pled between the gate electrodes 1332a-1 332d and the Now referring to FIG. 13, an alternative embodiment corresponding drain electrode 1336a-1336d selective for a four bit digitally controlled phase shifter40' ly in accordance with control signals fed to control suitable for use in transceivers 12i and 12V (Fig. 2 and 75 gate electrodes 1334a-1334d on lines 29i2,-29i2d pro Fig. 3) includes a firststage 40a'having a single pole vided by suitable modification of the radarsystem 11 fourthrow (SP4T) FET switch 1330 and a second stage (Fig. 1). Signals on control lines 29i2.-29i2d are here 40b'having an SP4T FETswitch 1370, as shown. The logical control signals. One of such signals on lines SP4T FETswitches 1330 and 1370 are here of a type 29i2,,-29i2d is selected to be in an "on" state,while the disclosed in the above mentioned U.S. Patent No. 80 remaining ones of such signals on lines 29i2,-29i2d are 4,313,126. Each stage 40a', 40b'isformed on a placed in an "off" state, thus placing only one FET of substrate (not shown), having a ground plane (not the FETs 1330a-1330d, in a conductive state and the shown). remaining ones of such FET's 1330a-1 330d, in a The first stage 40a'of the four bit digital phase non-conductive state. Similarilythe output signal shifter 40'further includes FET's 1330a-1330d, as 85 from the first stage is coupled or decoupled between shown. FET's 1330a-1 330d are fabricated such that the gate electrodes 1372a-1 372d and the correspond gains and phases provided to an input signal are ing drain electrode 1376a-1 376d selectively in re substantially equal, as explained in conjunction with sponse to control signals fed to control gate elec Fig. 5-7. Each FET 1330a-1330d, includes a input gate trodes 1374a-1 374d, via lines 2961-296, as shown.

1332a-1332d, a control gate 1334a-1334d, drain elec- 90 In responseto a control signal fedto one of the trodes 1336a-1336d and a source region 1338. FET's control gate electrodes 1334a-1334d the correspond 1330a-1330d are here connected in a common ing one of the FET's 1330a- 1330d is placed in a (grounded) source configuration.A low inductance conducting state, coupling the inputsignal on the ground connection is here madefrorn the source input gate electrode of such FET, to the corresponding electrode 1338 to the ground plane 43 (not shown) by a 95 drain electrode of such FET. The remaining FET's of conventional via hole connection. the FET's 1330a-1330d are held in a nonconducting A microwave transmission line 512, here having an state by control signals fed to remaining ones of the impedance of 50 ohms is coupled to an impedance control gates 1334a-1334d. Thus, a signal coupled to matching circuit 513, as previously explained in thetransmission line 1320 from drain electrode 1336a conjunction with FIGS. 4-6. The impedance matching 100 will have a net phase shift of 3Aq) with respectto circuit is coupled to input gate electrodes 1332a- phase of an input signal on drain electrode 1336a, 1332d. The drains 1336a-1336d are electrically con- becausethe signal coupled from drain electrode nected to identical impedance matching networks 1336a will passthrough the three phase shift sections 545a-545d of a type previously described in conjunc- 1322,1324 and 1326 of transmission line 1320 before tion with FIG. 8. Impedance matching networks 105 arriving atthe output port 1330. In a like manner, a 545a-545d are each coupled to a transmission line signal applied from the drain electrode 1336b to 1320 having a characteristic impedance Z., here 50 transmission line 1320 will have a net phase shift of ohms. Transmission line 1320 is terminated at one 2Aq), a signal applied from drain electrode 1331 c to end in a resistor 1322, here having a value equal to 50 transmission line 1320 will have an incremental phase ohms, the characteristic impedance of the transmisshift of Aq), and a signal applied from drain electrode sion line 1320. The resistor 1322 is coupled in shunt 1336d to transmission line 1320 will have an in between the transmission line 1320 and ground. Drain cremental phase shift of O'with respect the signal on electrode 1336d is electrically connected to the end of drain electrode 1336d. Thus by selective application of transmission line 1320 through the impedance match- control signals fed to control gates 1334a-1334d an ing network 545d. Drain 1336c of FET 1330c is 115 incremental phase shift of 3A(p, 2Aq), A(p, or 00 may electrically connected to transmission line 1320, be obtained. By selecting the electrical length of each through the matching network 545c defining a section incremental phase shift (A (p) of the first stage equal to of transmission line 1326, drain electrode 1336b of FEJ be 22.5, a total phase shift of up to 67.5'is provided by 1330b is electrically connected to transmission line the first stage. The phase shift provided by the 1320 through the matching network 545b defining a 120 matching network 545a-545d is the same for each section of transmission line 1324, and drain electrode drain electrode matching circuit and thus does not 1336a of FET 1330a is electrically connected to affectthe differential phase shift produced.

transmission line 1320, through the matching network The output of the first stage 40a'is electrically 545a, defining a section of transmission line 1322. connected to the input of the second stage 40b', as Here, all the transmission line sections 1322-1326 125 shown. The second stage 40b'of the four bit digital have the same electrical length and thus each section phase 40'is identical to the first stage 40a'except for shifts the phase of an applied signal by an equal the electrical length of the transmission line 1320'. In a amount. The total phase shift of an output signal with like manner, as discussed forthe first stage 40a', the respectto the phase of the input signal fed through second stage of the four bit digital phase shifter40' transmission line 512 is the sum of the phase shifts 130has drain electrodes, here 1376a-1376d electrically 8 GB 2 158 997 A 8 connected to a portion of a transmission line 1320'.

The incremental phase shift of transmission line 1320' is here setto 90% Thus, a total phase shift of 27Watthe output 133Vis obtainable in the second stage 40W.

This in combination with the first stage 4Whaving a total available phase shift of 67.5 provides the four bit digital phase shifter40% having a capability of providing a 360'phase shift, in 22.5' increments.

Now referring to FIG. 14, a digitally controlled phase shifter section 50 suitable for use in the transceiver 12i 75 (Fig. 2), by replacing TIR switches 18b, 18d and phase shifter40, and fortransceiver 12V' (Fig. 4) by replacing phase shifter44, includes the single channel phase shifter40'of FIG. 13, and FET's 1410a-1410d. Each FET 1410a-1014d has a signal gate electrode 1412a-1412d, 80 a control gateelectrode 1414a-1414d, drain electrodes 1416a-1416d, and source electrodes 1418a-1418d, as shown. FET's 1410a 1410d are connected in a common (grounded) source configuration. The signal gate electrodes 1412a, 1412b of FET's 1410a, 1410b are here coupled to the transmission lines32a and 32g of thetransceiver 12i (FIG. 2) respectively, through a pair of impedance matching circuits 513, as described in conjunction with FIG. 5. Each drain electrode 1416a, 1416b is coupled to the phase shifter40'via transmis- 90 sion line 1420. The output of the phase shifterWis coupled to the input gate electrodes 1412c, 1412d of FET's 141 Oc, 141 Od, respectively, via transmission line 1422 and impedance matching circuit 513. The drain electrodes 1416c, 1416d are coupled to transmission 95 lines 32h and 32d, respectively, of the transceiver 12i (FIG. 2). In operation, one of a pair of input signaisfed to the signal gate electrodes 1412a, 1412b of input channels 1430,1432 is selectively coupled to the corresponding drain electrodes 1416a, 1416b in re sponse to signals fed to control gate electrodes 1414a, 1414b on lines 29il, 29il. Such selectively coupled signal is fed to the phase shifterWand the phase of such signal is shifted in response to control signals 29i2a-29i2h as previously doscribed. One of the pair of 105 output channels 1434,1436 is selected, by signals on lines 2gil, 2-9i, fed to control gates 1414c, 1414d. The phase shifted signal, is coupled to the input gate electrodes 1412c, 1412d of FETs 141 Oc, 141 Od. The phase shifted signal fed to each of the input gate electrodes 1412c, 1412d is coupled to one of the drain electrodes 1416c, 1416d selectively in responseto control signals on lines 29il, 29i, fed to control gates 1414c, 1414d, respectively, as previously explained.

The signal on the selected one of the drain electrodes 115 1416c, 1416d is coupled to transmission lines 32h during the receive mode or32d of the transceiver 12i (FIG. 2) during the transmit mode.

Assuming one miliiwatt of power consumption per FET, the power consump..:on of the phase shifter 50 is four milliwatts since four FET's are conducting at the same time. Two FET's of the four reciprocating switches conduct and one FET in each of stages 40a' and 40b'(FIG. 13) conducts, during operation of the phase shifter. The net overall gain forthe phase shifter section 50 is approximately 4 db. This assumes a 6 db loss due to input signal division into the four channels, FET's 1330a-633pe of phase shifter stage 40a'(FIG. 13) and 6 db of loss due to input signal division forstage 40b'(FIG. 13). In addition, there is a loss of 3 db in each stage (40a', 40W) attributable to the terminating resistors 1322 fortransmission lines 1320 and 1320' (Fig. 13), and there is a loss of 1 db per stage due to parasitics and the matching circuits. These losses are partially compensated for by a minimum of 8 db gain for each FET resulting in a net loss of at most 2 db per stage. Moreover, the FET switches 141 Oa-141 Od contribute 16 db of gain (8 db perswitch, two switches active at one time). This gain is reduced, however, by 3 db due to signal division into the two channels of FET's 141 Oa, 141 Od and 1 db due to pa rasitics and the matching circuits. Thus, the net gain for the phase shifter 50 is approximately 4 db.

Referring nowto FIG. 15, an alternative embodiment of an phase shifter40" suitableforuse in transceiver 12i (Fig. 2) and 12V(Fig. 3), includes a first phase shifter stage 40a% a second phase shifterstage 40W', and a third phase shifter stage 40C cascade interconnected, as shown. Each phase shifter stage 40a% 40W' and 40c" is similarto the digitally controlled phase shifterstage 40a described in conjunction with FIGS. 6-8. Phase shifter stage 40a" is here used, however, to provide a variable continuous phase shift between O'and 90'. Phase shifting stage 40Wis used to produce a phase shift of (p = 00 or a phase shift of (p = 900, and phase shifter stage 40c" is used to produce a phase shift of 1) = 00 or g) = 180'. The cascade interconnection of phase shifter stages 40a% 40W' and 40c" provides the phase shifter 40---which is capable of varying the phase of an input signal continuously overthe range of Wto 360'.

Referring also to Fig. 16- Fig. 17, an exemplary one of the stages 40a"4W' here 40a" is formed on the su bstrate 41 having a g round plane 43. The phase shifter stage 40a" is coupled to transmission line 32b of the transceiver 12i (FIG. 2). The phase shifter stage 40a" includes a transmission line 512 coupled between the input matching network 513 as explained in conjunction with FIG. 5 and thetransmission line 32b of transceiver 12i (FIG. 2). The matching network 513 is coupled to input gate electrodes 532a, 532b of a pair of FET's 530a-530b, as shown. FET's 530a-530b further include control gate electrodes 534a-534b, source electrodes 538a- 538b, and drain electrodes 536a- 536b. FET's 530a-530b arefabricated, such that gains and phases provided to an input signal fed to the input gate electrodes 532a, 532b are substantially equal at the drain electrodes 536a, 536b, as explained in conjunction with FIG. 6. FET's 530a-530b are here connected in a common (grounded) source configuration, as shown. The control gate electrodes 534a-534b are fed voltage level control signals on control lines 29i3a, 296b. The radar system (Fig. 2) provides the control signals on lines 296a, 296b (not shown in Fig. 2). The levels of such signals on the control lines 296., 296b are used to control the operating point of each FETand hencethe amplitude of signals coupled to the drain electrodes 536a, 536b. The drain electrodes 536a, 536b are electrically connected to capacitor 544 and impedance matching networks 545a, 545b as described in conjunction with FIGS. 6-8. In the preferred embodiment of the invention, the impedance matching networks 545a, 545b are electrically connected to a conventional four port or quadrature coupler 1560. Such a coupler is described in an article 9 GB 2 158 997 A 9 entitled "GaAs Monolithic Lange and Wilkinson Cou plers" by Raymond C. Waterman, Jr. et al, IEEE Transactions on Electron Devices, Vol. ED-28, No. 2, February 1981. A quadrature coupler is here used to couple input signals on each input of th coupler, in quadrature, to the output. In otherwords, the phase of the input signal from drain electrode 536b as coupled to the output 1570 of the couplerwill lag the phase of the input signal from drain electrode 536a as coupled to the output 1570 of the coupler by 90'.

Thus, unlike prior embodiments of the invention where signalsfed to the control gate electrodes 534a-534b are complementary pairs of control signals, such signals provided to place an FET in an off-state or an on-state, the signals fed on lines 29i3a, 29i3b to the control gate electrodes 534a, 534b, here are selectable voltage levels between pinchoff and zero volts "on" levels of such FET.

An outputvoltage signal V,,, when measured atthe 75 drain electrode, of an input signal Vi fed to the input gate electrode is given as: Vi = A(,eit, is VO = BA.ej(" ' ), for embodiments disclosed in conjunction with FIGS. 5-14where B is the gain and ip is the phase provided to the input signal by the FET. However, if the 80 control signals on lines 29i3a, 29i3a fed to the control gates 534a-534b provide voltage level signals which change the operating point of the FET between the off state and the on state, the FET's 530a, 530b no longer function as switches, and, instead the FETs 530a, 530b 85 function as variable gain amplifiers. When the output voltage V O(A) of the FET 530a is a function of the control gate voltage V(,) fed to control gate 534a, the portion of the output voltage Vt at the output of the coupler 1560 from the voltage V. (A) is given as: V. = BAA,3i('t ' 90 lp+ Apn),where BAisthe gain of FET530a asafunction of the control gate voltage, '"n is the phase shift corresponding to the pathlength between the drain electrode of the n th FET and the output of the coupler 1560. The output voltage of FET 530a and FET 530b may be represented as:

V O(A); V,,(B) where Vc,(A) = BAA.ej(" ' q1); VO(B) = BB A,04)t +0 Since the quadrature coupler 1560 combines the two input signals V W and VO(B) in quadrature, the 100 output voltage at the coupler 1560 maybe represented as:

VoT VO(A) -jV,,() or VoT = BAAei('ot + 4' + 'I>A) + BBA,,e(w' + q' + ''I)B) or VoT = A.ej(' ' ' ' ''4A) IBA + BBe -jTtf2] 105 which maybe simplified to:

VoT = AJ13WO where B' = (BA 2 + BB 2p/2 and tan 0 = BB/BA.

Thus,the phaseof an inputsignalVi (Fig. 15) isshifted in accordance with the ratio of the amplitudes VO (A), VO (131 of such input signal as coupled to each drain electrode 536a, 536bcoupled in quadratureto provide the signal V.t (Fig. 15) at the output of the quadrature coupler 1560.

Thus by selecting the relativevalues of B, and B2 any phase between 0 and n/2 maybe realized. Since only the ratio of B, and B2 determines the phase, it is possible to keep B'and hence the overall gain of the stage 40a" substantially constant. This is accom plished by separately adjusting the values of B, and 132. This provides an additional flexibility of amplitude control along with phase adjustment.

As an example, for a minimum phase shift increment of rill 6, the values of B, and B2 which will yield all eight phase shift increments between 0 and rLI2 with substantially constant amplitude B'are given in the Table below.

TABLM Ph- bl Shift whe 0 1.000 /16 3V/16 0 0:1733 2 r 4 07 3-/8 1 0.383 7/16 1 0.195 /2 1 0 a 1 bIB - al 0:1E915 0 3 3 b2V " B2 0 556 0:707 0. a32 0.924 The minimal phase shift increment provided by the variable phase shift stage 40a" is limited only bythe degree of control of the voltage applied to the control gate electrodes 534a-534b of FET 530a-530b of phase shifter stage 40a".

Phase shift stage 40a" is cascade interconnected to phase shift stage 40b", as shown. The phase shift stage 40b" is identical to phase shift stage 40a". The only difference between the stages 40a" and 40b", is the technique for producing the phase shift. A phase shift of 00 or 900 provided by phase shifter stage 40b" is determined by controlling which FET 530a-530b is biased in the on state, as previously described in conjunction with Figs. 6-8.

Phase shift 40c" stage is similar to phase shift stage 40a" exceptforthe inclusion of an additional 90'of pathlength difference such as transmission line section 554b (Fig. 9b) coupled between the impedance matching network 545a and the coupler 1560.

Referring nowto FIGS. 18-19, bidirectional switch 18a having a first branch port 19a coupled to transmission line 32a (Fig. 2), a second branch port 21 a, coupled to transmission line 32h (Fig. 2), and a common port 20a coupled to transmission line 33i, (Fig. 2), is shown. The bidirectional switch 18a is formed on the substrate 41, having the ground plane 43 formed on the bottom surface of substrate 41, as shown. FETs 50a50b are formed on a portion of the substrate 41. In the preferred embodiment, FET's 50a, 50b include a plurality of FETcells, each cell having a reactive component (C") coupled between the drain and source electrode of each cell as shown in Fig. 20. A network, here the FET 50a is formed interconnecting each one of such drain electrodes of each FETcel I. Such network is formed having a characteristic impedance equal to the characteristic impedance of the transmission line sections 58a, 58b, here 50 ohms. The network is formed as follows: a length (d) of a microstrip conductor 59 having a distributed inductance per unit length (LL) and a distributed capacitance per unit length (CL) is chosen such that when coupled between the cells of each FET it will provide such networkwith the predetermined characteristic impe- dance given as: Z, = (LL(CL + 2 (C"/d)))"2. The bidirectional switch further includes a pair of transmission lines 58a-58b, each having a electrical length substantially equal to one quarter of a wavelength (AJ4) whereXc is the wavelength of the nominal operating frequency for the circuit. The first drain electrode 54a of FET 50a is coupled between the first branch port 19a and to one end of transmission line 58a. The transmission line 58a is coupled between the branch port 19a and the common port 20a. A drain electrode 54b of a second FET50b is coupled to the second branch port 21 a, and one end of the transmission line 58b. The other end of transmission line 58b is coupled to the common port 20a. The sources 56a-56b of FET50a-50b are electrically connected to ground. The gate electrodes 52a-52b of FET's50a-50b are electrically connected to control lines 29il, 29il, and are fed complementary signals on such lines.

TheT1R switch 18a is used to couple a signal on transmission line 33i of the transceiver 12i (Fig. 2) fed to the common port 20a to one of the branch ports 19a or2la in accordancewith a pairof complementary control signals on lines 29il, 29i,,fedtogate electrodes 52a, 52b. The T/R switch 18a couples an input signal from common port 20a to branch port 19a, as follows: the control signal online 29il, is fed to the gate electrode 52a of FET 50a, placing FET 50a in a nonconducting state; correspondingly, the control signal fed on line 29i, is applied to the gate electrode 52b of FET50b placing FET 50b in a conducting state; by placing FET50b in a conducting state, a short circuit@ (low impedance path to ground) is produced atthe end 58b'of transmission line 58b coupled to the drain electrode 54b; one quarter of a wavelength from this point (atthe second end of transmission line 58b) the short circuit atthe first end appears as an open circuit0(high impedance) to a microwave frequency signal having a wavelength substantially similarto the wavelength of the corresponding centerband frequency of operation forthe bidirectional switch 18a. The transmission line 58a and the open circuit resulting from FET50a being in a nonconducting state, appears as a 50 ohm transmission line atthe common port side 58a'of the transmission line 58a. Thus, a signal on common port 20a is coupled to the branch port 19a. In a similar manner, by changing the state of the complementary pair of control signals on lines 29il, 29i,,amicrowave frequency signal on common port 20a maybe coupled to the branch port 21 a.

Having described preferred embodiments of the invention, itwill now become readily apparentto those of skill in the artthat other embodiments incorporating the invention may be realized. It is felt, therefore, thatthis invention should not be limited to the disclosed embodiments but rathershould be limited onlyto the scope of the appended claims.

Matter described hereinbefore is described and claimed in co-pending patent application No. 8305509 from which the present application is divided.

Claims (1)

1. A phased array antenna for producing collimated and directed beams of transmitted and received electromagnetic energy comprising:

an array of antenna elements; a plurality of transceiver elements each one of such elements being coupled to a corresponding one of such antenna elements each one of the transceiver elements comprising:

means for providing gain and phaseto electro- magnetic energy passing therethrough; and GB 2 158 997 A 10 means for directing transmit and received electromagnetic energythrough the gain and phase shift means.

Printed in the United Kingdom for Her Majesty's Stationery Office, 8818935, 11185, 18996. Published at the Patent Office, 25 Southampton Buildings, London WC2A lAY, from which copies may be obtained.