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GB2184288A - Oxidation inhibition of copper bonding pads using palladium - Google Patents
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GB2184288A - Oxidation inhibition of copper bonding pads using palladium - Google Patents

Oxidation inhibition of copper bonding pads using palladium Download PDF

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Publication number
GB2184288A
GB2184288A GB08614593A GB8614593A GB2184288A GB 2184288 A GB2184288 A GB 2184288A GB 08614593 A GB08614593 A GB 08614593A GB 8614593 A GB8614593 A GB 8614593A GB 2184288 A GB2184288 A GB 2184288A
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United Kingdom
Prior art keywords
copper
layer
angstroms
palladium
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB08614593A
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GB8614593D0 (en
Inventor
Hem P Takiar
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National Semiconductor Corp
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National Semiconductor Corp
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Filing date
Publication date
Application filed by National Semiconductor Corp filed Critical National Semiconductor Corp
Publication of GB8614593D0 publication Critical patent/GB8614593D0/en
Publication of GB2184288A publication Critical patent/GB2184288A/en
Withdrawn legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/40Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44Conductive materials thereof
    • H10W20/4403Conductive materials thereof based on metals, e.g. alloys, metal silicides
    • H10W20/4421Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being copper
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/012Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/075Connecting or disconnecting of bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/019Manufacture or treatment of bond pads
    • H10W72/01951Changing the shapes of bond pads
    • H10W72/01955Changing the shapes of bond pads by using masks
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251Materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251Materials
    • H10W72/252Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29Bond pads specially adapted therefor
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/551Materials of bond wires
    • H10W72/552Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5525Materials of bond wires comprising metals or metalloids, e.g. silver comprising copper [Cu]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/59Bond pads specially adapted therefor
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/921Structures or relative sizes of bond pads
    • H10W72/923Bond pads having multiple stacked layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/951Materials of bond pads
    • H10W72/952Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/981Auxiliary members, e.g. spacers
    • H10W72/983Reinforcing structures, e.g. collars

Landscapes

  • Wire Bonding (AREA)

Abstract

A copper bonding pad structure for the tape automated bonding of semiconductor devices includes a palladium anti-oxidation layer 30 over the exposed copper. The palladium layer has a thickness in the range from about 80 to 300 Angstroms, and is particularly suitable for use since it has a very low diffusivity into copper, even at elevated temperatures. In the preferred embodiment, the copper bonding pad structure comprises an aluminium layer applied directly over an aluminium metallization pad 12, a nickel layer 22 applied directly over the aluminium layer, and an overlying copper layer 24. The nickel layer inhibits the migration of copper into the aluminium, while the copper layer with palladium may be bonded directly to copper bump tape. In an alternative embodiment, a copper bump is formed directly over the copper bonding pad, which allows for bonding to a flat copper bonding tape. <IMAGE>

Description

SPECIFICATION Oxidation inhibition of copper bonding pads using palladium Background of the invention 1. Fieldofthe invention The present invention relates generally to tape automated bonding between copper bonding pads onsemiconductordevicesand lead frames orother external circuitry. More particularly, the invention relates to oxidation inhibition on the copper bonding pads.
Tape automated bonding is a method for simultaneously connecting a plurality of bonding pads on a semiconductor device to external circuitry, typically by connection to leads on a lead frame on which the device is to be mounted. The bonding pads are usually formed from copper and define the input and output terminals ofthesemiconductor device.
Tape automated bonding is accomplished using a metal tape, typically a thin coppertape or plated coppertape, having short connector beams formed therein. By aligning the tape with the semiconductor device, the inner ends of the connector beams may be bonded to the bonding pads on the semiconductor device in a single operation, typically thermal compression or reflow,to form innerlead bonds. Afterthe inner lead bonds are formed, outer lead bonds between the outer ends of the connector beams and the lead frame leads are formed and the excess tape excised.
In forming the inner lead bonds, it is necessary that a projection or bump be formed on one ofeitherthe connector beams orthe bonding pad. Such bump serves to provide the metal necessaryforforming the bond as well as for providing the necessary distance or offset between the connector beam and the semiconductor die. In either case, it is necessary that the copper bonding pad or bumped copper bonding pad be treated to inhibit oxidation ofthe copper, which oxidation would interfere with the bond quality and the resulting electrical contact with the connector beam.
Heretofore, oxidation ofthe copper bonding pad or bumped copper bonding pad has been accomplished by depositing a thin layer of gold over the top layer of the semiconductor device, typically by sputtering or using an electrolessgold plating bath. The gold layerwasusuallythin, having a thickness of about 500 A, and the inner leadswere formed in a conventional manner using either bumped coppertape orflat coppertape.
While the use of gold to inhibit the oxidation of copper is generally acceptable, itsuffersfrom certain drawbacks. In particular, when exposed to higher tem peratu res, the gold will diffuse into the underlying copper, leaving the copper exposed to oxidation. Such diffusion requires the use of thicker gold layers to adequately protectthe underlying copper, and in some cases diminishes the ability of the gold layerto protect the copper against oxidation.
For these reasons, it would be highly desirable to provide alternate methods for protecting copper bonding pads and copper bumped bonding pads against oxidation. In particular, it would be desirable to identify other protective coating materials which are electrically conductive, which are non-reactive in the environments likely to be encountered by the semiconductor, which display low diffusivity in copper, into which copper displays a low diffusivity, and which may be conveniently applied to the surface of the semiconductor device.
2. Description of the background art Tape automated bonding on semiconductor devices having bumped bonding structures is described generally in U.S. Patent 4,000,842. The tape automated bonding employing bumped bonding tape is described generally in U.S. Patent 4,209,355. The use of various znti-oxidation coatings, including gold, chromate, and copper phosphate, on copper bonding structures is described in U.S.
Patent 4,188,438.
Summary of the invention Improved methods for inhibiting the oxidation of copper bonding structures on semiconductor devices are provided. The copper bonding structures are ofthetypewhich are usedfortape automated bonding of the semiconductor to a lead frame or other external circuitry. Specifically, the copper bonding structuresform the inner lead bondswith the connector beams ofthe bonding tape. The process ofthe present invention is useful with both bumped bonding structures which are intended to mate with flat bonding tape, as well as with unbumped bonding structures which are intended to mate with bumped bonding tapes.
The method of the present invention comprises applying a layer of palladium as an oxidation inhibition layer over the copper bonding structures.
Preferably, the palladium layer is applied to a thickness in the range from 80 to 300 A, more preferably in the range from 100 to 200 A. Such application is normally accomplished by sputter deposition. It has been found that palladium, in contrasttothe gold oxidation inhibition layers of the prior art, displays a very low level of migration into the underlying copper layer, even at high temperatures. Moreover, copper resists migration into the palladium, even the same high temperatures. The palladium has further been found notto interfere with the formation of low resistance electrical connections between the bonding tape and the bonding structure, and is substantially non-reactive under the conditions to which the semiconductor is normally exposed.In particular, the palladium is highly resistant to oxidation under high oxygen environments at elevated temperatures.
Brief description of the drawings Figure 1 illustrates an aluminum metallization pad covered by a pair of insulating layers priorto formation ofthe copper bonding pad structure ofthe present invention.
Figure 2 illustrates the metallization pad of Figure 1 after a opening has been etched in the insulating layers to provide access to the metallization pad.
Figure 3 illustrates the exposed metallization pad of Figure 2 after aluminum, nickel and copper layers have been sequentially applied.
Figure 4 illustrates the metallization pad structure of Figure 3, further including a photoresistlayer formed thereover.
Figure 5 illustrates the structure of Figure 4, wherein the photoresist layer has been exposed and developed to remove all areas other than those overlying the metallization pad.
Figure Gillustratesthe copper bonding pad structure of the present invention,which has been formed by etching the copper, nickel, and aluminum layers and stripping the photoresist.
Figure 7 illustrates the copper bonding pad structure of Figure 6 having a palladium layer applied thereover to inhibit oxidation of the copper.
Figure 8 illustrates an alternative embodiment of the present invention, where the copper bonding pad structure of Figure 6 has a copper bump structureformed thereover, fu rther having a palladium layerto inhibit oxidation of the copper bump.
Description of the preferred embodiment The present invention provides an improved copper bonding pad structure intendedfortape automated bonding of semiconductor devices. The copper bonding pad structure is characterized by a final layer of palladium which acts to inhibit oxidation of the copper bonding pad structure, while at the same time allowing thermocompression bonding ofthe copper bonding padstructureto conventional copper bonding tape. The palladium layer is normally pure palladium, oran alloy consisting primarily of palladium, and is applied by sputter deposition orelectroless plating atthefinal stages of the water fabrication.
In the preferred embodiment, the copper bonding structure is formed ofthree metal layers deposited sequentially over an exposed aluminum metallization pad, which structure prevents the migration ofcopperfrom the bonding pad into the underlying aluminum. Although this is the preferred embodiment, it will be appreciated that the present invention wi 11 beequral Iy usefu with will other bonding pad structures which are presently known and which may be developed in the future. The present invention relates to the oxidation inhibition ofthe exposed copper on the copper bonding pad structure, and is not limited by the particular manner in which the copper is connected to the underlying circuit elements.
Referring now to Figures 1-8, the process for forming the copper bonding pad structures of the present invention will be described in detail. Figure 1 illustrates a semiconductor substrate 10 having an aluminum metallization pad 12 formed on its surface. Passivation layers 14 and 16 have been formed overthe metallization pad 12, in a conventional manner. In order to form the copper bonding pad structure of the present invention, it is first necessaryto provide an access opening through the insulating layers 14 and 16. This may be accomplished by conventional photolithographic techniques, to provide opening 18, as illustrated in Figure 2.
Afterformation of the opening 18, an aluminum layer 20 (Figure 3) may be formed directly overthe aluminum metallization pad 12, as well as covering the insulating layer 16. The aluminum layerwill typically have a thickness of at least 2,000 A, more typically being in the rangefrom 2,000 to 6,000 A, usually being about 4,000 A. Since the aluminum layer is being applied directly overthe aluminum metallization pad 12, the aluminum layer may be applied by sputter deposition, evaporation, or other conventional technique.
Afterthealuminum layer 20 is deposited, a nickel layer 22 is deposited directly over the aluminum layer. The nickel layer 22 will be deposited by conventional methods, typically by sputter deposition, and will form a nickel-aluminum alloy at the interface between layers 20 and 22. The thickness of the nickel layer will be sufficient to prevent migration of the copper into the aluminum, usually being at least about 2,000 A, more usually being in the range from 2,000 to 5,000 A, usually being about 3,OOOA.
Copper layer 24 is next deposited by sputter deposition to a thickness of at least4,000 , usually in the range from about 4,000 to 1 5,000 , more usually about8,000 . The copper layerservesto bond directly to the copper bumped tape in a conventional manner.
Afterapplyingthethreemetal layers 20, 22 and 24 ofthe metallization pad structure, a photoresist layer 26 (Figure 4) is applied overthesemiconductor device. The photoresist will be used to define the limitsofthemetallization pad structure. First, the photoresist is exposed and developed so that the photoresist is removed from most of the area of the semiconductor device, but remains overthe aluminum metallization pad 12, as illustrated in Figure 5.The copper and nickel layers 22 and 24, respectively, are then etched in a liquid etchant, such as nitric acid and hydrogen peroxide, followed by an aluminum etch in phosphoric/acetic acid mixture The etches are continued until the metal layers are substantially removed from all areas of the semiconductor device except those areas above the metallization pad 12 which is protected by the photoresist cap 26a (Figure 5). Photo resist cap 26a is then removed,andthecoppercleaned in a mild acid.
The resulting structure is illustrated in Figure 6.
The structure illustrated in Figure 6is generally suitableforthermocompression bonding to copper bonding tape. The exposed copper layer 24, however, is subject to oxidation when the semiconductor device is exposed to an oxygen-containing ambient. Such oxidation is undesirable since it interferes with the formation of a low resistance bond with the copper bonding tape.
Referring nowto Figure7, in afirstembodimentof the present invention, oxidation of the copper bonding pad structure 24 is inhibited by the application of a thin palladium layer 30 on top of the coppermetallization layer24. The palladium layer30 is applied overthe entire top surface of the semiconductor device by either sputter deposition of electroless plating. The palladium layer30 is then removed from al I a reas of the other all areasofthewaferotherthanthe bopper bonding pads 24 by conventional photolithographic masking techniques.
Alternatively, the palladium layer could be applied by sputtering or evaporation to the structure in Figure 3. The excess palladium would then be removed during the subsequent etching operation described in connection with Figures 4-6.
In either case, the palladium will be applied to a final thickness in the range from 80to 300 A, more usually in the rangefrom about 100 to 200 A. It has beenfoundthatthepalladium layers below about 80 A often display discontinuities in the coverage of the copper, and are therefore less effective in inhibiting oxidation. In contrast, palladium layers having a thickness above about 300 A are very brittle and tend to crack during the thermocompression bonding of the copper bonding tape. The palladium layer 30 will normally be applied by sputter deposition, although electroless plating may also find use.
Referring now to Figures, a second embodiment of the present invention is illustrated. A copper bump 32 is formed directly on top of the copper layer 24. The copper bump 32 is formed by conventional techniques, and will typically project about 0.001 inch above the surface ofthe semiconductor device.
A palladium layer 34 is then applied over the copper bump by either of the techniques described in connection with Figure 7. As illustrated in Figure 8, the palladium layer 34, would have been applied to the structure of Figure 3, and subsequently etched with layers 20,22, and 24, as the vertical surfaces of the palladium have been removed.
Afterthe deposition of the pailadium layer 30 or 34 the semiconductor devices are generally ready for the formation of inner lead bonds with the copper bonding tape by conventional techniques.
Although the foregoing invention has been described in some detail byway of illustration and example for purposes of clarity of understanding, it will be obviousthat certain changes and modifications may be practiced within the scope of the appended claims.

Claims (17)

1. A semiconductor device having at least one copper bonding pad structure, wherein said copper bonding pad is covered by a layer of palladium to inhibit oxidation ofthe underlying copper.
2. 2. A semiconductor device according to claim 1, wherein the layer of palladium has a thickness in the range from about 80 to 300 Angstroms.
3. A semiconductor device having at least one metallization pad structure comprising an aluminium metallization pad, an aluminium layer deposited directly overthe aluminium metallization pad, a nickel layer deposited directly over the aluminium layer to form a stable aluminium-nickel alloyatthe interface, a copper layer deposited over the nickel layerto allow bonding to copperbonding tape, and a palladium layer deposited overthe copper layerto inhibit oxidation of the underlying copper.
4. Asemiconductordevice according to claim 3, wherein the aluminium layer has a thickness in the range from about 2,000 Angstroms to 6,000 Angstroms.
5. A semiconductor device according to claim 3 orclaim 4, wherein the nickel layer has a thickness in the range from about 2,000 Angstroms to 5,000 Angstroms.
6. A semiconductor device according to any of claims3to5,whereinthecopperlayerhasa thickness in the rangefrom about 4,000 Angstroms to 15,000 Angstroms.
7. Asemiconductordevice according to any of claims 3 to 6, wherein the palladium layer has a thickness in the range from about 80 to 300 Angstroms.
8. A semiconductor device according to any foregoing claim, wherein the copper layer is bumped.
9. A semiconductor device according to any foregoing claim, wherein the copper layer is not bumped.
10. A method of forming a copper bonding structure on an aluminium metallization pad, said structure being capable of bonding to coppertape, said method comprising: applying an aluminium layerdirectlyoverthe aluminium metallization pad; applying a nickel layer directly overthe aluminium layer; applying a copper layer directly over the nickel layer; and applying a palladium layer over the copper layerto inhibit oxidation of the copper.
11. A method according to claim 10, wherein the aluminium layer is applied to a thickness in the range from about 2,000 Angstroms to 6,000 Angstroms.
12. A method according to claim 10 orclaim 11, wherein the nickel layer is applied to a thickness in the rangefrom about 2,000 Angstroms to 5,000 Angstroms.
13. A method according to any of claims 10 to 12, wherein the copper layer is applied to a thickness in the range from about 4,000 Angstroms to 15,000 Angstroms.
14. A method according to any of claims 10to 13, further comprising applying a copper bump overthe copper layer before the palladium has been deposited.
15. A method of forming a copper bonding structure on a semiconductordevicefor thermocompression bonding to copper tape, said method being characterised by applying a layer of palladium overthe copper bonding structureto inhibit oxidation of the copper.
16. A method according to any of claims 10 to 15, wherein the palladium layer is applied to a thickness in the range from 80 to 300 Angstroms.
17. A method according to any of claims 10 to 16, whereinthe palladium layer is applied bysputter deposition orelectroless plating.
GB08614593A 1985-12-16 1986-06-16 Oxidation inhibition of copper bonding pads using palladium Withdrawn GB2184288A (en)

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US80944385A 1985-12-16 1985-12-16

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GB2184288A true GB2184288A (en) 1987-06-17

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DE (1) DE3640248A1 (en)
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Publication number Priority date Publication date Assignee Title
EP0308971A3 (en) * 1987-09-24 1990-10-10 Kabushiki Kaisha Toshiba Bump and method of manufacturing the same
EP0426246A1 (en) * 1989-11-01 1991-05-08 Koninklijke Philips Electronics N.V. Interconnection structure
EP0589678A3 (en) * 1992-09-23 1995-04-12 Dow Corning Hermetic protection for integrated circuits.
EP0966045A1 (en) * 1997-06-11 1999-12-22 Micronas Intermetall GmbH Method of fabricating a semiconductor device having a structured metallisation
WO2001001478A1 (en) * 1999-06-28 2001-01-04 Unaxis Balzers Aktiengellschaft Component and method for the production thereof
WO2001008213A1 (en) * 1999-07-27 2001-02-01 International Business Machines Corporation REDUCED ELECTROMIGRATION AND STRESS INDUCED MIGRATION OF Cu WIRES BY SURFACE COATING
US6218732B1 (en) * 1998-09-15 2001-04-17 Texas Instruments Incorporated Copper bond pad process
WO2001035462A1 (en) * 1999-11-05 2001-05-17 Atmel Corporation Metal redistribution layer having solderable pads and wire bondable pads
GB2360295A (en) * 2000-03-15 2001-09-19 Ford Global Tech Inc Palladium and palladium/copper membranes for use in fuel cells
EP1139413A3 (en) * 2000-03-24 2002-06-12 Texas Instruments Incorporated Wire bonding process
US6423642B1 (en) 1998-03-13 2002-07-23 Semitool, Inc. Reactor for processing a semiconductor wafer
US7026721B2 (en) * 1999-11-18 2006-04-11 Taiwan Semiconductor Manufacturing Company, Ltd. Method of improving copper pad adhesion
US7176576B2 (en) 2000-03-03 2007-02-13 Micron Technology, Inc. Conductive connection forming methods, oxidation reducing methods, and integrated circuits formed thereby
US7217325B2 (en) 1999-01-22 2007-05-15 Semitool, Inc. System for processing a workpiece
WO2008078268A1 (en) * 2006-12-27 2008-07-03 Nxp B.V. Semiconductor component with inertly encapsulated metal surface layers
US7399713B2 (en) 1998-03-13 2008-07-15 Semitool, Inc. Selective treatment of microelectric workpiece surfaces
US8354692B2 (en) 2006-03-15 2013-01-15 Infineon Technologies Ag Vertical semiconductor power switch, electronic component and methods of producing the same

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US6759597B1 (en) 1998-02-02 2004-07-06 International Business Machines Corporation Wire bonding to dual metal covered pad surfaces
JP3165129B2 (en) * 1999-02-26 2001-05-14 日本発条株式会社 Thermoelectric conversion module block for thermoelectric generation
JP2012069691A (en) * 2010-09-22 2012-04-05 Toshiba Corp Semiconductor device and method of manufacturing the same

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Cited By (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0308971A3 (en) * 1987-09-24 1990-10-10 Kabushiki Kaisha Toshiba Bump and method of manufacturing the same
EP0426246A1 (en) * 1989-11-01 1991-05-08 Koninklijke Philips Electronics N.V. Interconnection structure
EP0589678A3 (en) * 1992-09-23 1995-04-12 Dow Corning Hermetic protection for integrated circuits.
US5825078A (en) * 1992-09-23 1998-10-20 Dow Corning Corporation Hermetic protection for integrated circuits
EP0966045A1 (en) * 1997-06-11 1999-12-22 Micronas Intermetall GmbH Method of fabricating a semiconductor device having a structured metallisation
US6423642B1 (en) 1998-03-13 2002-07-23 Semitool, Inc. Reactor for processing a semiconductor wafer
US7399713B2 (en) 1998-03-13 2008-07-15 Semitool, Inc. Selective treatment of microelectric workpiece surfaces
US6218732B1 (en) * 1998-09-15 2001-04-17 Texas Instruments Incorporated Copper bond pad process
US7217325B2 (en) 1999-01-22 2007-05-15 Semitool, Inc. System for processing a workpiece
WO2001001478A1 (en) * 1999-06-28 2001-01-04 Unaxis Balzers Aktiengellschaft Component and method for the production thereof
WO2001008213A1 (en) * 1999-07-27 2001-02-01 International Business Machines Corporation REDUCED ELECTROMIGRATION AND STRESS INDUCED MIGRATION OF Cu WIRES BY SURFACE COATING
US6342733B1 (en) 1999-07-27 2002-01-29 International Business Machines Corporation Reduced electromigration and stressed induced migration of Cu wires by surface coating
US7468320B2 (en) 1999-07-27 2008-12-23 International Business Machines Corporation Reduced electromigration and stressed induced migration of copper wires by surface coating
US6577008B2 (en) 1999-11-05 2003-06-10 Atmel Corporation Metal redistribution layer having solderable pads and wire bondable pads
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JPS62145758A (en) 1987-06-29
FR2591802A1 (en) 1987-06-19
DE3640248A1 (en) 1987-06-19
GB8614593D0 (en) 1986-07-23

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