GB2185164A - Photovoltaic relay with past switching circuit - Google Patents

Abstract

The gate capacitance of a Field effect transistor (24) used as a switch is rapidly charged via a diode (35) to turn the FET on, and is rapidly discharged to turn the FET off by a switching transistor (36) connected across the diode and the FET such that it becomes conductive only when the diode becomes reverse biased, thereby providing a discharge path for the gate capacitance. The circuit is used in a photovoltaic relay, the FET being turned on by a photovoltaic isolator (20) having a LED 21 energised by an input signal optically coupled to and dielectrically isolated from a series-connected stack of photo diodes connected to the switching FET, which may comprise a bilateral semiconductor FET (BOSFET). <IMAGE>

Description

GB 2 185 164 A 1

SPECIFICATION

Photovoltaic relay This invention relates to solid state relays.

Reed relays are well known electromechanica I relays in widespread use. Such relays have a limited lifetime,for example, of the order of about one million operations and are relatively large and expens- 10 ive. Efforts have been made to replace reed relays by relays employing solid state components. These efforts to date, however, have not produced a unit which is generally competitive, in terms of characteristics or economics, with a reed relaytype de- 15 vice.

Thus, commercially available solid state relays almost universally use thyristors (SCRs ortriacs) as output devices. Thyristors, however, are poor analogs of an ideal electromechanical switch. For ex- 20 ample, thristors have a minimum 0.6 volt on-state voltage drop, must have polarity reversal to turn them off, require a one-half cycle turn- off time, and have high holding currents and high reverse leakage currents. Thus, thyristor devices are generally un- 25 satisfactoryfor applications such as general purpose instrument switching which continues to rely on reed switches. The use of anti- parallel connected thyristors is also disclosed in Patent 4,296,331.

Solid state relays employing a MOSIFET rather 30 than thyristor form an excellent solid state analog of the ideal conduction/blocking characteristics of a pair of mechanical contacts. Bidirectional conduction MOSFETs can control either a-c or d-c circuits, therebyforming a truly universal contact.

35 Relays are also known wherein the input energy for switching the transistor is derived f rom a photo voltaic generatorwhich can be illuminated by a suit able LED or other radiation source in order to pro duce an output current which causes the switching 40 of the device. Such a relay is shown in United States Patent No. 4,227,098.

When the main power switching device is a power MOSFET, the input current from the photovoltaic source must charge the gate capacitance of the de 45 vice sufficiently in order to turn the device on. When using photovoltaic generators, commonly a stack of solar cell-type devices, such generators must op erate into a high impedance to preventthe diversion of the cell output current away from the MOSFET gate capacitance. The need fora high impedance de lays the discharge of the gate capacitance when the input radiation signal to the photo-generatoris turned off and the photo-generator output voltage collapses. Thus, in the circuit of Patent 4,227,098, the 55 main power MOSFET remains on afterthe input signal terminates for the length of time necessaryto discharge the gate capacitance of the power MOSFET into a high impedance circuit. The circuit of Patent 4,227,098 is also sensitive to false firing due to 60 high dV/dt across the power MOSFETterminals since the high dV/dt will charge the drain-to-gate capacitance of the power MOSFET and turn on the relay without an input signal.

Circuits are known to caose more rapid discharge 65 of this gate capacitance for highspeed turn-off. Such 130 circuits, however, employ a second photovoltaic source, as is shown in United States Letters Patent No. 4,390,790. The second photovoltaic source or array is used to sense the presence or absence of an 70 input signal and turns on a depletion mode MOSFET when the input illumination is turned off with the turn-off of the input signal. The MOSIFIET gate capacitance can then discharge more quickly th rough the conducting depletion mode MOSFETfor higher 75 relay turn-off speed.

A photovoltaic isolator may serve as a voltage source which can turn on a power switching device such as a power metal oxide semiconductor field effecttransistor (MOSFET), as shown, for example, in

80 United States Patent 4,227,098, dated October7, 1980. The photovoltaic generatorwhich is used in such photovoltaic isolators must have a relatively high output so that immediately upon the energization of the LED, a sufficiently high outputwill be pro- 85 duced from the photovoltaic stackto providethe gate power needed to drivethe gates of control devices such as MOSFETs or bipolar transistors, orthe like.

Photovoltaic generators are known which consist of a dielectrically isolated group o f photovoltaic generators spaced overthe surface ofa dielectric support and electrically connected in series with one another. A photovoltaic generator of this type is shown in above-mentioned Patent 4,227,P98. Such devices are commercially available. Diele'trically isolated, laterally spaced and series-connected photogenerator cells have the disadvantage thbt only a small volume, which may be only about 1 mil deep, can be used for collection of generated minority carriers 100 and low lifetime material is used. Also, the electrode system for connecting the devices in series blocks incident light. Consequently, the output current of such devices is limited. Moreover, the devices employ a relatively complex structure and are expens- 105 iveto manufacture.

Photovoltaic generators have also been made of a stack of seriesconnected wafer elements which each have PN junctions therein arranged in the sameforward conduction direction. These devices can be cut 110 into small slabs which can be edge illuminated to produce an output voltage acrossterminals connected atthe two ends of the stack. A device of thistype is shown in U.S. Patent 3,422,527, issued January 21, 1969 to J.M. Gault and assigned to the assignee of the present application.

An edge illuminated stack of cells is inherently superiorto dielectric isolated cells since light can go as deep as desired into the slab and the carriers produced will still be collected even if they are formed, for 120 example 5 mils from the collecting junction. Moreover, with edge illuminated slabs, the electrical contacts between adjacent units are out of the light path.

In prior art edge illuminated arrangements used as photovoltaic generators, the output current power is

125 limited. Thus, such devices hae not been efficient enough to rapidly charge a MOSFET gate capacitance to reach a turn-on threshold voltage in a very short time. Commonly, the individual wafers of such devices employ an N type body with a shallow Ptype diffusion to form the collection junction. Also, re- 2 GB 2 185 164 A latively thick wafers have been used so thatthe final stack has a very large heightwhich isdifficultto illuminate evenly bya single LEDlocated atthecenter of the stack.

According to the present invention, there is provided a photovoltaically operated solid state relay circuitcomprising:

a photovoltaic isolator circuit comprised of an LED means having input energizing terminals, and a 10 photovoltaic pile which is optically coupled to said LED means and is dielectrically isolated therefrom; said photovoltaic having positive and negative outputterminals which have a voltage produced therebetween in response to illumination by said 15 LED means; characterized in containing a bidirectional output serniconductorfield effect transistor means having firstand second output powerterminals, a gate terminal and a substrate terminal; a resistor connected across said positive and negative output terminals; a diode having an anode connected tothe positive terminal of said photovoltaic pile and a cathode connected to said gate terminal; and a high gain transistor; said high gain transistor having a base connected to said anode of said diode, an emitter connected to said cathode of said diode and a collector connected to said substrate terminal; whereby, the generation of an outputfrom said 30 photovoltaic pile produces sufficient powerto turn on said field effect transistor means at high speed and, whereby, when the voltage output of said pile drops below a given value, said high gain transistor turns on to reduce the relaycircuit input impedance.

General aspects of the present invention will now be described without limiting the scope of the invention.

In accordance with one embodiment of the present invention, a novel high voltage bidirectional output 40 switch field effect transistor (BOSFET) structure is provided which employstwo laterally integrated field effect transistors having a common central source region. The device is preferably operated by the output of an opto-coupler or photovoltaic isola- tor circuit. Two outer drain regions of the device are connected to a central source region through respective enhancementtype channel regions which can be inverted to connected the two outer spaced drainsto one another through a relatively low resist- 50 ance conduction path between the two drain electrodes. For example, a resistance path lowerthan about 2 ohms can be formed. This resistance is generally compatible with most applications using reed relays.

The novel junction configuration employs reduced 55 surface fields of novel configuration. Thus, with the invention, two channel regions are preferably symmetrically disposed between two depletion regions. A common source connection communicates between the separated drain regions. The channel re-

60 gions are P regions disposed within an implanted N (-) region each formed atop a P(-) body. Control circuit components are integrated into the BOSFET chip. In one embodiment, a diode and a PNPtransistor are formed in the N(-) layer, where the diode is formed in a P type well while the PNP transistor em- ploys the N(-) region as its base region. Thetwo main drain regions are isolated from each other and the N (-)region for the PNP transistor and diode by a deep P+ isolation diffusion.

The voltage between the drain reglonswhen the device is off can be of the order of 1 00to 1,000volts to make the relay compatiblewith general reed relay application. This relatively high voltage is possible since the high outputvoltage is blocked across the 75 lateral N(-) drift region and never across the gate oxide, whetherthe relay is controlling a-c or is d-c voltage. Consequently, even though the device output voltage is high, an extremelythin gate oxide can be used to make the gate very sensitive, and so 80 thatthe device can be turned on by relatively low inputvoltages with a relatively low currentsource. As a result, the device can be turned on by the output of an optocoupler or photovoltaic initiator of the type later disclosed. Thus, the semiconductor switching 85 device, or BOSFET, is a high voltage, relatively low on resistance device, which has an extremely sensitive gate turn-on characteristic.

Note thatthe device of the invention can be used in any general application and could, for example, 90 serve as a direct replacement for existing thyristors ortriacs. The device is also applicable for use asthe power switching component of a solid state relay which hasthe other relay components integrated into the same chip with the power switching element.

A novel solid state relay circuit is also described which permits the use of a single photovoltaic initiator outputfor driving the BOSFET into conduction with the circuit having relatively high inputturn-on 100 impledance, to I imit the requirements of the size of the photovoltaic initiator structure, and a low input turn-off impedanceto provide high speedturn-off time.

The novel circuit insures thatthe gate voltage al- 105 ways instantaneously follows a single photovoltaic generator output. There aretwo conditionswhich tend to makethe power MOSFET gate voltage deviated from the intended photovoltaic generator output. These arethe charge stored on the gateto 110 source capacitance Ciss and the currentwhich can flowunder high dWdtthrough the drain-to-gate capacitance CD-G.which falsely chargesthe gate. It has been recognized thatwhen the power MOSFETgate is connected directlyto the photovoltaic generator, it 115 is impossible to distinguish whether agate signal is properly present from an output of the photogenerator oras a result of the charging of one of the parasitic capacitances Ciss or CD-G- In accordance with one beneficial arrangement, a 120 sensing impedance is connected between the photogenerator and power MOSFET gate which can be used to control auxiliary circuitsto quickly eliminate false MOSFET gate voltages. In a preferred arrangementthe sensing impedance is a diode, although 125 other components such as a zenerdlode, MOSFET, or resistor could be used. By using a separate sensing impedance, it becomes possibleto control the auxiliary circuits without the need fora second phot9generator array or pileto enable rapid dis- 130 charge of the capacitance Ciss When the input signal GB 2 1P5 164 A 3 1 50 is turned off.

Ina preferred arrangement, the charging circuit from the photovoltaic source output to the gate-to source circuit of the power MOSFET has a diode con 5 nected therein which permits current flow from the photovoltaic sources into the gate capacitance and serves as the sensing impedance. A switching trans istor circuit is connected in parallel with the gate cap acitance Clss of the power MOSFET device and is 10 controlled from an input control terminal connected to the positive output terminal of the photovoltaic source, so thatthe switching transistor is biased on when the photovoltaic source output voltage begins to collapse. Consequently, the relaywill switch on as 15 soon as suff icient current is generated from the photovoltaic source to charge the gate capacitance of the power MOSFETto the necessaryvalue. When, however, the circuit is to be turned off, and when the outputvoltage of the photovoltaic source reduces 20 below a given value, the switching transistorturns on to place a short circuit across both the gate cap acitance of the power MOSFET and across the photo voltaic source, so that both the gate capacitance Ciss and the ouptut of the photovoltaic source is short 25 circuited bythe switching transistor. Therefore, the power MOSFET rapidlyturns off.

A novel dynamic a-c clamping circuit is also descri bed which includes a further switching transistor connected across the gate-to-source electrodes of 30 the power MOSFET. A resistance-capacitance dif ferentiating circuit may be provided and connected forturning on the second switching transistorto by passthe Miller currentthrough the gate-to-drain par asitic capacitance CD-G of the power MOSFETwhen the dV/dt exceeds a given value. Notethatthis a-c circuit is connected between the sensing impedance referred to above and the power MCSFETgate elec trode.

Notethatthe novel solid state control circuitwhich 40 is disclosed as integrated into a single chip with the 105 BOSFETcan also be used to drive conventional FET devices.

The novel solid state relay described herein has many advantages over existing relays in the market, 45 including the electromechanical reed relay. Thus, the novel circuit described herein can switch either a-c or d-c voltages and has extremely small leakage current when in the off state, which is characteristic of MOSFETtype devices. It also has extremely low thermal offsetvoltage and generates no electro magnetic interference radiation when closed. It is also perfectly resistive in the on state, having no min imum holding current or outputvoltage. It can thus accurately transmit analog signals. Moreover, it re 55 quires as little as 1-2 milliwatts of input powerto re main in the "on" state. Furthermore, the device can turn on and off within a few microseconds, as contra sted on the milliseconds required to operate a reed relay or a conventional solid state relay. The load 60 current capacity of the device is limited only by chip size and junction geometry and can be of the order of 500 to 1,000 milliamperes to satisfythe load current ratings of conventional reed relays. It also has ex tremely long operating lh, in excess of a trillion op erations, The overall device can be housed in any de- sired kind of package, for example a 16 pin DIP housing similar to that now used by reed relays and other conventional solid state relays.

A novel photovoltaic stack is also described which 70 has an exceptionally high output voltage and current while employing relative few wafers in the stackto make a relatively short height stac. In accordance with one preferred arrangement, q high resistivity P type body is used. Athin N +layer pn the bodythen 75 forms the collection junction in the body. By using a Ptype body having a thin N+ layerto form the collection junction, minority carriers in the Ptype body are electrons. Such carriers have a higher mobilitythan holes which arethe minority carriers in the conventional N type body.

Preferably,the body material has a high lifetime and a resistivity greaterthan about 5 ohm centimeters,for example, 30 to 50 ohm centimeter material formed from floatzone drawn crystal ingots.

85 However, lower resistivity material of 1 to 5 ohm centimeter material which has been used in conventional P type solar cells can also be used. Use of a lower resistivity material was known to produce a higher output voltage but, in the applications of 90 arrangements described herein, it is possible to reduce outputvoltage in favor of the higher short circuit current obtained by using higher resistivity materials.

In a further aspect of the described arrangement, 95 the individual semiconductor wafers are as thin as possible consistent with their being handled without excessive breakage. The novel process described herein makes the use of such verythin wafers possible since wafer grinding, which applies stress to 100 the stack, maybe the last process step before alloying. In fact, the wafers are mode thinnerthan the diffusion length of carriers which are produced in the wafer. This can be done since a novel P+ layer is spaced atop the P(-) bodyto serve as a reflecting layer which reflects minority carriers already collected by the PN junction.

As anotherfeature of the described arrangements, an N+ layer of extremely high conductivity is employed on one side of the P(-) body. The use of a 110 very heavily doped N + layer permits the use of an aluminum of aluminum silicon eutecticfoil for alloying the stacktogether without converting the N + layertq a Ptype region. The N+ diffusion is preferably carried outwith a phosphorus impurity, The 115 phosphorus will act as a getterfor metal ions within the wafer and thus further increases the lifetime of the material.

The reflection P+ layer previously described, as well asthe N+ layer, are preferably formed bywell 120 controlled diffusion processeswhich are well known such asthose employing predepositions with POC13 and BN.

As pointed out above,the stack is connected together bythe alloying of a thin aluminum or 125 aluminum eutecticfoil between adjacentsemiconductor wafers. If desired, however, a metal impregnated epoxyof polyamide can be used to connecttogetherthe stack. ThiswoLlId permitthe use of shallower junctions and thus an even shorter height 130 stack.

4 GB 2 185 164 A End plates which maybe of monocrystal line sil icon wafers are also used for the stackto provide a sufficiently long "stand-off" distance to contain saw damage, without damaging a junction and to allow 5 use of conductive epoxy to secure the stack ends to spaced leads without danger of shorting out a jun ction of an active wafer.

When wafers are processed as described above, their individual outputs are sufficiently high that a 10 stack of less than abouttwenty devices, and prefer ably only aboutten devices is needed to produce a suitable output current and voltage suff iciently high to rapidlyturn on a power MOSFET.

The invention will be further described by way of 15 example only and with referenceto the accompany- 80 ing drawings, in which:

Figure 1 is a circuit diagram of a first embodiment of the novel circuit which may be integrated into a single chip, 20 Figure2 showsthe equivalent circuit diagram of the novel bidirectional output serniconductorfield effect transistor shown in Figure 1, Figure 3 shows the characteristic output voltage as a function of time forthe photovoltaic isolator circuit 25 portion of Figure 1, Figure 4shows the currenttransfer characteristic of the relay circuit of Figure 1, Figure 5 is a plan view of a single chip containing the output circuit of Figure land in particular shows the drain and source metallizing patterns, Figure 6is an enlarged viewof the wafersurface and of thejunctions emerging thereon in the circled region A of Figure 5, Figure 7is an enlarged view of thejunction pattern 35 in the dotted enclosed region B of Figure 5 and shows the PNPtransistor and diodejunction of the circuit of Figure 1 integrated into the chip surface, Figure8is a cross-sectional view of Figure 6taken across the section line 8-8 in Figures 5 and 6and showsthe basicjunction pattern used forthe 105 BOSFETdevice, Figure 8a schematically illustrates the manner in which the gate oxide isterminated shortof the area of curvature of the polysilicon gate, Figure9 is a cross-sectional viewtaken acrossthe section line 9-9 in Figure 7 and shows the junction pattern forthe transistor and diode of Figure 1, Figure 10 is a top viewof a portion of the periphery of the chip of Figure 1 and illustrates the inputresis- tor, Figure 11 is a cross-sectional view of Figure 10, taken acrossthe section line 11-11 in Figure 10, Figure 12 is a plan view of a second embodiment of a BOSFET, 55 Figure 13 is a cross-sectional diagram of Figure 12 taken across section line 13-13 in Figure 12, Figure 14 is a second embodiment of a circuit which can be integrated into the chip of Figures 5,6, 8,12 and 13, 60 Figure 15is a top view of a singlewaferof mono crystalline silicone which is employed fora photo generating stack, Figure 16is a cross-secfional viewof Figure 1 taken acrossthe section line 16-16 in Figure 15, 65 Figure 17showsthewafer of Figure 16 afteroxidiz-130 ing its surface and afterthe formation of a photoresist mask on one surface, Figure 18shows the wafer of Figure 17 afterthe removal of the oxide layerfrom one surface of the 70 wafer, Figure 19 shows the wafer of Figure 18 after a P type diffusion into the unmasked surface of Figure 18, Figure20 shows the wafer of Figure 19 after a photoresist mask is applied to one, su rface and the oxide layers removed from the otler surface, Figure 21 shows the wafer of Figure 20 afterthe formation of a very high concentration N + region into the exposed surface of the wafer of Figure 20, Figure 22 shows the wafer of Figure 20 after al I oxide is stripped from the wafer, Figure 23 shows a stack of wafers, each identical to that of Figu re 22, with interposed aluminum eutectic foils and aluminum contacts on the opposite ends of the stack, Figure24 shows a single prior art slab orstack having the shape of a parallelepiped which has been cut fromthestackof Figure 23 after the stack has been alloyed together, Figure25is atop view of the photovoltaic isolator of Figure 24 contained in a plastic housing.

Figure 26 is a cross-sectional view of Figure25 taken across the section line26-26in Figure25,and Figure 27 is a cross-sectional view of the stack of 95 Figure 24, and shows the extent of saw damage after dicing.

Referring firstto Figure 1, there is shown therein oneembodimentof a circuit which can beemployed to produce a solid state relay employing a BOSFET 100 and control circuit. A photoisolator oroptocoupler is shown in an enclosed doffed line 20 in Figure 1.

Photovoltaic isolator20 consists of an LED 21 connected to relay inputterminals 22 and 23 and a stack of photovoltaic diodes l9which produce an output currentwhen illuminated by LED 21. LED 21 or modifications thereof can be excited by either an a-c ord-c inputto terminals 22 or23. In the embodiment shown, a d-c input sourcewill be connected tothe terminals 22 and 23 in orderto turn the LED 21 onand 110 off. Byway of example, the input circuit can be arran ged to apply about 10 milliamperes to the LED 21 in orderto excite the LED.

The remainder of the circuit of Figure 1 includes solid state relay components for turning on and off 115 the novel BCSFET 24 which has output terminals 25 and 26. The output terminals 25 and 26 can be connected in either an a-c or d-c circuit since device 24 has bidirectional conduction characteristics, although the device is a high voltage device. Thus, 120 the BOSFET device 24 is equivalentto the circuit shown in Figure 2 of two series-connected vertical conduction high voltage MOSFETs 30 and 31 which are shown connected between terminals 25 and 26. Conventional MOSFETs 30 and 31 are turned on and 125 off by a gate to substrate control voltage which is applied between terminals 32 and 33. The structure and process for manufacture of the BOSFET24will be later described in detail.

The control components of Figure 1 forthe BOSFET24 include diode 35, a PNPtransistor 36 and Z' 1 50 GB 2 185 164 A 5 an input resistor37. Resistor37 hasavery high impedance and can typically be a 5 megohm resistor.

The characteristics of the solid state circuit of Figure 1 when implemented as later described are 5 similarto those of conventional solid state relays and reed relays which are now in common use. Byway of example, the circuit characteristics may be such that the circuit can withstand 400 volts peak between terminals 25 and 26 at a maximum load current of about 10 200 milliamperes. The on resistance between terminals 25 and 26 is about 25 ohms maximum. The device input capacitance is about 60 to 80 picofarads and the device output capacitance is about40 picofarads. The capacitance between the input and 15 output circuits is about 2 picofarads. The turn-on time of the circuit with a 5 megohm resistor 37 is approximately 50 microseconds with 10 milliamps drive and its turn-off time is about 90 microseconds. Pickup sensitivity can be increased by increasing the 20 input impedance 37 and the input impedance 37 can also be decreased to increase turn-off speed.

The characteristic of the photovoltaic isolator 20 is shown in Fig ure3 on an exaggeragted scale. Thus, as shown in Figure 3, in a bout4 microseconds fol- 25 lowing the instant that LED 21 turns on, the output voltage of stack 19 rises to approximately 3 volts, when employing an input impedance of about 5 megohms. The drive for the LED in producing the characteristic of Fig ure3 is about 10 milliamperes.

30 The on time will be shortened by employing a higher input impedance 37 or increasing the LED drive. The outputvoltage of stack 19 will immediately begin to decay with the turn off of the LED 21. This decay would ordinarily take a relatively long time, as 35 shown in dotted lines in Figpre 3, since the gate capacitance of BOSFET24 sloWly discharges in prior art circuits which do not empidythe novel diode 35 and PNP transistor 36 will begin to conductwhen the output voltage of the stack 19 drops about 0.6volt

40 less than the MOSFET gate voltage. The input imped- 105 ance of the circuit is then reduced by the gain of the transistor 36. Thus, as shown in Figure 3, the stack voltage and gate voltage of BOSFET 24 rapidly col lapses to obtain relatively high speed turn-off even 45 though a high input impedance 37 is used for rapid turn-on.

Note that the diode 35 forms a low impedance charging path to the gate circuit of BOSFET 24to enable high speed turn-on of the device with the full input impedance of resistor 37 in place. Diode 35 is in fact a sensing impedance which could be replaced by other impedances.

The circuit of Figure 1 operates as follows:

In orderto turn on the relay, LED 21 is excited and a 55 charging current flows from the stack 19. This charging current flows through diode 35 to charge the gate capacitance of BOSFET 24. When thethreshold voltage of the BOSFET gate capacitance 24 is exceeded (about 1.0 volt), the novel BOSFETturns on and 60 goes full-on at about 2 to 2.5 volts. A conduction path is then established between terminals 25 and 26. Because of the low current and voltage requirements forthe BOSFET 24, a relatiyely small photoisolator stack 19 can turn on the BOSFET 24.

65 Note thatvery rapid response is obtained from the photovoltaic stack 19 since its current feeds into the high input impedance circuit defined by resistor 37. Under ordinary circumstances, this same high input impedancedefeats rapid turn-off of the device since, 70 in orderto turn off the BOSFET, it is necessaryto discharge the gate capacitance through the same impedance. In accordance with the invention, however, the very high performance PNP transistor 36, which has the high gain characteristics, for example, of a 75 static induction transistor (SIT) produces a 20:1 improvement in turn- on speed. As will be later seen, the use of a PNP transistor is compatiable with the construction of the BOSFET device24. Note particularly that the transistor 36 is not used to clamp the 80 photovoltaic isolator 20 butfollows its outputvoltage. Oncethe outputvoltage of the stack 19 dropsto aboutO.6volt belowthe gate voltage, transistor 36 turns on. Theffective input impedance of the circuit is then the resistance of resistor37 divided bythe 85 beta of transistor36 which is about400. Consequently, the effective inputcircuit becomes a relatively low impedance circuitwhich can relatively quickly dischargethe gate capacitance of the BOSFET24to relatively quicklyturn if off.

The current transfer characteristics of the circuitof Figure 1 is shown in Figure4. In Figure 4, when the gate voltage, which isthevoltage of the positive outputterminal of stack 19 minustheforward drop of diode 35, reaches about 1 volt,the BOSFET24 be- 95 ginsto turn on. Once approximately 2 volt is reached,the device is almostfull on and the load current reached atthattime might,for example, be 100 milliamperes. The actual voltage needed to switch BOSFET 24 from a blocking condit" ntoafullyon 1% 100 condition is less than about 3 volt sothatthedevice is operable with TTL circuits.

Figures 5-11 showthe novel BOSFET24in a single chip of silicon along with diode 35, transistor 36 and resistor 37. In one arrangement, and for the ratings which were previously stated forthe overall relay, the chip has a thickness of about 15 mils and a length and width of 71 and 92 mils, respectively. Obviously, other sizes can be used.

The surface of the chip is shown in plan viewin 110 Figure 5which particularly showsthe metallizing pattern forthe source and drain electrodes of the BOSFETdevice 24. Obviously,the single chip shown in Figure 5 will be one of a large number of chips which are simultaneously produced on a relatively 115 largeareawafer.

Referring to Figures 5,6 and 8, the BOSFET device 24 consists of two main drain electrodes 50 and 51, respectively, shown with cross-hatching for convenience. Enlarged pad regions 52 and 53 are employed 120 to make electrical contactto the drains 50 and 51 by conventional wire bonding techniques.

Drains 50 and 51 will ultimately be connected to the terminals 25 and 26 of Figure 1 and each consists of a plurality of spaced elongated fingers, such as 125 drain fingers 54 and 55 which are shown in enlarged detail in Figure 8. Note thatthe arrangement of Figure 5 is exaggerated in detail and in actual device, approximately fifteen fingers will be used for each drain region.

130 A plurality of elongated source contacts, including 6 GB 2 185 164 A source contacts 56 and 57 are disposed laterally across the chip and are disposed symmetrically between spaced pairs of extending drain fingers. The individual source fingers are electrically connected to one another by a frame containing vertical central conductor 65 and surrounding border 66. Consequently, a current path will be defined, for example, from drain 50 to drain 51 and extends from parallel connected fingers 54 and 55, into the source finger 10 56, and then to the right along source finger 56 to the drain fingers 58 and 59. All drain and source metals may be aluminum. The bottom surface of the chip can have an electrode secured thereto which is connected to the source border 66. Asubstrate connec- tion pad 60 is provided on the surface of the device of Figure 5.

The novel interdigitation type pattern described above uniquely enables the use of a high voltage between the drains 50 and 51 without imposing a high voltage across the gate oxides which control the above current conduction path, as will be later described. Note that parallel conduction paths existfor each of the adjacent pairs of drain electrodes and source electrodes shown in Figure5.Also provided on the surface of the device of Figure 5 is a gate pad 61 which enables an easy bonded connection to the gate circuit of the device, as will also be later described. Note furtherthatthe substrate pad 60 of Figure 5 corresponds to the substrate terminal of BOSFET24 30 in Figure 1 which is connected to the negative output terminal of stack 19 while the gate pad 61 corresponds to the anode of diode 35 which is connected to the positive outputterminal of stack 19.

As also shown in Figure 5, a region of the chip area 35 shown within the dotted line area B, and which will be laterdescribed, is reserved forthe formation of diode 35 and transistor 36, as is schematically illustrated. The surface of thechipwill also carrytheresistor37around its outer periphery in a mannerto be 40 later described but not shown in Figure 5.

The junction pattern which is used forthe novel arrangement is shown in Figures 6 and 8 in connection with thejunction pattern of typical area Aof Figure 5. Notethat this pattern will be employed over 45 the full surface of the device of Figure 5.

Referring nowto Figures 6 and 8, the body of the chip 70 is a lightly doped P(-) region which, as previously stated, has a thickness of about 15 mils and can, for example, have a resistivity of 30 ohm cent- 50!meters. The main P(-) region is not in series with the main current path of the device but itcletermines the breakdown voltage of the BOSFET. A lightly doped N type drift region 71 is then formed in the upper surface of the P(-) body region. The N(-) re- 55 gion 71, sometimes termed a depletion region of drift region, preferably has a depth of about 5 microns and may be formed by conventional epitaxial growth techniques. Preferably, however, layer 71 is novellyformed by ion implanation. The N(-) drift re60 gion 71 must be correctly doped in orderto obtain correct depletion in a lateral direction during operation of the device so thatthe field atthe device surface will be equally distributed overthe surface. Preferablythe N(-) region 71 is formed by a phosphorus

65 implanation, with a dose of about 1 X 1012 ions per cm 2. A subsequent drive for about 18 hours at about 1,200'C. follows the implanation in orderto diffuse the phosphorus ions to the depth of about 5 microns, as previously described.

A P+ region 72 which includes strips underlying each of the source strips of Figure 5 is then formed. The lateral sides of the strips such as strip 72 are preferably more lightly doped than thq laterally interior section sincethese regionswill define the channels 75 of the MOSFET device to be formed as will be later described.

In forming the strips, such as strip 72 of Figures 6 and 8, a field oxide is grown on the surface of region 71 and appropriate narrow strips are opened in the

80 oxide by conventional masking, photolithography and etching. An ion implanation operation then takes place using, for example, boron ions at a relatively heavy dose, for example, 3 X 1014 ions per CM2. A subsequent driveforabout 100 minutes at 1,2000C.

85 foilowsthe implantation to diffuse the boron ionsto a depth of 5 microns orgreater.

Thereafter, a masking oxide is grown to about 5,000Angstroms. Asecond mask isthen appliedto the oxide surface and windows are etched on the regions which are to receive a gate and N+ source strips 82 and 83 to be later described. A gate oxide is then grown on the exposed silicon surface to a thickness of about 700 Angstroms. Polysilicon is next deposited overthe full surface to a thickness of about 95 5,000Angstroms.

Athird mask is then applied overthe polysillcon surface and the desired polysilicon gate pattern is photolithog raphical ly formed on the device surface and the polysilicon exposed by thq mask is etched 100 awayto the gate oxide. The exposed gate oxide is also etched away and a relatively low ion dose,for example, 3 x 1013 ions per em' is then applied to form the more lightly doped P type regions 72a and 72b on either side of the P+ strip 72 and beneath the 105 gate oxide. A subsequentdrive for about 120 minutes at about 1,1 250C follows the implanation to diffuse the lightly doped region to a depth of 2-1/2 to 3 microns and to grow a masking oxide of approximately 1,500 Angstroms. This masking oxide is 110 used in the formation of the control circuit components, allowing a lightly doped P region to be diffused while preventing the laterformation of an N + region in the same window. The use of lightercloped P type regions 72a and 72b will reduce the threshold 115 voltage of the BOSFET, as will be described.

Afourth masking and photolithography operation isthen employedto open strips inthefield oxide, which strips are above drain regions 80 and 81. A fifth masking and photolithography operation is also

120 employed to open strips in the 1,500 Angstrom masking oxide above source regions 82 and 83 and selected areas of the control circuit. N + regions 80,81,82 and 83 are then convention a] ly formed as by diffusion. Regions 80 and 81 are N + strips which underlie 125 drain contact fingers 54 and 55. In general, however, the N+ regions 80 and 81 are parts of a digitated pattern having the general shape of the drain electrode 54 in Figure 5. Obviously, a similar pattern underlying the drain electrode 51 is also formed atthe same 130 time. N+ regions 82 and 83 of Figure Bare narrow GB 2 185 164 A 7 1 50 strips which underlie the source finger 56.Thereaf ter, a protective reflowed oxide coating is applied to the device surface and a masking operation opens windowsforthe necessary metallization including 5 source and drain contacts. Notethatsource contact finger 56 shorts the N+ regions 82 and 83 to the cen ter of P+ region 72. Clearly, other identical strips un derlie the other source strips and are formed within corresponding P type regions, such as the region 72.

10 The N + strips 82 and 83 define channel regions 72a and 72b which can be inverted to form N type chan nels for an enhancement type MOSFET action.

Elongated polysilicon gates shown as polysilicon gates 90 and 91 in Figure 8 overlie the channel re 15 gions 72a and 72b, respectively. The oxidethickness beneath the active polysilicon gate region abovethe channels 72a and 72b is extremelythin and is prefer ably about700 Angstroms, therebyto substantially reduce the threshold voltage of the device. The poly 20 silicon gates 90 and 91 are appropriately connected to the gate pad 61 of Figure 5 and are covered with respective layers 100 and 101 of Siloxor a glassy in sulation layerwhich insulates the conductive poly silicon gates 90 and 91 from the source metal strip 25 56.

Itwill be noted from the abovethatthe novel pro cess is a DMOS process in thatthe source and channel regions are self-aligned with the polysilicon gate. Indeed,the process is a triple diff used process if the initial N(-) region 71 is also included.

As shown in Figure 8a, the polysilicon layer9l en closes the ends of drain regions such as regions8l.

In accordance with a preferred arrangement,the gate oxide above the channel and drain regions such 35 as region 72b is terminated just priorthe point at which the polysil icon gate 91 beings its curvature.

This prevents exposure of gate oxide to hot carriers in avalanche breakdown, which occurs preferentially in this region of junction curvature. Damage to the 40 gate oxide is thereby avoided and the ruggedness of 105 the device is increased.

There is also present a conventional field oxide layer 93 in Figure 8 which extends across the entire surface of the device and which has a thickness, for example, of 1.2 microns. Using conventional pro cessing techniques,the oxide layer are appropriately opened and the drain electrodes including the drain fingers 54 and 55 and the source electrode strips 56, are deposited as shown. Note that a single metal sheet can be deposited overthe surface of the device to make contactto chip surface regions exposed by windows in the masking oxide and the metal can then be masked and cuttothe final desired pattern shown, for example, in Figure 5 and in Figure 8.

55 The resulting field effect transistor is a novel lateral 120 bidirectionally conducting field effect transistor (BOSFET) in which relatively high voltage can be connected between drains 50 and 51. When a suit able low voltage, as from a low current source, is 60 applied to the polysilicon gates 90 and 91, the under- 125 lying channels 72a and 72b overthe full area of the chip of Figure 5 will be invqrted so that currentwill flowf rom drains 50 through the inverted channel re gions to the source fingers such as source finger 56.

65 The current will then flow outwardly from sourcefin- 130 ger56 on the other half of the device again through the inverted underlying channels into the fingers of the drain 51 to establish a current conduction path between the two drain electrodes. Note that the de- 70 vice is a high voltage device since there is only a very small voltage difference between the polysilicon gate90-91 and the source fingers such as finger 56 which are clamped to a substrate reference voltage. Therefore, only a few volts will ever appear across 75 the thin oxide layer overlying channel regions72a and 72b, even though a very high voltage appears between the drain electrodes 50 and 51.

Consequently, the novel device as described has general application as an a-c or d-c switching power 80 MOSFET. The current rating of the device is, of course, limited only by the effective width of channels 72a and 72b and, in a device of the size described for Figure 2 of about71 x 92 mils, the current rating is about 200 milliamperes. The threshold vol- 85 tage of the device is extremely low in view of the thin gate oxide and is about 1 volt with full turn-on occurring at between 2 and 2-1/2 volts. The on resistance of the device is also relatively low and, for example, is less than about 25 ohms.

The spacing between the drain fingers, such as the drain fingers 54 and 55, in the embodiment shown, is about 8 mils center-to-center. The width of the P+ region 72 may be about 1 mil. With an arrangement of this type, itwas found thatthe lateral field stress

95 between any drain region such as regions 81 or80to the P+ region 72 is very well distributed along the surface of the wafer immediately eneath the field oxide 93. That is to say, the equi potential] ines along the surface are evenly distributed..Consequently,

100 local breakdown dueto high localized stress atthe surface is avoided.

The novel BOSFETstructure described to this point isverywell adapted to havethe diode 35 and PNPtransistor36 integrated therein in the region B of Figure 5. Thejunction pattern employed in the region "B" is shown in detail in Figures 7 and 9. Referring to Figures 7 and 9,the N(-) region 71 has an enlarged P+ diffusion 110 formed therein atthe sametime thatthe P+ diffusion 72 is made. Note in Figure 7that 110 the P+ diffusion 72 contains N+ strips 82 and 83 which are identical to those which underlie the source strip 56 in Figure 8 butthatthose of Figure 7 underlie the smaller length source strips on either side of region Bin Figure 5. Atthetimethe Ptype 115 diffusions 72a and 72b are performed, P type diffusions 11 land 112 are also carried outwithin the N(-) frame exposed within the P+ rectangular ring 110ofFigure7.AnN+contactregionll3andN+ region 114 are also made atthe time the N+ regions 82and83areformed.

The circuit and junction pattern defined in Figure 7 is shown in Figure 9. Thus, the diode 35 is defined by the PN junction formed between P region 11 land the N+ region 114. The N+ region 114is electricallyconnected to the polysilicon gate lattice which is connectedtothe gate pad 61 in Figure 5. The anode of diode 35 is electricallyconnected to the N +region 113 and is then connected to the positive terminal of the input circuitto the relay.

The PNP transistor 36, which is a very high gain 8 GB 2 185 164 A transistor, is formed of the P region 112, the N(-) body 71 and the P(-) body 70. The collector electrode is electrically connected to the P+ enclosing ring 110 which is connected to the P(-) body as 5 shown. Reg ion 110 is then electrical ly connected to the su bstrate electrode and to the negative term inal of the photostack input. Note that the formation of the PN P transistor is ideal ly suited to the steps used for producing the BOSFET device and a very hig h 10 gain transistor is inherently formed.

The resistor 37 of Figure 1 can be implemented on the chip in any desired manner. Preferably, as shown in Figure 10, the resistor can encircle the outer periphery of the chip of Figure 5 and can have a length, for example, from 100 to 200 mils to produce a resistor having a resistance from 1 to 5 megohms. Resistorterminalsare preferably formed underthegate pad 61 and in a P+ peripheral region 130 which is formed with the formation of the P+ regions72.

Figure 10 schematicaliy illustrates in dotted line 131 a planviewof an N() strip region 132extending aroundthechip peripheryand having itsendsspaced bytheP+ region 130,asshown in Figure 11.The strip 132 may have a width, for example, of 15mic- 25 rons. It is provided with N+ end pads 133 and 134 which are electrically connected to suitable terminals 135 and 136, respectively (Figure 11) which are then connected to appropriate potential nodes within the chip. Note that the N +regions 133 and 134 30 relative to the P+ region 130 define an inherent zener diode 140 (Figure 11) having a breakover voltage from 10 to 12 volts.

The novel BOSFETstructure described above can be implemented in other manners. Figures 12 and 13 35 show a second embodiment of a junction pattern which could be used to implementthe BOSFET. The junction pattern of Figures 12 and 13 should be compared to that of Figure 8 and similar numerals identify identical parts. The principal difference between 40 the arrangement of Figure 8 and that of Figures 12 and 13 isthatthe drains D1 and D2 are fully interdigitated. The P+ region 72 of Figure 8 is formed of two individual laterally spaced sections 150 and 151 in Figure 13 with a single N +region 152 disposed 45 centrally between them and connected to the source strip 56. N+ regions 160 and 161 arethen formed in the Ptype regions 150 and 151 to define two channels in each of P regions 150 and 151 which cooperate with pairs of polysilicon gates 162-163 and 164165, respectively (Figures 12 and 13). Gates 162-163 and 164-165 are periodically connected to gate metal strips 170 and 171 respectively.

Figure 14shows a circuit which can be integrated into the BOSFET chip previously described, where the circuit has advantages overthat of Figure 1, in regardto increased turn-off speed and independencefrom unintended dV/dtturn-on. Components similartothose of Figure 1 have been given similar identifying numerals in Figure 14.

The high speed turn-off circuit in Figure 14 consists of NPN transistor200, P channel MOSFET201 and resistor 202. These form a regenerative turn-off circuit which insures that the voltage on the inherent parasitic gate to substrate capacitance Ci., fol lows, and indeed, pu lls down the voltage of stack 19 when LED 21 turns off. Once the stack voltage fal Is anout 0.5 volt below the gate voltage of device 24, P channel MOSFET 201 tu rns on and Ci,, discharges th roug h MOSFET 200 and the base to emitter circu it 70 of N PN transistor 200. This turns on transistor 200 to discha rge stack 19 and to Iceep MOSFET 201 tu rned on during the discharge process. Note that components 35,200,201 and 202 are easily integrated into the BOSFET chip.

The switch-off speed of the switching circuit of Figure 14 is equivalentto the switching speed of the circuit of Figure 1 with resistor 37 equal to 470 kilohms. The circuit of Figure 14 does not require as low a value forthe discharge resistor 37 and there- 80 fore does not load down the photovoltaic pile as much. This improves the pick-up sensitivity and turnon speed of the circuit, as well as the turn-off speed.

Figure 14 also provides a dynamic a-c clamping circuitfor dV/dtsuppression. Thus,the distributed 85 drain-to-gate parasitic capacitance CD-G can permit a sufficiently high pulse currentto flow under a large enough dWdt between terminals 25 and 26 to turn on MOSFET24 in the absence of an input signal atterminals 22 and 23. The suppression circuit includes 90 resistor 210, capacitor 211 and NPN transistor 212, all of which can be integrated into the power MOSFET chip. The resistance-capacitance dividerwill actto turn on transistor 212 to ground the node between capacitor Ci and CD-G if the dV/dt across terminals 25 95 and 26 exceeds a given value.

In the circuit of Figure 14, resistors 202 and 210 are each 1 megohm, and capacitor 211 is 20 picofarads.

Referring to Figures 15 and 16, there is shown therein the starting waferfor making a photo- 100 generating waferwhich will be eTployed in a stack. The relative dimensions of the wafer of Figures 15 and 16, as well as laterfigures, are exaggerated out of proportion forthe sake of clarity. The waferof Figure 15 may be of high resistivity P type material 105 and the wafer is as thin as possible while being sufficiently strong to resist breakage under careful handling. For example, the wafer of Figures 15 and 16 is cutfrom an ingotformed byf loat zone crystal grown techniques and has a P type resistivity of app- 110 roximately 50 ohm centimeters. This is aboutthe highest practical value which can be obtained, However, lower resistivities could be used such as those used for conventional P type solar cell material such as 1 to 5 ohm centimeters. The use of high resistivity 115 material reduces the outputvoltage of each cell which is ultimately produced from the wafer, but a higher short circuit current will be available.

The wafer employed has a diameter of about 2 inches and has a thickness of about 7-1/2 mils which is 120 the thinnestthat can be handled in a commercial process without excessive breakage. Largerwafer diameters, for example 3 inches, could be used butthe thickness of the largerwafers would have to be increased, for example, to 9 mils.

The top and bottom surfaces of the wafer 320 of Figures 15 and 16 are oxidized by grown oxide layers 321 and 322 which have a thickness of about 0.4 micron each. A conventional photoresist mask layer 323 is then formed atop the oxide layer 322 in Figure 130 17. The wafer is conventionally etched to remove the ; I -e GB 2 185 164 A 9 unmasked oxide layers 322 while leaving the oxide layer 321 intact, as shown in Figure 18.

Thereafter, a boron containing carrier is deposited at least on the bottom unexposed surface of the 5 wafer 320 in Figure 18 and boron is then driven into the wafer to form the P+ region 330 shown in Figure 19. The drive used is a 10 hour drive at 1,250C and until the boron diffuses to a depth of about 1 mil. The drive in Figure 19 is carried out until a surface re10 sistivity of about 50 ohms persquare is reached. Note that the oxide layer 321 acts as a mask during the boron precleposition and drive processes. Also, during the boron drive, a layer of oxide 331 having a thickness of about 1 micron will grow on the bottom 15 su rface of the wafer in Figure 19.

Thereafter, and as shown in Figure 20, a photoresist layer 332 is applied overthe surface of oxide layer 331 and the unmasked oxide layer 321 is removed from the u pper su rface of the wafer in Fig u re 20 20.

Thereafter, an extremely heavy N + predeposition and drive using a POC13 source is used to form an N + region 333 in the unmasked surface. To diffuse the N + region 333 into the upper su rface of wafer 320, a 25 phosphorous source material is precleposited on the wafer at 1,1 250C fortwo hours and until the sheet resistance measured is about 0.8 ohm per square. Thereafter, the impurity is driven for 10 hours at about 1,2000C. This drives the N + region 333 to a 30 depth of about 1 mil. The drive is discontinued when the resistivity atthe N + surface of the wafer is about 0.5 ohm per square. Note thatthis surface resistivity of 0.5 ohm per square is e>qremely high and is obtained bythe presence of greaterthan about 1 X 1020 35 phosphorus ions per cubic centimeter atthe wafer surface. Indeed, the phosphorus ion concentrations could be as high as 2 x 1020 ions per cc which is approximately the solid solubility limit.

This novel N + diffusion will cause an increase in the lifetime of the P() region 320 since the phosphorus ions will act as a greaterfor metal ions in the silicon body. Moreover, the process for forming the extremely heavily doped N+ region 333 is the last process step for the formation of the junction pattern 45 and will permit the use of an aluminum foil or an aluminum eutectic as the means for alloying together a large number of wafers into a stack. That is, the aluminum wil I not invert the N+ layers 333 to a P type conductivity. Thereafter, and as shown in Figure 22, al I oxides are stripped from the wafer of Figure 21, as bythe use of a 6:1 hydrogen fluoride oxide etch.

The next step in the process in the formation of the stack, wherein as shown in Figure 23, ten wafers in- 55 cluding wafers 340,341 and 342 are stacked with 1 mil thickfoils 343 between them. Different numbers of wafers can be stacked. Foils 343 are preferably aluminum silicon eutectic foils having 88% aluminum and 12% silicon by weight. Eight mil thick 60 end plates 344 and 345 are stacked on the opposite ends of the stack and may be of pure aluminum. Note that if plates 344 and 345 are of aluminum silicon eutectic, the foils immediately adjacent plates 344 and 345 can be dispensed with. Plates 344 and 345 65 may also be of silicon.

The entire stack is then held under light pressure in any appropriate way and is placed in a suitable apparatus for alloying togetherthe stack. For example, the stack can be placed in a beltfurnace using 70 a nitrogen gas purge. The furnace should be at a temperature which will produce an 800'C peakfor about 5 minutes over a total travel time through the oven of about45 minutes. Conventional alloying surfaces can also be used.

Afterthe stack has been alloyed, the stack is diced into slabs of a desired dimension which slabs are formed by cutting through the stack in a direction parallel to the axis. Figure 24 shows one slabformed from the stack of Figure 23 and which is cut byany 80 suitable conventional single or multiple blade saw. The slab of Figure 24 has the typical dimensions of about 20 mils wide by 60 mils long. The slab height is defined bythe total height of the ten silicon wafers and connecting foils defining the slab and is app- 85 roximately 100 mils. Otherwidth and length dimensions and other numbers of wafers per stackcould be used. Thus, slab elements of 40 mils by 15 mils might also be used. Note particularly that the 100 mil height produced bythe slab of ten wafers is small so 90 thatthe distance from an illuminating LED which may be 30 mils from the center of the slab is notvery differently spaced from any wafer element of the slab.

A photovoltaic slab of Figure 24 can now be 95 assembled into a photovoltaic isolator as is shown in Figures 25 and 26. Thus, in Figures 25 and 26, there is shown a support base 350 which suitably supports the slab 351 of Figure 24with electrodes 352 and 353 extending from the top and bottom electrodes 345 100 and 344, respectively. A conventional LED 360, having electrodes 361 and 362 is preferably an infrared output LED, isthen seated on support 350 and is generally centered on the slab but is spaced from the slab by a sufficient distance, for example 30 mils,to 105 produce the desired dielectric isolation (3,750 volts) between the LED electrodes and the stack electrodes. In Figures 25 and 26, the housing heightwill be slightly greaterthan about 60 mils and the diameter will be slightly greaterthan about 60 mils and the 110 diameter of the top of the housing will be about 125 mils. The assembly is then covered with a transparent insulative silicon body

370 which is transparentto the LED radiation. The silicone body 370 is coated 115 with a reflective coating 37 1. Preferably, the coating 371 consists of silicone of the same formulation as body 370, but contains a white reflective material, for example titanium dioxide powder, suspended therein. The use of silicon for suspending powder in- 120 sures adherence of the coating 371 to the silicon body370.

Figure 27 shows a detail of the stack of Figures 24, 25 and 26, and shows howthe damage bythe dicing saw is contoured by the end plates 344 and 345. In 125 particular,the plateswiil have rough-bevelled or roughened edges such as edges 401 and 402 in plate 344 and edges 403 and 404 in plate 345. Plates 344 and 345 arethick enough to receive all saw damage and the saw damage does not extend to thejunctions 130 in the wafers adjacent the end plates. Plates 344 and 10 GB 2 185 164 A 345 also have sufficient thickness or "stand-off" to receive conductive epoxy masses 410 and 411, respectively, which maybe used to cement the stackto the end edges of spaced lead from elements or other 5 electrodes 412 and 413, respectively, without danger of shorting across the active junctions adjacent the end plates.

Although the present invention has been described in connection with a number of preferred emb- 10 odiments thereof, manyvariations and modifications will now become apparentto those skilled in the art. Therefore,the present invention is limited not bythe specific disclosure herein, but bythe appended claims.

Attention is directed to co-pending patent application number 8501283from which this application has been divided and to application (agents reference 230P49574A) which has also been divided from application number8501283.

Claims (10)

1. A photovoltaically operated solid state relay circuit comprising:

a photovoltaic isolator circuit comprised of an LED means having input energizing terminals, and a photovoltaic pilewhich is optically coupled to said LED means and is dielectrically isolated therefrom; said photovoltaic having positive and negative 30 outputterminals which have a voltage produced therebetween in responseto illumination by said LED means; characterized in containing a bidirectional output serniconductorfield effect tra nsisto r means having 35 first and second powerterminals, a gate terminal and a substrate terminal; a resistor connected across said positive and negative output terminals; a diode having an anode connected to the positive terminal of said photovoltaic pile and a cathode connected to said gate terminal; and a high gain transistor; said high gain transistor having a base connected to said anode of said diode, an emitter connected to said cathode of said diode 45 and a collector connected to said substrate terminal; whereby, the generation of an outputfrom said photovoltaic pile produces sufficient power to turn on said field effect transistor means at high speed and, whereby, when the voltage output of said pile 50 drops below a given value, said high gain transistor turns on to reduce the relay circuit input impedance.

2. A circuit as claimed in claim 1, wherein the bidirectional output semiconductorfield effecttransistoris capable of withstanding greaterthan aboutfifty 55 volts between its outputterminals and being s,.,,,titched into conduction in response to the application of a voltage greaterthan about one volt between said gate and substrate terminals and said resistor has a value greater than 1 00k ohms.

3. The circuit of claim 1 or 2, which is further chracterized in that said high gain transistor is a PNP transistor.

4. The circuit of claim 3, which is further characterized in that said field effect tra nsisto r means, 65 said diode, said PNP transistor and said resistor are integral components formed in a single chip silicon.

5. The circuit of claims 1, 2,3 or4, which isfurther characterized in that said field effect transistor means is a metal oxide semiconductorfield effect 70 transistor device which has negligible leakage current when off and which has a conduction resistance between its said power terminals of less than about 25 ohms.

6. A switching circuit for rapidly switching on 75 and rapidly switching off a power metal oxide semiconductorfield effect transistor; said powertransistor having drain, source and gate electrodes; said switching circuit including an input unidirectional voltage source having first and second terminals 80 switchable between a high and low inputvoltage, a diode means and a switching transistor having first and second electrodes and a control electrode; characterized in that said first and second terminals of said voltage source, said diode means and said gate 85 and source electrodes of said powertransistor are connected in closed series relation with a polarity whereby currentfrom said voltage source can flow through said diode means to charge the gate capacitance of said power transistor when said voltage 90 source is switched to said high voltage; said first and second electrodes of said switching transistor connected to said gate and source electrodes, respectively, of said power transistor; said control electrode connected to said first terminal of said 95 voltage source,whereby said switching transistor is switched on to define a discharge path across said gate capacitance when the voltagp of said voltage source is reduced from said high voltage to said low voltage.

7. The relay of claim 6, which is further characterized in including a dynamic clamping circuit connected between said gate and source electrodes of said outputtransistor; said dynamic clamping circuit being operable to bypass the Miller current in 105 the parasitic drain-to-gate capacitor of said output transistorwhen the dV/dt of a voltage between said drain and source electrodes exceeds a given value.

8. The relay of claim 7, which is further characterized in that said dynamic clamping circuit inclu- 110 des a series-connected resistor and capacitor and a transistor connected in parallel with said resistor and capacitor; said transistor having a control electrode connected to the node between said resistor and capacitor.

9. A photovoltically operated relay, substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.

Amendments to the claims have been filed, and have 120 thefollowingeffect (a) Claims 1-9 above have been deleted.

(b) New ortextually amended claims have been filed asfollows:- 125 CLAIMS 1. A photovoltaica Hy operated sol id state relay circuitcomprising:

a photovoltaic ísol ator ci rcuit comprised of an LED 130 means having input energizing terminals, anda GB 2 185 164 A 11 I photovoltaic pilewhich is optically coupled to said LED means and is dielectrically isolated therefrom; said photovoltaic having positive and negative outputterminals which have a voltage produced therebetween in response to illumination by said LED means; characterized in containing a bidirectional output sem icon ductor field effect transistor means having first and second output power termaina Is, a gateter 10 minal and a substrate terminal; a diode having an anode connected to the positive terminal of said photovoltaic pile and a cathode con nected to said gate terminal; and a high gain transistor; said high gain transistor 15 having a switching terminal connected to said anode of said diode, a first electrode connected to said cathode of said diode and a second electrode con nected to said substrate terminal; whereby, the generation of an outputfrom said 20 photovoltaic pile produces sufficient power to turn 85 on said f ield effect transistor means at high speed and, whereby, when the voltage output of said pile drops below a given value, said high gain transistor turns on to reduce the relay circuit input impedance.

2. A circuit as claimed in claim 1, wherein said switching terminal, said first electrode and said second electrode are respectively the base, emitter and collector of said high gain transistor.

3. A circuit as claimed in claim 1 or 2, wherein the 30 bidirectional output semiconductor field effecttrans istoris capable of withstanding greaterthan about fiftyvolts between its outputterminals and being switched into conduction in responsetothe applica tion of a voltage greaterthan aboutonevolt between said gate and substrate terminals and said resistor 100 has a value graterthan 100k ohms.

4. The circuit of any preceding claim, which is further characterized in that said high gain transistor is a PNP transistor.

40 5. The circuit of claim 4, which is further char acterized in that said field effect transistor means, said diode, said PNP transistor and said resistor are integral components formed in a single chip of sil icon.

45 6. The circuit of any preceding claim, which is further characterized in that said field effecttransis tor means is a metal oxide semiconductor field effect transistor devicewhich has negligible leakage cur rentwhen off and which has a conduction resistance between its said powerterrninals of lessthan about ohms.

7. A switching circuit for rapidly switching on and rapidly switching off a power metal oxide semi conductorfield effect transistor; said powertransis tor having drain, source arld gate electrodes; said switching circuit including an input unidirectional voltage source having first and second terminals switchable between a high and low inputvoltage, a diode means and a switching transistor having first 60 and second electrodes and a control electrode; char acterized in that said first and second terminals of said voltage source, said diode means and said gate and source electrodes of s ' aid powertransistor are connected in closed serie relation with a polarity whereby current from said voltage source can flow through said diode means to charge the gate capacitance of said power transistor when said voltage source is switched to said high voltage; said diode means being connected to said switching transistor 70 in such a manner that voltage developed across said diode meanswhile charging said gate capacitance inhibitsturn-on of said switching means; said first and second electrodes of said switching transistor connected to said gate and source electrodes, re- 75 spectively, of said powertransistor in such a way as to enable substantially immediate turn-off of said switching transistor upon the voltage of said voltage source being reduced from said high voltage to said lowvoltage; said control electrode connected to said 80 firstterminal of said voltage source, whereby said switching transistor is quickly switched on to define a rapid discharge path across said gate capacitance when thevoltage of said voltage source is reduced from said high voltage to said lowvoltage.

8. The relay of claim 7, which isfurther characterized in including a dynamic clamping circuit connected between said gate and source electrodes of said output transistor; said dynamic clamping circuit being operable to bypass the Miller current in 90 the parasitic drain-to-gate capacitor of said output transistor when the dWdt of a voltage between said drain and source electrodes exceeds a given value.

9. The relay of claim 7, which is further characterized in that said dynamic clamping circuit inclu- 95 des a series-connected resistor arld capacitor and a transistor connected in parallel with said resistor and capacitor; said transistor having control electrode connected to the node between said resistorand capacitor.

10. A photovoltaically operated relay, substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.

Printed for Her Majesty's Stationery Office by Croydon Printing Company (UK) Ltd, 5187, D8991685, Published by The Patent Office, 25SouthamptonBuildings, London, WC2A 1AY, from which copies maybe obtained.