GB2185366A - Multi-phase PSK demodulator - Google Patents

Abstract

A multi-phase PSK (phase shift key) demodulator is applied to recover binary encoded serial data from a continuous multiphase modulated signal source. This demodulator mainly comprises a carrier detector 17, hard limiters 11,14, a harmonic phase-locked clock regenerator 12, a digital multi-phase demodulator 15, a data clock divider 13 and a reference phase synchronizer 18. The digital multi-phase demodulator 15 receives the output of the harmonic phase-locked clock regenerator 12 and N-th phase rectangular wave PSK signal to produce demodulated binary encoded parallel data. Then the demodulated parallel data is converted into serial data via a parallel-to-serial converter 16. The reference phase synchronizer 18 can obtain a phase reference from a leader preamble or a continuous distributed sync word. Thus transmission is not required for phase resynchronization. The regeneration of the carrier-related clock signal and data demodulation are independent of data pattern if the input signal is preemphasized or conditioned. <IMAGE>

Description

SPECIFICATION Multi-phase PSKdemodulator Background of the invention The present invention relates to a multi-phase PSK (phase shift key) demodulator.

Important parts of a PSK demodulator circuit normally include a carrier synchronizer (regenerator) and a multi-phase data demodulation means by detecting the input signal with the reproduction carrier. Numerous circuits concerning the carrier synchronizer have been disclosed before including popular ones such as Costas loop, Nth power loop and early-late gates loop. The Costas loop has potential phase detector imbalance problem, whereas the Nth power loop can have "ideal power" problems. And most of these circuits process input signal with analog mixer, phase shifter and voltage summer. In practice, their performance is easily suffered from the circuit impairments such as offset voltage, internal noise and delay accuracy.

Summary ofthe invention It is an object of the present invention to provide an improved method and apparatusfor demodulating a continuous multiphase PSK signal.

It is another object of the invention to recover the carrier clock, symbolic clock and data through the information of continuous PSK signal's zero-crossing transitions.

It is another object of the invention to obtain reference phase synchronization through a frame synchronization without retransmission.

It is another object of the invention to recover the data clock and data from a continuous PSK signal without the error introduced from "ideal power" problem or data pattern variation as in Nth power loop.

The present invention, because of the continuous phase modulated input source, provides a simplier structure reproducing the required carrier and encoded data through most digital means.

In accordance with this invention, there is provided a continuous PSK demodulator comprising a full wave rectifier to slice the input signal which has been pre-conditioned into an uni-polar clocktracking signal, a hard limiter converting the uni-polar signal into a rectangular wave signal, a harmonic phase-locked clock regeneratorfor reproducing a N-th (N=2n, n being a natural number) time harmonic frequency of the carrier, a frequency divider dividing the harmonic clock signal into a serial data clock, a hard limiter converting input signal a N-th rectangular PSKwave, a demodulatortranslating the N-th rectangular PSKwave into a binary encoded parallel data, a parallel to serial converter converting the parallel data into a serial form, a carrier detect circuit detecting input carrier activity to initialize the following mentioned reference phase synchronizer, a reference phase synchronizer correlating a predetermined pattern preamble of the input signal after initialization by carrier detect circuitto generate phase pulse chain synchronizing the demodulator and the frequency divider to proper phase relationship and an input signal source in terms of a message form with a leader preamble period and followed by data field in a continuous N-phase PSKformat.

In another embodiment, the input signal source further includes a distribution sone word encoding. Thus the reference phase can be obtained again inside the data field by a frame synchronization.

Briefdescription ofthe drawings The invention will now be further described in conjunction with the accompanying drawings, in which Figure lisa block diagram of multi-phase PSK demodulator, Figure2 is a block diagram of a harmonic clock regenerator, Figure3 is a bock diagram ofandemodulator, Figure 4 is a block diagram of a data clock divider, Figure 5is a block diagram of a reference phase synchronizer, Figure 6 is a block diagram of an example of an input signal structure and timing relationship to signals generated by carrier detect and reference phase synchronizer, Figure 7is atable of a continuous multi-phase PSKsignal with N=4example, Figure 8 is a block diagram of another embodiment's input signal structure and timing relationship to signals generated by carrier detect and reference phase synchronizer, and, Figure 9 is a block diagram of another embodiment's reference phase synchronizer.

Detailed description of the preferred embodiments ofthe invention Turning now to figure 1, a continuous N-phase (N =2) PSK modulated signal with a modulation frequencyf Hz is applied to terminal 100. In this embodiment,the carrierfrequency has been assigned same as modulation frequency for convenience but the invention does not prevent the carrierfrequencyto be a multiple of modulation rate. To the extreme, the N-phase's N number may be other integer. Normally, this input signal is sent by a transmitter in terms of a message form with a preamble pattern leader as shown in figure 6. The pattern sone word is M modulated symbols wide and is repeated through out the preamble period. Waveform with different degrees shifted example-for a QPSK continuous modulation format is shown in figure 7.The leader period is provided for the demodulator's clock regeneratortraining period and reference phase synchronization.

The PSK modulated signal source applied at terminal 100 is sliced by a full wave rectifier 10 into an uni-polar signal. The rectification is to increase the positive transitions which are used for phasetracking.

This rectified signal is sensed before applying to an input of a harmonic clock regenerator 12. This harmonic clock regenerator 12 produces a N-f Hz clock output which is divided into a serial data clockwith n-f Hz by divider 13. The N-f Hzclockfrom harmonic clock regenerator 12 also applies two inputs of digital multi-phase translator 15 and reference phase synchronizer 18 through circuit path 102. The n-f Hz data clockgenerated by divider 13 is connected to clock input C of parallel to serial converter 1 6through circuit path 103.

The input signal from terminal 100 is also received by hard limiter 1 4which converts the PSK signal into a rectangularwave sequence. This N-th digital PSKwave is fed to digital multi-phase translator 15 and reference phase synchronizer 18 through circuit path 104. Digital multi-phase translator 15 also receives the N-f Hz clock frequency through circuit 102 and decodes the data sequence into a bit wide paraalel output.

Duringthe preamble period, translator 15 receives also a chain of reference phase signals REFSYfrom the reference phase synchronizer 18 to reset itto proper phase relationship. During normal data period, a negative active signal P. LOAD is generated at circuit path 106 by digital multi-phase translator 15 to indicate the decoded paralle data ready at circuit path 105. An error signal ERROR is also generated at circuit path 109 if any illegal data sequence is detected (caused by input noise or phase segment slip) by digital multi-phase translator 15. This error signal ERROR can be used externally to request the transmitter to retransmitthe initial preamble sequence again. Parallel to serial converter 16 accepts the parallel data from translator 15 through circuit path 105 during P. LOAD low period.It also accepts the serial clockfrom circuit path 103to propagate outthe serial data to circuit path 107.

Input signal from terminal 100 also applies to carrier detect circuit 17. The moment of detecting the existence of a carrier triggers a one-shot pulse output named SYNCDTat circuit path 110. It is fed to reference phase synchronizer 18 and divider 13. This one shot pulse width should be less than the preamble leader duration. Reference phase synchronizer 18 is enabled to sortforthe predetermined pattern code during this one shot active period. Divider 13 also allows the phase synchronization during this period. For every predetermined sync code sorted by reference phase synchronizer 18, there is pulse REFSY generated atthe output which is fed to translator 15, divider 13 and parallel to serial converter 1 6through circuit path 108.

Nowturning to figure 2, a harmonic clock regenerator is comprised of a non-linear phase locked loop. The output of hard limiter 11 is connected to input of delay device 20 and C input offlip flop 24 through circuit path 101. The output of delay device 20 is fed to one inputofthe sequential phase/frequency detector. Thedata D input offlip flop 24 is connected to VCC (high state).Thus a positive edge of the signal applied to clock input C offlip flop 24causes its Q output high which applies two D input offlip flop 25. By the time a positive edgeof voltage controlled oscillator (VCO) 23 output appears at clock input C offlip flop 25,the high signal applied at D input is clocked to Q output which is fed to another input of the sequential phase/frequency detector 21 and resetterminal R offlip flop 24. Thus flop flop 24 is reset Its Q output is fed to resetterminal R offlip flop 25 and causes flip flop 25 reset also. If there is no positive edge applies two C input of flip flop 24, its Q output offlip flop 24 kepts at low.So even when there is a positive edge applied at C input offlip flop 25, there will keep at lowtoo at its Q output. Thus as a result, for every positive edge applied to C input offlip flop 24, there is a pulse generated at Q output offlip flop 25 synchronized by positive edge of signal from voltage controlled oscillator (VCO) 23. The positive edge of the incoming signal at circuit path 101 delayed by delay device 20 of 1 2Nf second is phase/frequency compared with the positive edge of the pulse from flipflop 25 Q output by a sequential phase/frequency detector 21. This detector is normally a charge-pumptri-statetype of which the error signal is filtered by low pass filter (LPF) 22 into a direct current signal.This direct current signal controls the voltage controlled oscillator (VCO) 23 to generate the required N-f Hz output. Voltage controlled oscillator (VCO) 23 provides a frequency maximum adjust, of which the frequency maximum has to be tuned less than 2N.f Hz in order preventing locking to other undesired harmonic frequency. Of course, a narrow pulling range crystal or LC oscillator does not require frequency limit tuning. The output of voltage controlled oscillator (VCO) 23 is also fed backto C input offlip flop 25. Sincethe positive edges apply to circuit path 101 at different harmonicfrequencies and the phase comparison is active only during a positive edge applied at circuit path 101 the system can be considered as a non-linear phase locked loop.Furthermore, if the hard limiterrs gain is sufficient, input signal's AM to PM is minimized and the regeneration of N.f Hz output is independent to input signal's pattern and waveshape.

Now turning to figure 3, a digital demodulator is illustrated. It is mainly comprised of a shift register, decoding circuit and a counter. The shift register 30 receives the N-th digital PSKwave from hard limiter 14 through circuit path 104. The N-f Hzclocksignal from harmonic clock regenerator 12 through circuit path 102 clocks the data into the shift register 30. The N-1 bit parallel output of shift register 30 and the last bit applied at line 104 is received by the decoding circuit 32 and is translated into a n-bit parallel output at circuit path 105.

The counter 31 is reset at proper phase relationship with data by a signal REFSYfrom reference phase synchronizer 1 8through circuit path 108 applied to its synchronous reset terminal SR. The N-f Hz clock signal applied at circuit path 102 is divided by counter31 into a carry signal P. LOAD at circuit path 106 indicating decoded data ready at circuit path 105. Atthe same time, this carry signal from counter 31 is also gated into the decoding circuitto sample the validation of the parallel input. lfthere is any phase segment slip orwrong data sequence, it is sensed by the decoding circuit 32 and a signal ERROR is outputted at circuit path 109.This ERROR signal line 109 is useful and valid for all N-phase PSK encoding except binary case (N=2). An example of a QPSK (N=4, n=2) decoding relationship is shown in figure 7.

Turning now to figure 4, a universal divider is shown to convert N-f Hz harmonic clock frequency into n-f Hz serial clock rate. Of course, if n is in turns of 2's power, a simple digital dividing counter with reset input as shown in figure 1 is sufficient. However, the ratio of N n is not always an integer, a phase locked loop is applied for the divider of general case in figure 4. The N-fHz clock signal applied at circuit path 102 is divided by counter 40 into a carry signal off Hz. This f Hz frequency is normally routed through selector 41 to one input of phase detector 43.The n-f Hz clock rate generated by voltage controlled oscillator (VCO) 45 is divided by counter 48 into a carry signal off Hz frequency is also normally routed through selector 46to the input of phase detector 43. The phase detector 43 compares these two input signals' positive edge phases to produce an error signal which is filtered by low pass filter (LPF) 44.

The phase detector may be comprised of a D-typeflipfiop, exclusive OR-gate, a charge-pumptype or other edge comparison detector, although a sequential phase/frequency charge-pump type is preferred. The filtered direct current signal from low pass filter (LPF) 44 applies to input of voltage controlled oscillator (VCO) 45 to produce the required n f Hz frequency output at circuit 103. During the preamble period indicated by the signal SYNCDT genrated from carrier detect 17 output applied at circuit path 110, the phase locked loop is enabled to trackthe reference phase signal REFSY in order to achieve the N/n divider phase synchronization.The reference phase pulse signal REFSY applies at circuit path 108 which is connected to synchronous reset input SR of counter 40 and input of inverter42. Counter 40 is reset synchronously with this reference phase signal REFSY. Inverter42 inverts the reference phase signal to proper edge same as the carry output of counter 40. The signal SYNCDTfrom carrier detect 17 output is connected to select S inputs of selector 41 and 46 through circuit path 110. During the signal SYNCDT is active on circuit path 11 swithin preamble period, selector 41 selects input from invert 42 output and selector 46 selects inputfrom counter 47's carry output.Since the sync pattern word inside the preamble period is M modulated symbols wide, the reference phase signal REFSY isf/M Hz and counter47 dividing ratio should be M in orderto match the comparing frequencies. At a result, the N/n divider accepts a signal REFSYf/M Hz from reference phase synchronizer 18 for phase tracking during carrier detect 17 output active period and switches to acceptthe normal N f Hz harmonic clock regenerator 102 outputfor phase tracking during normal data period while counters 40 and 48 are synchronized.

Nowturning to figure 5, a reference phase synchronizer 18 comprises a shift register, an inverter and a leader pattern correlator. The reference phase synchronizeris enabled only during preamble period by a signal SYNCDT generated from carrier detect 17 through circuit path 110, otherwise is reset. The digital sequence from the hard limiter 14th rough circuit path 104 is clocked into shift register 50 by the N-f Hz harmonic clock through circuit path 102. This clock signal is also connected to input of inverter 51. The shift register 50 is (M-N-1) bit wide where Mis the number of modulated symbols in a preamblesyncword and N is the pulse segments in a modulated symbol.The pattern correlator 50 checks the (M.N-1) bits from shift register 50 putput plus a further bit on line 104 (total MN Hz N bits) for the presence of syne wo rd during second half cycle of the N-f Hz harmonic clock provided by inverter 51 output. If the circuit detects the syne word, a positive signal pulse REFSY is generated. Thus for normal condition, There is a chain of pulse REFSY generated at circuit path 108 during peramble period. This chain of pulses REFSY is used for reference phase synchronization of the translator 15 and divider 13.

A preferred embodiment of the invention has been described but itwill be appreciated thatvanous modifications may be made by persons skilled in the art. Thus the invention is not limited to particular frequencies, sync pattern format or the number of phase segments in a modulation symbol. Moreover, if the modulation frequency is low enough (such as less than 1 OKHz), the logic circuits of translator 15, reference phase synchronizer 18, divider 13 and parallel to serial converter 16may be replaced by a processortype element which itself is a logic means.The processor according to its preset commands samples input pulses' clock periods (such as harmonic clock, data clock, limited input signal and carrier detect), manipulates logic decisions and compares results with preset ratios or values and switches its output (such as serial data clock, parallel data, reference phase signal and serial data) at propertimes calculated. Most operations may be carried out concurrently in a single processor. Pulse counting method or logic operation implemented bya processor routine has been exam pled in many text books.

The above stated embodiment extracts the reference phase from the preamble leader period. If there is any phase segment slip in the data field, there is less way to recover the reference phase again excepta retransmission sequence is requested. Another preferred embodiment ofthe invention is disclosed to anticipate the problem. If the incoming signal source isfurther encoded with a distributed syne word inside the data field, the reference phase can be extracted again by a reframing synchronization after a phase slip detected.

The basic block diagram is same as figure 1. The message structure shown in figure 6 is alternated byfigure 8 and the reference phase synchronizer in figure 5 is alternated by figure 9.

Now turning to figure 8, a suggested input signal message is shown. The message is leaded by a preamble repeated sync pattern and followed by a data field encoded with distributed sync words inside. Thus the data field is a type offrame structure which has X sub-frames. Each sub-frame has Y modulated symbols wide with a syne sym bol at the end. A symbol is a value representing the signal interval of each modulation time slot The repeated sync symbol fields are filled with a predetermined syne word. Th is syne word is preferred to be an asymmetric type to provide lower probability locking to opposite phase segments during frame resynchronization.

Now turning to figure 9, a modified reference phase synchronizer is shown. The leader reference phase synchronization circuit is same as shown in figure 5. The addition is mainly a distributed sync word correlator 53 and a reframe circuit 54. The data sequence from the hard limiter 1 4through circuit path 104 is connected to inputs of shift register 50, leader pattern correlator52, distributed sync word correlator 53 and a reframing circuit 54. The N.f Hz harmonic clock from harmonic clock regenerator 12 through circuit path 102 is connected to leader pattern correlator 52 through inverter 51, clock inputs of shift register 50, distributed sync word correlator 53 & reframing circuit 54. During preamble period,the reference phase signal from leader pattern correlator 52 applies two synchronous reset terminal SR of distributed sync word correlator 53 through OR-gate 55. Thusthe distributed sone word correlatoris synchronized by the reference phase signal from leader pattern correlator 52. During data field, a full frame counter inside the distributed syncword correlator 53 counts four a full frame of data (N-X-Ybits) and vertifies forthe distributed sync word. If there is no error, it indicates that there is no phase segment slip in the system.A LFB signal is generated at the last bit of a full frame digital sequence. This last fame sequence bit LFB signal applies two synchronize the reframing circuit 54. It is also combined with reference phase signal from leader pattern corelator 52 by OR-gate 56 into a signal REFSYto synchronize divider 13 and translator 15 in figure 1. If the sync word is not detected in distributed syne word correlato r 53, a slip of phase segment has been likely occured.A request to reframe signal RFREQ is generated by distributed sync word correlatr 53 during LFB active period. Reframing circuit 54 accepts the reframing rnquestsignal RFREQ and carries outa reframing process of a conventional way as stated in many text books and not illustrated here. Afterthe reframing is completed, the new position of sync word relative to the signal LFB has been obtained.A signal REFRM is generated at proper time bythe reframe circuit 54 and is fed to synchronous resetterminal SR of distributed sync word correlator 53 through OR-gate 55 in orderto synchronizethe correlator 53 tothe correcttime position agian. Indirectly, the lastframe sequence bit LFB and then reference phase signal REFSY is adjusted to correct time slot. As a result,the signal REFSYwhich is connected to translator 15 and idvider 13 in figure 1 synchronizes the system's phase relationship agian. Since REFSY signal which is same signal as the last fame bit LFB during data field period, it may be used for demultiplexing the frame structure data into sub-channels data.

The second preferred embodiment of the invention has also been described. Various other modifications may be apparent without departing from the spirit ofthe invention.

Certain alternation of circuit or signal is possible for hardware and performance trade-offwithoutchanging the invention's principle. As we known that normal QPSK has a good passband but high sidelobes and multi-frequency shifted key or MSK occupies a broad frequency band. The continuous multi-phase PSK may be encoded and adapted to have a narrow passband and superior rolloff behaviour to suit for a magnetic recording media such as cassette tape, floppy disk or hard disk, telephone subscriber line or other narrow passband channel such as a frequency-multiplexing channel. This coding for the continuous multi-phase PSKsignal consists mainly of two requirements.Thefirstone isto restrict a maximum time distance between two transitions within a modulated symbol or two adjacent symbols in particularto prevent a creation of a lowfrequency waveform along modulated symbols. This guarantees the low corner frequency of the pass band before any application of data scrambling. In order to do this, some of the 2N codings orcombinations of a symbol which carry the transitions' distance/s existing the required limit have to be eleminated (N=number of phase segments in a segment). The second one isto have a smooth zero crossing and to minimize the high sidelobes. This provides an equivalent partial response coding of the waveform between symbolsand ensures the phase Variation of any zero-crossing to be minimum. Of course, the signal may further contain an amputate or phase pre-emphasisfora pre-compensation of a channel's response, an error correction coding for an improved error rate, or a data scrambling for an expected D.C. mean.

Claims (13)

1. A multi-phase PSK (phase shift key) demodulatorfor operating upon an input signal representing a continous N-th phase (N=2", n being a natural number) PSK modulated source with a predetermined sync preamble and outputting a binary encoded serial data independent of data pattern when said input signal I being preemphasized or conditioned, said demodulator comprising:: a) a full wave rectifier means slicing the input signal into an uni-polarsignal, b) a first hard limiter means converting the uni-polar signal into a rectangular clock tracking signal source, c) a harmonic clock regenerator means receiving said rectangular clock tracking signal source for reproducing a N-th time harmonic frequency source of the carrier independent of signal's data pattern and feeding said harmonic frequency souce to a multi-phase translator and reference phase synchronizer, d) a second hard limiter means converting the input signal into a N-th phase rectangu larwave PSKsignal, e) said digital multi-phase translator means responding to clock output of the harmonic clock regenerator and rectangular PSK signal output of second hard limiterfor producing a binary parallel data, f) a frequency divider means dividing said N-th time harmonic frequency source into a serial data clock, g) a parallel to serial converter means converting said parallel data into serial one with the application of data clock, h) a carrier detect means generating a one-shot signal during the preamble period to control the frequency divider and enable a reference phase synchronizer, and, i) said reference phase synchronizer means extracting the reference phase signal from the preamble sync pattern to synchronize said digital multi-phase translator and frequency divider.

2. A multi-phase PSK demodulator of claim 1 wherein: a) said harmonic clock regenerator means comprises a non-linear phase locked loop comparing phases only during one directional edges of said clocktracking source applied to its input, b) said frequency divider means comprises either (i) a digital counterfor most divisible ratios or (ii) a phase locked loop dividing circuit for all general cases, c) said digital multi-phase translator means comprises a decoding circuit converting the N-th rectangular PSK signal into a parallel binary data, a counter generating a carry signal indicating decoded data ready and an error signal output indicating any illegal N-th rectangular PSKsequence or avalidation of phase slip except the BPSK (N=2, binary phase shift key) case, and, d) said reference phase synchronizer means comprises of a shift register and leader pattern correlatorto sort the sync pattern during preamble period and to generate a chain of syne pulses synchronizing said digital multi-phase translator means and frequency divider.

3. A multi-phase PSK demodulator of claim 2 wherein said non-linear phase locked loop meansfurhter comprises: a) a delay device means delaying the input signal's edge of half phase segment (i.e.

1 2Nf second, f is the modulation rate), b) a synchronous latch means storing the input signal's one-direction edge and being reset by a pulse generated from a sampling latch, c) said sampling latch means accepting a clock signal feedback from the following stated voltage controlled oscillator output to generate a pulse at its output after an one directional edge latched by said synchronous latch, d) a sequential phase/frequency detector means comparing edges' phases from said delay device output and sampling latch, e) a low pass filter means filtering said sequential phase/frequency detector's output into a direct current signal, and, f) a voltage controlled oscillator means accepting said low passfilter's output to generate a frequency source of Nf Hz at its output and requiring thefrequency maximum limited to less than 2Nf Hz and minimum limited to more than 0.5Nf Hz.

4. A multi-phase PSK demodulator of claim 1 or 2 wherein said frequency divider means for general cases comprising: a) a dividing by N counter means dividing said N-th time harmonic frequency by N to have a carry signal output and accepting synchronous reset from a said reference phase signal, b) a dividing by n counter means dividing a voltage controlled oscillator output by n and having a carry signal output, c) a dividing by M counter means dividing said carry output of said 'dividing by n counter' by M (where Mis a number of modulated symbols of a syne word) and having a carry signal output, d) a first selector means accepting the carry signal from said 'dividing by N counter' as input during data field period and said reference phase signal as input during preamble period, e) a second selector means accepting the carry signal from said 'dividing by n counter' as input during data field period and from said 'dividing by M counter' as input during preamble period, f) a phase detector means comparing phases from both said selectors' outputs with a locking frequency off Hz during data field period and f/M Hz during preamble period, g) a low pass filter means accepting said phase detector's output into a direct current signal, and, h) said voltage controlled oscillator means receiving said low passfilter's output to generate a n-f Hz signal output.

5. A multi-phase PSK (phase shift key) demodulator with a distributed reference phase synchronizerfor operating upon an input signal representing a continuous N-th phase (N=2n, n being a natural number) PSK modulated source with a predetermined sync preamble and a distributed sync word in data field structure and outputting a phase self-synchronized binary encoded serial data independent of data pattern when said input signal being preemphasized or conditioned, said demodulator comprising:: a) afull wave rectifier means slicing the input signal into an uni-polarsignal, b) a first hard limiter means converting the uni-polar signal into a rectangular clocktracking signal source, c) a harmonic clock regenerator means receiving said rectangular clocktracking signal source for reproducing a N-th time harmonic frequency of the carrier independent of signal's data pattern and feeding said harmonic frequency to a multi-phase translator and reference phase synchronizer, d) a second hard limiter means converting the input signal into a N-th phase rectangular wave PSKsignal, e) said digital multi-phase translator means responding to clock output of the harmonic clock regenerator and rectangular PSK signal output of second hard limiter for producing a binary parallel data, f) a frequency divider means dividing said N-th time harmonic frequency source into a serial data clock, g) a parallel to serial converter means converting said parallel data into a serial one with the application of data clock, h) a carrier detect means generating a one-shot signal during the preamble period to control the frequency divider and enable a reference phase synchronizer, and, i) said reference phase synchronizer means extracting the reference phase signal from the preamble sync pattern and the distributed sone word in data field to synchronize said digital multi-phase translator and frequency divider.

6. A multi-phase PSK demodulator of claim 5 wherein: a) said distributed syne word in a data field structure comprises many syne symbols and an asymmetric data pattern, and, b) said data field structure comprises a frame structure which has X sub4rames and each sub-frame hasY modulated symbols wide with a sync symbol atthe end.

7. A multi-phase PSK demodulator of claim 5 wherein: a) said reference phase synchronizer means comprises of shift register and leader pattern correlatorto sort the sync pattern during preamble period and comprises a distributed sone word correlator and reframing circuit to sort said distributed sync word during data field, and, b) said reference phase signal means comprises of the output of leader pattern correlator during preamble period and distributed sync word correlator output during data field to synchronize said multi-phase translator and frequency divider.

8. A multi-phase PSK demodulator of claim 5, or 7 wherein said refernece phase synchronizercomprises: a) said distributed sync word correlatorchecking said sync word at the end of a frame data, b) a reframe request signal line carrying a signal generated from said distributed sync word correlator requesting a reframe action at the reframe circuitfor anydetected sone word error (phase slip or misalignment), c) said reframe circuit responding to said reframe request signal from said distributed sync word correlator for searching a correct time slot of the distributed syne word, d) a reframe signal line carrying a signal generated at said correct time slot by the reframe circuit to reset the distributed sync word correlator and indirectly to synchronize the digital multi-phase translator and frequency divider, and, e) said distributed sone word correlator also being reset by the output of leader pattern correlator during preamble period.

9. A multi-phase PSK demodulator of claim 5, wherein said parallel to serial converter responding to a time multiplexing frame structure data input and a distributed sync reference phase signal for producing a time demultiplexed multi-channel serial data.

10. A multi-phase PSK demodulator of claim 1 or Swherein said frequency divider, translator, parallel to serial converter, and reference phase synchronizer means is substituted by a processor type elementwhich itself is a logic means.

11. A multi-phase PSK demodulator of claim 5 wherein said harmonic clock regenerator means comprises a non-linear phase locked loop comprising phases only during positive edges of said clock tracking source applied to inputfurtherincluding: a) a delay means delaying the inputsignal's edge of half phase segment (i.e.

1 2Nf second, f is the modulation rate), b) a synchronous latch means storing the input signal's positive edge and being reset by a pulse generated from a sampling latch, c) a sampling latch means accepting a clock signal feedback from a voltage controlled oscillator outputto generate a pulse at its output after a positive edge latched by said synchronous latch, d) a sequential phase/frequency detector means comparing positive edges' phases from said delay device output and sampling latch, e) a low pass filter means filtering said sequential phase/frequency detector output into a direct current signal, and, f) said voltage controlled oscillator means accepting said low pass filter output to generate afrequency source of N-f Hz at its output and requiring thefrequencysource of maximum limited to lessthan 2Nf Hz and minimum limited to more than 0.5Nf Hz.

12. A method of achieving reference phase synchronization without retransmission after a phase slip or misalignment at a multi-phase PSK demodulator, comprising inputting a multi-phase PSK modulated signal source containing a distributed syne word, correlating and verifying the distributed sone word for a proper reference phase position by a distributed sync word correlator, responding to a request of reframing due to a phase slip or misalignment indicated by the distributed syne word correlator as to resort a correct time slot of the distributed syne wo rd by a reframe circuit, and resetting the syne word word correlatorand synchronizing internal operations of said multi-phase PSK demodulator at said correct time slot provided by the reframe circuit to complete the reference phase synchronization.

13. A multi-phase PSK demodulator of claim 1 or5wherein said input signal being encoded in a waythat: 1) the passband bandwidth and high sidelopes of said input signal is minimized to suit for a magnetic recording media or a narrow band channel, 2) the coding restricts the maximum time distance between two transitions within a modulated symbol or two adjacent modulated symbols to prevent a creation of a low frequency waveform among symbols, and, 3) the waveform between symbols have to be adapted to have a smooth zero crossing and to minimize the highsidelopes.