GB2189084A

GB2189084A - Integrated circuit packaging

Info

Publication number: GB2189084A
Application number: GB08608696A
Authority: GB
Inventors: John Michael Young; Graeme Kenneth Barker
Original assignee: STC PLC
Current assignee: STC PLC
Priority date: 1986-04-10
Filing date: 1986-04-10
Publication date: 1987-10-14
Also published as: GB2189084B; GB8608696D0

Abstract

A package assembly for a plurality of integrated circuits, e.g. GaAs circuits, comprises a multilayer circuit board (11) having openings (17) for receiving the circuit chips (18). The circuits are connected to an upper metallisation level (16a), interconnections being provided by one or more lower levels (16b). Connections between levels are effected via plated through holes passing through openings in intervening ground planes (15). <IMAGE>

Description

SPECIFICATION Integrated circuit packaging This invention relates to a package assembly for integrated circuits and to a method of fabricating the assembly.

Small and medium scale gallium arsenide integrated circuits are now available which are capable of operation into the gigahertz frequency range. The packaging of these devices, however, remains a problem. In the gigahertz region signal wavelengths become comparable with package dimensions, and reflections from impedance discontinuities, bond wires and package capacitances degrade performances. Also every individual chip has to incorporate an output buffer to drive the package capacitances and the long transmission lines to the next packaged chip. This buffer circuit can be very wasteful of power and increases the overall chip size. Certain microwave packages for discrete devices have been developed, but the only existing packages for multipin devices are those for silicon chips.No consideration has been given to the characteristic impedance of the connection through these packages and the pad capacitances tend to be too high for circuits operating above about 1 GHz.

The object of the present invention is to minimise or to overcome this disadvantage.

According to one aspect of the invention there is provided a package assembly incorporating a plurality of integrated circuits, the assembly including a multilayer circuit board having openings each for receiving an integrated circuit, a plurality of metallisation levels, and ground planes one for each said level, wherein interconnections between said levels are provided via openings in the ground planes.

According to another aspect of the invention there is provided a method of fabricating a package assembly for a plurality of integrated circuits, the method including providing a stack of insulating laminer layers each having a ground plane on one surface and a metallisation pattern providing interconnections between the metallisation patterns of the stack via openings in the ground plane between the patterns, providing openings in the assembly each for receiving an integrated circuit, and providing contacts between the circuits and one or more said metallisation patterns.

An embodiment of the invention will now be described with reference to the accompanying drawings in which: Fig. 1 is a schematic cross-sectional view of the circuit package assembly, and Figs. 2 to 4 illustrate successive stages in the manufacture of the assembly of Fig. 1.

Referring to Fig. 1, the package assembly comprises a multilayer circuit board 11 mounted e.g. on a ceramic flat pack or heat sink 12 and including a plurality of stacked insulator levels 13 provided with an adhesive layer 14 therebetween.

Each insulator level has a conductive ground plane 1 5a, 1 5b on its lower surface and a metallisation, e.g. copper, pattern 16a, 16b, disposed on its upper surface. The adhesive 14 provides electrical isolation between the metallisation 16b and the adjacent ground plane 1 5a. Openings 17 are provided in the stack each for receiving an integrated circuit chip 18.

If the chips are fixed to the underlying heat sink by epoxy materials, the whole system will be repairable in that individual chips may be removed and replaced. Repairability is advantageous in view of the value of the individual chips that will be used in such a module.

Contact between the multilayer package, chip and ceramic flat pack may be effected by short gold wire bonds 19. Bonds to the chip are made on the top level tracks 16a which provide a microstrip transmission medium. Connection to the second level buried tracks is by through-hole plates via holes 20, which run through a clearance hole 21 in the microstrip groundplane 1 5a. The second level tracks provide a stripline transmission medium, together with the upper groundplane 15a the lower groundplane 1 5b and the dielectric layers. The microstrip and the stripline dielectric material may be polyimide (r = 3.5) which is bonded to the copper tracks and groundplanes using the adhesive 14.Due to the small thickness of the dielectrics required the adhesive thickness is approximately equal to that of the dielectric 13 but its dielectric constant is of similar magnitude, so the total dielectric thickness is that of the polyimide and the adhesive. The thickness of the layers 13 and 14 will of course depend on the number of layers and on the chip dimensions. Typically the layers 13 and 14 are between 20 and 30 microns thick.

Via holes are opened through the dielectric using a laser. At the point where the chip will be placed a large via hole is opened right through the multilayer package so that the chip may be bonded to a good ground and heatsink.

The metallisation track width may be approximately 100 microns which corresponds to the size of bondpads on GaAs chips. With this track width the impedance of lines achieved is approximately 50 ohms, but as the maximum length of interconnect at frequencies in the low gigahertz region is much less than A/8 the impedance of the track is not of overriding importance. Overall multilayer substrate size is typically Smm x Smm which allows the assembly to be bonded into a ceramic multipin flat-pack.

Referring now to Figs. 2 to 4, a sequence of process steps for manufacturing the multilayer assembly will be described below. The starting substrate is a laminate of copper/adhesive/ polyimide/adhesive and copper to which more layers of dielectric and copper will be added during the process.

1. Print and etch both sides of board 20 using a mask to provide alignment marks 21 for following steps (Fig. 2).

2. Print and etch lower side with 'window 22 in buried groundplane' mask.

3. Print and etch lower side with 'chip well' mask to define window 23.

4. Bond another layer 31 of adhesive/polyimide/ adhesive and copper to the lower surface of the treated board (Fig. 4).

5. Print and etch both sides of the assembly with 'top level/buried track window' mask.

6. Using laser, generate via holes 32 at window position.

7. Print and etch new lower surface with 'chip well' mask to define window 33 in register with window 23.

8. Electroless copper plate thin layer 34 over whole board to metallize through via holes.

9. Print and selectively plate copper with buried tracks mask and etch.

10. Repeat step 4 but apply first level of adhesive in double thickness to compensate for track depth (Fig. 4).

11. Print and etch top side with 'top level via' and lower side with 'bottom level groundplane via' mask.

12. Repeat step 6.

13. Print and etch both sides with 'chip well' mask.

14. Open chip well holes 40.

15. Repeat step 8.

16. Print and plate copper/gold with 'top level track' mask, and finish with copper etch.

The process described provides multilayer interconnect packages capable of accepting GaAs chips. The process is capable of expansion to incorporate larger numbers of chips on increasing numbers of layers whilst remaining adapted to mass production techniques.

The technique may be used in a wide range of applications, but it is of particular advantage for use in high frequency transmission systems.

Claims

1. A package assembly incorporating a plurality of integrated circuits, the assembly including a multilayer circuit board having openings each for receiving an integrated circuit, a plurality of metallisation levels, and ground planes one for each said level, wherein interconnections between said levels are provided via openings in the ground planes.

2. A package assembly incorporating a plurality of integrated circuits, the assembly including a housing, a multilayer circuit board comprising a stack of metallised insulating layers and supported on said housing and having a plurality of openings in each of which an integrated circuit chip is located, a first conductor pattern disposed on the surface of the circuit board and to which the integrated circuits are connected, a second conductor pattern, a first ground plane associated with the first conductor pattern, one or more further conductor patterns disposed below the first conductor pattern and ground plane, and further ground planes are associated with each said further pattern, wherein interconnections are provided between the conductor patterns via corresponding openings in the ground planes between those patterns.

3. A package assembly as claimed in claim 2, wherein at least some of the insulating layers comprise a polyimide.

4. A package assembly as claimed in claim 3, wherein at least one said insulating layer comprises an adhesive.

5. A package assembly as claimed in claim 2, 3 or 4, wherein the insulating layers are from 20 to 30 microns in thickness.

6. A package assembly as claimed in any one of the preceding claims, wherein the integrated circuits are gallium arsenide integrated circuits.

7. An integrated circuit package assembly substantially as described herein with reference to and as shown in the accompanying drawings.

8. A high frequency transmission system incorporating circuit package assemblies as claimed in any one of claims 1 to 7.

9. A method of fabricating a package assembly for a plurality of integrated circuits, the method including providing a stack of insulating laminer layers each having a ground plane on one surface and a metallisation pattern providing interconnections between the metallisation patterns of the stack via openings in the ground plane between the patterns, providing openings in the assembly each for receiving an integrated circuit, and providing contacts between the circuits and one or more said metallisation patterns.

10. A method of fabricating a circuit package assembly substantially as described herein with reference to and as shown in Figs. 2 to 4 of the accompanying drawings.