GB2198016A - Manchester decoders - Google Patents

Abstract

A Manchester decoder includes a majority conversion circuit 50 receiving a signal for decoding at an input 52, the circuit 50 providing a two-out-of three majority output to eliminate isolated single sample features in the input signal. The converted signal is supplied to a half-bit sample comparator 60 including a shift register 61, "late" and "early" pairs of samples being derived from the shift register 61 and tested for polarity coincidence in EX-NOR gates 62,63. A timing control circuit 70 including a five-bit counter 71 provides a sample signal at times dependent on the outputs of the gates 62,63 by virtue of the counter 71 being arranged to reset to a different count value depending on the output states of the gates 62,63. An output latch circuit 80 latches a sample derived from a stage of the shift register 61 as a data output signal, in response to the sample signal from the timing control circuit 70. The Manchester decoder is able to decode a highly distorted input signal (which may exhibit poor pulse rise-time and significant pulse droop) with edge jitter, in the presence of high levels of FM-receiver noise, by virtue of steering towards an optimum phase of signal determination unconstrained by the position of signal edges. <IMAGE>

Description

MANCHESTER DECODERS This invention relates to Manchester decoders, and in particular to Manchester decoders capable of decoding distorted input signals.

Manchester decoders can be used in a variety of applications requiring a balanced code, in other words a code having a balance of positive and negative signal elements resulting in a zero net DC component.

Typically, such balancing is required when the encoded signal is capacitively coupled at some stage along the signal path, for example at a transmitter modulation input.

Previously-proposed Manchester decoders are arranged to decode the coded signal by first locating and tracking the centre of each transition or edge in each bit period T, and then sampling the signal at times +0.25 T and -0.25 T relative to this central edge phase. The value of the bit is determined from either or both of these samples.

However, in the situation where the coded signal is derived from a non-optimal FM-transmitter, which may introduce undesirable pulse-shape distortions such as poor pulse rise-time and significant pulse droop, and which may also introduce edge jitter, for example due to the characteristics of asynchronous line-modems, performance of such a Manchester decoder will be degraded because the determination of the central edge phase is impaired by pulse-shape distortions introduced in the transmitter, and also the central edge may be subject to jitter introduced at the transmitter by the asynchronous line-modems. Furthermore, in the presence of high levels of FM-receiver noise, namely at very poor signal levels, additive noise in the radio path and FM receiver will mask and disturb the edge phases.

According to the present invention there is provided a Manchester decoder comprising: storage means for temporarily storing samples of an input signal to be decoded, the stored samples including first, second and third pairs of samples, each pair being separated by a predetermined time interval, respective ones of the first pair having been sampled earlier than the corresponding ones of the second pair and respective ones of the third pair having been sampled later than the corresponding ones of the second pair; detecting means for detecting polarity coincidence between the first pair of samples to provide an "early" output signal in the event of such coincidence, and between the third pair of samples to provide a "late" output signal in the event of such coincidence;; timing control means responsive to the "early" and "late" output signals to control the timing at which a sample signal is generated; and output latch means responsive to the sample signal to latch one of the second pair of samples as a data output signal.

In a preferred embodiment of the invention, the input signal is sampled a significant number of times (typically sixteen times) per bit.

Majority gating is preferably used on the input signal to eliminate spurious single sample features, typically due to additive noise. The preferred decoder is arranged to steer towards an optimum phase for determination of bit values1 at which phase there is consistent Manchester representation for each bit. Once an operating phase has been established, the decoder ignores signal edges which, being subject to jitter, might otherwise disturb the acquisition of optimum phase.

The invention will now be described, by way of illustrative and nonlimiting example, with reference to the accompanying drawings, in which: Figure 1 is a circuit diagram of a Manchester decoder according to an embodiment of the invention; Figure 2 is a logic diagram illustrating timing control of the decoder shown in Figure 1.

Figure 3 shows timing control waveforms of the decoder shown in Figure 1; and Figure 4 is a more detailed circuit diagram of the decoder shown in Figure 1.

Referring to Figure 1, there is shown a Manchester decoder embodying the invention. The decoder is operative on a 512 b/s code with a clock rate of 8192 Hz and has fully synchronous operation.

A majority conversion circuit 50 is in the form of a shift register 51 with three stages "8" to "10", an input 52 for the signal to be decoded being applied to the first stage "8". The coded waveform, for example derived from an F.M demodulator, is sampled at 16 times bit-rate, positive values being coded "1" and negative values "0", and the resulting sampled signal is applied to the input 52. The shift register 51 also includes a clock input 53, and has parallel outputs to three AND gates 54 whose outputs are connected to an OR gate 55. The majority conversion circuit 50 is operative to eliminate spurious single sample features due to additive noise by majority gating each three sequential samples to provide a two-out-of-three majority output as described in more detail later.This is equivalent to a non-linear third order median filter.

The output of the OR gate 55, which constitutes the output of the majority conversion circuit 50 is connected to a half-bit sample comparator 60 comprising a 13 stage shift register 61 having stages "11" to "23", and two EX-NOR gates 62,63 connected to the shift register 61 which also includes a clock input 64. The EX-NOR gate 62 receives outputs from the stages "11" and "19" and the EX-NOR gate 63 receives outputs from the stages "13" and "21".The samples to be processed are present in the stages "12" and "20" (although, as will be described later, they are actually derived from the stages "15" and "23" three sample clock pulses later to allow time for phase adjustment), therefore the EX-NOR gate 62 receives "late" samples from the stages "1 1" and "19" to provide a late output L indicative of samples one sample later than the nominal sampling phase, whereas the EX-NOR gate 63 receives "early" samples from the stages "13" and "21" to provide an early output E indicative of samples one sample earlier than the nominal sampling phase. As will be explained later, these early and late outputs E and L are used to control the timing of the subsequent sampling.

it will be seen that the half-bit sample comparator 60 performs comparisons of samples spaced apart by 8 samples, and since the sampling is at 16 times bit-rate, this constitutes a half-bit comparison.

A timing control circuit 70 receives the late and early outputs L,E from the EX-NOR gates 62,63 for controlling the timing of a sample pulse which is used to select a particular pair of half-bit samples from the shiftregister 61 and to latch the sampled value until the next sample pulse. The timing control circuit 70 includes a 5-bit synchronous counter 71 including stages "0" to "4", a three-input AND gate 72 providing a load signal from the stages "2" to "4" and a four-input AND gate 73 providing the sample pulse from the stages "0" to "3". The counter 71 also includes a clock input 74.

As will be seen from the timing control logic diagram shown in Figure 2, the synchronous counter 71 covers the states 12 to 28. During the state 28, the counter 71 samples the early and late signals E,L and then synchronously resets to one of the states 12, 13, 14 or 15 depending on the phase analysis.

During the state 15, the sample pulse is generated as a result of "ones" being present in the stages "0" to "3" thereby enabling the AND gate 73. "Illegal" states of the counter 71 outside the range of allowable states 12 to 28 will immediately converge on to the correct sequence within one clock pulse, as a result of the counter logic. These "illegal" states will converge to the allowable states, as follows: 0 to 11 will converge to : 17 to 28 29 will converge to : 12 to 15 30 will converge to : 12 to 15 31 will converge to : 16 to 19.

The sample pulse from the timing control circuit 70 is fed to an output latch circuit 80 which also receives sample outputs from the stages "15" and "23" of the shift register 61 forming part of the half-bit sample comparator 60. As stated above, the outputs from the stages "15" and "23" represent the samples which are to be processed and are the sample values of the stages "12" and "20" delayed by three sample clock pulses. The output latch circuit 80 includes an output latch 81 having three stages "5" to "7" and a clock input 32, and an EX-OR gate 83 receiving he outputs from the stages "15" and "23" of the half-bit sample comparator 60.The output latch stage "5" receives and latches the output of the half-bit sample comparator stage "15" to provide a "data" output; the output latch stage "6" receives and latches the output of the EX-OR gate 83 to provide a "good" output indicative of valid decoding; and the output latch stage "7" receives and latches the sample pulse from the timing control circuit 70 to provide a "bit clock" output.

The operation of the decoder shown in Figure 1 will now be described with reference to the timing control waveforms A, B, C and D shown in Figure 3.

The 16 times bit-rate sampled signal for decoding is applied to the input 52 of the majority conversion circuit 50 in which a two-out-of-three majority conversion is performed on the samples. The effect of this is that a transition of the type "0,0,0,1,1,1" (or vice versa) will appear at the output in the same form but delayed by one sample. A single-sample feature, generally arising from noise, of the type "0,0,1,0,0" (or its inverse) will appear at the output as "0,0,0,0,0" (or its inverse) again delayed by one sample. In this way, only established features in the signal are preserved, ephemeral features are deemed to be due to noise and are eliminated.

After majority conversion in the circuit 50, the binary sequence passes to the shift register 61 of the half-bit sample comparator 60. The samples are compared at half-bit (namely 8 sample) spacing by the EX-NOR gates 62,63, the gate 62 providing a late output L derived from the stages "11" and "19", and the gate 63 providing an early output E derived from the stages "13" and "21". If either of the EX-NOR gates 62,63 shows a match, then this indicates a bad phase for decoding. Since the gates 62,63 effectively test the signal one sample before and after the nominal sampling phase, the outputs of the gates can be used to correct the decoding phase.

If both gates return zero outputs (indicative of dissimilar samples), then this indicates correct operation and the data continues to be sampled at the nominal sampling phase. If only the early gate 63 returns an output of one (indicative of identical samples), then the sampling point is to be retarded by one sample. If only the late gate 62 returns an output of one (indicative of identical samples), then the sampling point is to be advanced by one sample.

In either case, a "good" sampling phase will result. However, if both the gates 62,63 return an output of one, then the decoder is out of synchronisation and the sampling phase is to be advanced by two samples.

Phase-tracking therefore has a resolution of 1!16 bit, but phase-acquisition is more rapid, with a resolution of 1/8 bit.

The correction of the decoding phase is performed by the timing control circuit 70. The synchronous counter 71 covers the states between binary 12 (01100) and binary 28 (11100), as shown in Figure 2. At the state 28, the presence of "ones" in the stages "2", "3" and "4" causes the AND gate 72 to provide a load pulse which resets the counter 71 to any of states 12 to 15 depending on the particular permutation of the late and early outputs L,E from the EX-NOR gates 62,63. Thus correct operation (E=0, L=0) will cause the counter to reset to the state 13. With just an early match (E=l, L=0), the counter is reset to the state 12. With just a late match (E=0, L=l), the counter is reset to the state 14.If there is a match reflected by both early and late outputs (E=l, L=l), the counter is reset to the state 15. At the state 15, the presence of "ones" in the stages "0" to "3" causes the AND gate 73 to output the sample pulse. These phase adjustments take time to implement and therefore sampling by the half-bit sample comparator 60 is effectively delayed by three samples, by obtaining the sample outputs from the stages "its" and "23" rather than the stages "12" and "20", so as to allow time for the phase adjustments to take place. As previously mentioned, should the counter 71 take up an "illegal state" (namely any of the states 0 to 11 or 29 to 31), it will immediately converge on to the correct sequence.

Referring to Figure 3, the waveform A illustrates the situation in which operation is in-phase with the early and late outputs E,L both at zero.

The data output sampling period is every 16 samples, with the counter 71 resetting to the state 13 after the state 28. The waveform B represents late operation, the early output E being zero and the late output L being one, when it is necessary to advance the phase. This is achieved by reducing the data output sampling period to 15 samples, the counter 71 resetting to the state 14 after the state 28. The waveform C represents early operation, the early output E being one and the late output L being zero, and the required phase delay is achieved by increasing the data output sampling period to 17 samples, the counter 71 resetting to the state 12 after the state 28. The waveform D represents out-of-phase or out-of-synchronisation operation with both early and late outputs E,L being at one.In this case, the data output sampling period is reduced to 14 samples, the counter 71 resetting TO the state 15 after the state 28. Thus it will be apparent that variations in the data output sampling period are achieved by changing the count values of the counter 71, and this is done by changing the count state to which the counter resets once it has attained the maximum allowable count, namely 28.

As mentioned previously, the timing control circuit 70 generates a sample pulse when the counter 71 reaches the state 15. This sample pulse causes the output latch circuit 80 to latch the output of the stage "15" of the shift register 61 as the required decoded data, until the next sample pulse. Also, an indication of a "good" comparison is provided at the output of the latch stage "6", as long as the outputs of the stages "15" and "23" are dissimilar. In addition, the output latch circuit 80 provides a bit clock pulse, as shown in the waveforms A to D of Figure 3, starting on the trailing edge of the sample pulse, to provide an indication of the timing of the data output sampling.

Figure 4 shows a more detailed circuit arrangement of the decoder shown in Figure 1. The output latch stages "5" and "6" of the output latch circuit 80 are constituted by D-type flip-flops forming a synchronous latch enabled by the sample pulse to provide the latched data and "good" outputs.

The sample signal is also delayed by a further D-type flip-flop forming the stage "7", to provide the recovered bit clock pulse. The fully synchronous counter 71 (stages "0" to "4") is formed by conventional steering logic in the stages "0" to "3", with a load facility in the stages "0" to "1"; the stages "2" to "4" do not require a load facility. The stage "4" has modified steering to maintain a "one" output following a "zero" in the stages "2" or "3", or following a "one" output in both the stages "0" and "1". It can be seen from the timing control diagram of Figure 2 that this is sufficient both to maintain the correct state sequence and to terminate any "illegal" states of the counter.

The above-described Manchester decoder can be used with a nonoptimal FM-transmitter, since the decoder can compensate for undesirable pulse-shape distortions, such as poor pulse rise-time and significant pulse droop, and edge jitter, caused by the characteristics of asynchronous linemodems, which can be introduced by such a transmitter. The decoder is also able to decode the signal even in the presence of high levels of FM-receiver noise.

The improved decoder performance is obtained by sampling the signal a significant number of times (for example sixteen times, as described above) per bit. Spurious single sample features (for example, due to additive noise) are eliminated by majority gating (two-out-of three in the preferred embodiment) equivalent to a non-linear third-order median filter. The decoder is arranged to steer towards a "good" phase at which to determine the bit value, "good" phase being defined by consistent Manchester representation for each bit. The decoder therefore optimises its operating phase on a performance basis. In a low noise situation, the performance curve will plateau, resulting in a degree of phase latitude. In a high noise environment, the decoder will converge on the optimum phase as determined by pulse-shape distortion characteristics.Once an operating phase has been established, the decoder ignores signal edges which, being subject to jitter, might otherwise disturb the acquisition of the optimum phase.

The distortions to the pulse-shape, including distortions which are asymmetric about the signal transitions, particularly pulse droop, mean that the previously-proposed decoder operation of sampling at times +0.25 T and -0.25 T (T being the bit period) is no longer at the optimum phase. In the case of pulse droop, it is preferable to sample closer to the start of the pulse, but not too close otherwise poor pulse rise-times will affect the results. The optimum phase will vary according to the transmitter, the radio channel and the receiver characteristics. The above-described Manchester decoder is able to compensate for these transmission-reception deficiencies by steering towards the optimum phase available under each set of conditions, and then to determine bit values at that phase, ignoring any displaced signal edges such as may arise from jitter.

Claims (14)

1. A Manchester decoder comprising: storage means for temporarily storing samples of an input signal to be decoded, the stored samples including first, second and third pairs of samples, each pair being separated by a predetermined time interval, respective ones of the first pair having been sampled earlier than the corresponding ones of the second pair and respective ones of the third pair having been sampled later than the corresponding ones of the second pair; detecting means for detecting polarity coincidence between the first pair of samples to provide an "early" output signal in the event of such coincidence, and between the third pair of samples to provide a "late" output signal in the event of such coincidence;; timing control means responsive to the "early" and "late" output signals to control the timing at which a sample signal is generated; and output latch means responsive to the sample signal to latch one of the second pair of samples as a data output signal.

2. A Manchester decoder according to claim 1, wherein the predetermined time interval between each pair of samples is one half of the nominal bit period of the input signal.

3. A Manchester decoder according to claim 1 or claim 2, wherein respective samples of the first, second and third pairs of samples are each separated by a single sample period.

4. A Manchester decoder according to daim 1, claim 2 or claim 3, wherein the storage means is a shift register arranged to receive the input signal samples, and the first, second and third pairs of samples are derived from different stages of the shift register.

5. A Manchester decoder according to any one of the preceding claims, wherein the timing control means comprises a counter which is resettable to different count values depending on whether the "early" and/or "late" output signals are present.

6. A Manchester decoder according to claim 5, wherein the counter is a five-bit counter having allowable states 12 to 28, the counter being resettable from the state 28 to: the state 12 in the presence of the "early" output signal only; the state 13 in the absence of either the "early" or "late" output signals; the state 14 in the presence of the "late" output signal only; and the state 15 in the presence of both the "early" and "late" output signals.

7. A Manchester decoder according to claim 6, wherein the counter is arranged to generate the sample signal at the state 15.

8. A Manchester decoder according to claim 6 or claim 7, wherein all unallowable states of the counter are arranged to converge to the allowable states.

9. A Manchester decoder according to any one of claims 5 to S as dependent on claim 4, wherein the output latch means derives the second pair of samples from stages of the shift register selected to allow for a time delay caused by processing of the "early" and/or "late" signals by The counter to provide the sample signal.

10. A Manchester decoder according to any one of the preceding claims, comprising a majority conversion means arranged to receive the input signal samples and to supply to the storage means samples modified as a result of majority conversion.

11. A Manchester decoder according to claim 10, wherein the majority conversion means is operative on three sequential samples to provide an output dependent on the states of the majority of the three samples.

12. A Manchester decoder according to claim 10 or claim 11, wherein the majority conversion means comprises a further shift register and logic means operable on parallel outputs of the further shift register to provide the majority conversion.

13. A Manchester decoder according to any one of the preceding claims, wherein the output latch means is also responsive to the sample signal to provide a bit clock synchronised with transitions in the data output signal.

14. A Manchester decoder substantially as hereinbefore described with reference to the accompanying drawings.