GB2199696A

GB2199696A - Submerged storage plate memory cell

Info

Publication number: GB2199696A
Application number: GB08729623A
Authority: GB
Inventors: Daeje Chin
Original assignee: Samsung Semiconductor Inc
Current assignee: Samsung Semiconductor Inc
Priority date: 1987-01-06
Filing date: 1987-12-18
Publication date: 1988-07-13
Anticipated expiration: 2007-12-18
Also published as: KR880009439A; GB2199696B; JPS6453445A; DE3744375A1; FR2609350A1; GB8729623D0; NL8800007A

Description

1 1 1 7 0 1 SUBMERGED STORAGE PLATE MEMORY CELL 2199696 This invention

pertains to semiconductor memory devices, but more specifically to array storage capacitors of high-density dynamic random access memories.

In the data processing arts, there continuously exists a need for improving the design and operating performance of memory devices by increasing their data storage capacity and operating speed. Dynamic random access memories (DRAMs) have filled an ongoing need in the sense that, with each new generation of DRAMs, larger amounts of data have been stored in a relatively fixed sized memory chip. At present, one-megabit DRAM are currently commercially available and reseaLh efforts now are directed to four-megabit DRAMs, and higher. A typical one or four-megabit DRAM occupies about fifty to eighty square millimeters having an individual cell size of about ten to fifty square micrometers.

In an effort to increase the data storage capacity, e.g., packing density, efforts have been directed toward reducing the area occupied by the individual storage cells since they consume most of the available chip area. Limitations on the size of the data storage cell include minimum acceptable charge levels required by a sense amplifier for sensing charge susceptibility to thermal and radiation noise, and leakage. The attainment of four-megabit DRAMs has, for example, been made possible by employing trench-type storage capacitors in the storage arrays wherein trenches -are formed in the substrate to increase the effective surface area of the storage capacitor confined within a relatively small planar surface area of the substrate.

In the past, array storage capacitors were formed 2 totally on the surface of the substrate.

An article titled "A Substrate-Plate Trench-Capacitor (SPT) Memory Cell For Dynamic RAMs" by Lu et al., IEEE Journal of Solid State Circuits, Volume SC 21, No. 5, October 1986, as an example, shows a trench capacitor storage cell formed on a substrate including an epitaxial layer grown thereon. A polysilicon core, serving as one plate of a capacitor, extends from the surface of the substrate through the epitaxial layer into the p+ region of the substrate. The polysilicon core stores charge in response to a voltage applied thereto through an transfer transistor connected to the core. Charged storage is effected by interaction between the polysilicon core and the p+ region of the substrate in the lower portion of the trench. A capacitor dielectric separating the polysilicon core and the p+ substrate typically comprises silicon dioxide or the combination of silicon dioxide and silicon nitride, as known in the art. Such a construction has several advantages over planar type capacitors formed totally on the surface of the substrate in that it affords an increase in effective capacitive area for charge storage while being confined in a relatively small planar surface area on the surface of the silicon substrate.

A device constructed according to the Lu disclosure, however, may have potential disadvantages, such as a propensity for charge carrier punchthrough between trenches and among other components on the surface of the substrate. Punch-through tendencies limit the proximity of trenches to other trenches and components, which in turn, limit the packing density of the storage cells. Many prior art DRAMs also require epitaxial layers which entail additional processing time and costs in manufacturing.

Q 3 r, ii It is also known in the art to f orm a single trench storage plate capacitor without an epitaxial layer. This has been achieved by providing an n+ region around the trench in the body of the p-type silicon substrate.

The n+ region serves as a depletion region which stores charge in response to a voltage applied to a polysilicon plate and which is insulated therefrom and disposed internally of the trench. Since charged storage in this construction occurs outside the trench in the depletion region, the device has a tendency to be very leaky and unsuitable for high density packing of components on the semiconductor substrate.

Accordingly, it is an objective of the present invention to overcome the difficulties and drawbacks of prior art techn iques for achieving high density packing of components on a semiconductor substrate.

It is another objective of the present invention to attain the design of a one-transistor storage cell suitable for fabrication with acceptable processing yields which cell has a submerged storage plate that does not require an epitaxial layer.

It is yet a further objective of the present invention to provide a submerged storage plate one-transistor memory cell having high noise immunity.

It is also an objective of the present invention to provide a device design and structure which enable greater.production yield.

SUMMARY OF THE INVENTION

In accordance with the present invention, a one- transistor memory cell comprises a semiconductor substrate for carrying integrated circuit components thereon, a trench formed in the substrate f or f orming a capacitor region extending into the body of the 4 substrate, a recessed region of dopant disposed about the trench in the substrate thereby to form a conductive charge storage region around trench that is submerged in the body of the substrate, a conductive material serving as the capacitor storage plate disposed in the trench for effecting charged storage in response to a voltage potential applied thereto, and a dielectric material interposed between the conductive material and the charged storage region.

In a preferred structure, the submerged storage cell cooperates with a transfer transistor in a onetransistor memory cell of a dynamic random access memory. It comprises a substrate, a trench in the substrate for forming a capacitor region extending generally normal to the surface of th e substrate, a doped region recessed within the trench disposed in the body of the silicon substrate for defining a submerged charged storage region, a conductive polysilicon core filling the trench for forming one plate of the capacitor and for storing charge in response to a voltage applied thereto, a dielectric material interposed between the conductive and the charged storage region for serving as a capacitor insulator, and a conductive connector such as doped polysilicon for interconnecting the conductive core and the source region of the transfer transistor for enabling the passage of charge to and from the storage cell.

The recessed charge storage region is formed in successive steps wherein first a shallow trench is formed in which an oxide layer is formed, and then second a deeper trench is f ormed at the bottom of the shallow trench where the oxide layer is removed. Subsequently, dopants are introduced in the trench to dope the deeper trench while the remaining oxide mask on 1.

the side walls of the shallow trench prevent doping of the walls of the shallow trench thereby forming the recessed charged storage region.

other advantages, attributes and objectives will become more readily apparent upon review of the succeeding disclosure. taken in connection with the accompanying drawings. The invention though is pointed out with particularity by the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 depicts sectional view of a submerged storage cell of a preferred embodiment of the present invention; Figure 2 depicts a sectional view of a submerged storage capacitor of a preferred embodiment of the present invention embodied in a one- transistor memory cell; and Figures 3(a)-through 3(h) depict successive stages of fabrication of a submerged storage plate capacitor in a one-transistor memory cell of a preferred embodiment.

DESCRIPTION OF ILLUSTRATIVE EMBODIMENT Device Structure of p- or n-type semiconductor substrate. The following description of the illustrative embodiment is directed to an n-type substrate, but the principles and teachings herein are equally applicable to p-type substrates.

The capacitor is f ormed in a trench 11 of generally conical shape having an internal surf ace which extends normal to the plane of the surface 12 of the semiconductor substrate. Around the exterior of the trench 11 is placed a heavily doped p+ region 13 of boron formed by, preferably, a gas phase diffusion process. Region 13 may alternatively comprise a heavily f 1 6 doped n+ region of phosphorous. In each case the region 13 constitues one plate of the capacitor. A solid core of polysilicon material 14 deposited in the trench 11 constitutes the other conductive plate of the capacitor. The core 14 is separated from the capacitor region 13 in the silicon body by a thin dielectric layer 15 of silicon dioxide, or a composite structure of silicon nitride and silicon dioxide, as known in the art. Preferably, the dielectric layer 15 has a thickness of about 100 to 200 angstroms.

Because in many instances it is desirable to place certain components within a lightly doped well in the semiconductive body, a p-type well 16 is arranged in the surface of the body 10 of the silicon substrate.

Ordinarily, a number of other components, such as an access transistor or peripheral control circuit, might be located in the p-well 16 to take advantage of the particular properties it possesses. The submerged capacitor, however, is constituted by the region of the trench below the silicon surface 12. Charge storage occurs in the core material 14 in a deeper portion of the trench 19 due to the relatively high concentration of p+ type material of boron surrounding the trench in the p+ region 13 at this deeper location.

The trench 19 is formed in successive operations. In a first operation, a shallow trench is formed in p-well 16 of the substrate by a reactive-ion etching process. The shallow trench extends in the substrate approximately 1.5 microns. After forming the shallow portion of the trench, an oxide layer is deposited on its internal side walls and bottom. An anisotropic etching process is next used to etch away the bottom portion of the shallow portion of the trench leaving intact the oxide layer on the walls thereof as a mask to ll V, d i 7 5.

L)lock a subsequent impurity diffusion process. In a second step, a deeper trench of about 3.5 microns is etched in the bottom of the shallow trench. A heavily doped boron diffusion process infuses impurities in the walls of the deeper trench to attain a concentration level preferably above 1019 atoms per cm3 and junction depth of about 1.0 micrometer. The boron-doped region 13 constituting the capacitor storage region thus is submerged sufficiently below the surface 12 of the silicon substrate because the oxide layer in the shallow portion of the trench served as a mask during the boron diffusion process. Preferably, a gas-phase diffusion process is employed to perform the boron diffusion..

By virtue of this construction, charged storage occurs in the conductive core 14, which preferably comprises n+ doped polYsilicon, rather than in an inversion layer of the silicon body thereby to substantially reduce charge leakage and punch-through among trenches and other components on the substrate, and improve noise immunity due to alpha particle degradation and thermal excitation of electrons.

Further, it matters not whether the p-well 16 resides in the body of substrate because the heavy dose of impurities, e.g., boron or phosphorous, disposed about the lower portion of the trench defines the charge storage region.

Figure 2 depicts another embodiment of the present invention wherein a submerged storage plate capacitor is used in combination with a.transfer transistor in a one- transistor dynamic random access memory cell. In this instance, the storage cell extends through p-well 16 into the silicon body 10 so that the lower region 19b of the storage capacitor takes full advantage of the properties of the n-type substrate, while the transfer 8 is transistor (and/or other peripheral circuit) takes full advantage of the properties of the p-well 16.

In Fig. 2, the storage capacitor of the one-transistor memory cell is constructed similar to that described in connection with Fig. 1. It comprises conductive material 14 preferably composed of n+ doped polysilicon, trench formed by a shallow and wider portion 19a, and narrow and deeper portion 19b which extends through the p-well 16 into the body of the substrate 10. A thin capacitor dielectric 15 separates the conductive polysilicon core 14 from the heavily doped p+ region 13. The one-transistor memory cell also includes a transfer transistor comprising a gate 20, and source and drain regions 21 and 22 separating a channel region 23 immediately below the gate 20. A gate insulator 24 separates the transistor gate 20 and the channel region 23 to control the flow of current between the source and drain regions 21 and 22 in response to a control signal applied to the gate 20. To enable transfer of charge between the storage capacitor and the circuits utilizing the charge, a piece of conductive polysilicon 26 interconnects the core 14 and the source region 22 of the transistor. A layer of insulating material 28 covers and protects the various underlying layers on the semiconductor substrate. As conventionally known, various conductors, such as conductors 30, carry signals among the respective components on the semiconductor substrate. An electrical contact also couples the transistor control gate 20, but is not shown for the sake of clear illustration. Fig. 2 conveniently shows a two-dimensional slice in a three-dimensional structure to illustrate the submerged capacitor. Various channel stops, as conventionally known, separate respective components on the substrate surface of the substrate.

9 r il Advantageously, the heavily doped p+ region of boron cooperates with the p+ channel stop diffusion surrounding the trench walls to substantially minimize leakage current from the capacitor storage plate.

Further, because of the oxide mask in the shallow portion of the trench, the " n+ source drain region of the transistor is not affected while the p-well conductance is increased by orders of magnitude.

By the above construction, it is seen that epitaxial laye rs are totally eliminated thereby enabling substantial cost reduction, greater yield, and reduced manufacturing time in fabricating MOS semiconductor devices employing trench-type storage capacitors.

Ster)s of Fabrication Figures 3(a) through 3(h) depict various stages during the process ing a silicon wafer to make An embodiment of the present invention. A starting semiconductor wafer 30 comprises a lightly doped n-type or p-type substrate and includes p-wells 31 and 32 and an n-well 33 formed by a conventional process of diffusion or ion implantation. In practice, the base concentration of impurities in the substrate is approximately 1014 -atoms per cM3 P-wells 31 and 32, for example, have a concentration of 1016 atoms per CM3, whereas the n-well 33 has a concentration of approximately 1016 atoms per CM3.

A composite silicon nitride and silicon dioxide layer., 34 and 35 respectively, are deposited on a thin layer of silicon dioxide 36. After a photolithographic process, the oxide/nitride/oxide layers 34, 35 and 36 are etched to form a reactive-ion-etching (RIE) mask and the silicon substrate 10 is further etched to form trench 40 (Figure 3(b)). In the next stage as depicted in Figure 3(c), an oxide layer 42 is deposited or thermally grown on the surface of the body of the substrate 30 as well as inside the trench 40. The bottom portion 44 of the trench subsequently is removed by an RIE process after which a second deeper trench is formed as previously set forth.

Next, boron impurities are predeposited on the exposed surfaces of the trench 40 which are not covered by the oxide mask 42 thereby to form a p+ layer 46 as depicted in Figure 3(d). The p+ region 46 surrounds the external region of the trench 40 in the body 30 of the silicon substrate. Preferably, the first trench is about 1.5 microns in depth, whereas the second trench is about 3.5 microns in depth, for a total depth of about 5 microns. By virtue of the two-step trench etching process, the p+ region 46 is submerged silicon substrate 30. The junction depth of the region 46 with respect to the surfaces of the internal walls of the second RIE etched trench is approximately one micron and its surface concentration is about 1019 atoms per cm3 after all thermal cycles are completed.

In Figure 3(e), a dielectric storage layer 48 is formed on the internal surfaces of the trench 40, which subsequently is filled with an n+ doped polysilicon core which also overlies the top of the wafer 30. The dielectric layer 48 and doped conductive silicon 50 are formed by conventional processes well known in the art. The core stores the charge and serves as one plate of the submerged capacitor. The polysilicon material 50 is doped by an gas-phase diffusion. After polysilicon 50 above the nitride layer 34 is removed, field oxide regions 52 (Figure 3(f)) are grown after removal of the nitride layer 2 and oxide layer 3. Thereafter, a gate oxide layer 54 is thermally grown underneath a strip of z k t beneath the surface of the 11 t 1 rA, polysilicon material 56 which serves as the gate electrode of a field effect transistors disposed between source and drain regions 58 and 60. A layer of insulating oxide 62 covers the polysilicon gate 56 and the source and drain regions are formed by a conventional ion implantation process.

In its final construction, Figure 3(h) depicts a polycide interconnection layer 66 overlying an insulating layer 68 in order to pass charge to and from a storage cell. The core 50 of the submerged storage cell connects to the transfer transistor by way of a thin conductive polysilicon layer 64 defined by a photolithography process, or alternatively, by a silicide layer defined by a self-aligning technique involving sputtering, silicidation and etching of unreacted metal portions. A passiyation layer 70 overlies_various components disposed on the body of the semiconductor substrate 30.

In operation, the highly doped p+ region of boron 46 serves as a storage plate for the trench capacitor and also increases the conductance of the p-well 32. By virtue of the two-step formation process for doping the lower portion of the trench 40, the effective storage plate is submerged beneath the surface of the substrate 30 to attain the advantages described herein.

As it will be appreciated from the above that as the result of the present invention, a submerged storage plate capacitor is achieved useful for various integrated circuit devices, such as one transistor memory cells in a dynamic random access memory. It will be equally apparent and is contemplated that modifications and/or changes may be made to the illustrative embodiments without departing from the true scope and spirit of the invention. For example, 1 semiconductor substrates other than silicon may. be employed. Further, the submerged region may be heavily doped with a p-type or n-type impurity, boron and phosphorous being only exemplary. Moreover, the submerged charge storage region may be f ormed by other processes to achieve the same or similar result without departing from the scope of the invention. Accordingly, it is intended that the foregoing description and accompanying drawings are illustrative of the preferred embodiments only, not limiting, in that the true spirit and scope of the invention is determined by reference to the appended claims and their legal equivalent.

13

Claims

CLAIlds: is C.

1. In a dynamic random access memory including a semiconductor substrate having a first storage cell for storing a charge, and a transfer transistor for transferring charge with said storage cell wherein the transistor includes a gate, a source and a drain, said storage cell comprising: well means having a second impurity formed at a given.depth in the surface of the substrate; trench means extending through said well means and into said substrate for forming a capacitor region: recessed dopant means having said first impurity disposed below the surface of said substrate and about said trench means for defining a charge storage region in said capacitor region; conductive means disposed in said trench means for effecting the storage of charge in response to a voltage potential applied theretoli dielectric means interposed between said trench means and said conductive means functioning as a capacitor insulator; and means for interconnecting said conductive means and the transfer transistor to enable.the transistor of charge with said capacitor region.

2. In a dynamic random access memory including semiconductor substrate, a storage cell for storing charge, and a transfer transistor for transferring charge with said storage cell wherein the transistor includes a gate, a source and a drain, said storage cell comprising:

14 trench means for forming a capacitor region extending in a direction that is generally normal to the surface substrate, recessed dopant means disposed below the surface of said substrate and about said trench means for defining a charge storage region in said capacitor region; conductive means disposed in said trench means for effecting the storage of charge in response to a voltage potential applied thereto; dielectric means interposed between said trench means and said conductive means functioning as a capacitor insulator; and connection means for interconnecting said conductive means and the transistor for transferring charge with said capacitor region.

3. An MOS capacitor having a submerged storage region for storing an electrical charge, said capacitor comprising: a substrate, trench means forming a capacitor region extending in a direction that is generally normal to the surface of the substrate, recessed dopant means spaced from the surface of said substrate and about said trench means for defining a charge storage region in the substrate, conductive means disposed in said trench means for storing said electrical charge in response to a voltage potential applied thereto, and dielectric means interposed between said trench means and said conductive means for functioning as a capacitor insulator.

T.

1 e t

4. An MOS capacitor as recited in claim 3 wherein said recessed dopant means is formed in successive steps, a.first step being to form a shallow trench in the substrate and masking the walls thereof to inhibit infusion of dopants, and a second step being to f orm a deep trench and doping the walls thereby forming said recessed dopant means only in said deep trench.

5. An MOS capacitor as recited in claim 4 wherein said shallow trench has a larger cross-sectional area than said deep trench.

6. An MOS capacitor as recited in claim 3 wherein the substrate has a first impurity type and includes well means of a second impurity type disposed in the substr ate, and said trench means extends from the surface of the substrate through said well means and into the body of the substrate.

7. An MOS capacitor as recited in claim 6 wherein said f irst impurity is n-type and said second impurity is p-type.

8. An MOS capacitor as recited in claim 7 wherein said conductive means comprises doped polysilicon and said dopant means comprises boron.

9. An MOS capacitor as recited in claim 4 wherein the substrate has a first impurit type and includes well means of a second impurity type disposed in the substrate, and said trench means extends from the surface of the substrate through said well means and into the body of the substrate.

1 16

10. An MOS capacitor as recited in claim 9 wherein said f irst impurity in n-type and said second impurity is p-type.

11. An MOS capacitor as recited in claim 10 wherein said conductive means comprises doped polysilicon and said dopant means comprises boron.

12. In a dynamic random access memory including an n-type semiconductor substrate, a storage cell for storing a charge, and a transfer transistor for transferring charge with said storage cell wherein the transistor includes a gate, a source and a drain, said storage cell comprising: a pwell of p-type impurities disposed in the surface of the substrate, trench means for forming a capacitor region extending in a direction that is generally normal to the surface substrate, said trench means extending through said p-well and into the body of the n-type substrate, recessed dopant means disposed below the surface of said substrate and about said trench means for defining a charge storage region in said capacitor region, said recessed dopant means being formed in successive steps, a first step being to form a shallow trench and masking the walls thereof to inhibit infusion of dopants, and a second step being to form a deep trench and doping the internal surface thereof with a heavy conc entration of boron to define a + charge storage region, 1 t 17 conductive means composed of n+ doped polysilicon disposed in said trench means 'for storing charge therein in response to a voltage potential applied thereto; dielectric means interposed between said trench means and said conductive means for functioning as a capacitor insulator; and connection means comprising conductive polysilicon for interconnecting said conductive means and the transfer transistor for transferring charge with said capacitor region.

14 p.-bi-1,ed 29sea-, The Pa-e-, OffIce. SZt,' HOI:SE 66 71 High Holbor.-., 13ndor. WC1R 47F. Pw-ther cop2es maybe obtamed from Uhe Patent OMce. Saaes Branch, St Mary Cray. Orplngwrx. Kent BR5 3RD. PrMted by MuUplex tachWcrues It& St M&r_v Cray, Kent. Con. 1/87.

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