GB2201534A - Arithmetic assembly - Google Patents

Abstract

An arithmetic assembly comprises a number of summing devices (9, 10 Figs. 3, 5) arranged in series. Each summing device has two input ports (A, B) and two output ports (5, 6A) and is adapted to generate signals at its output ports representing respective bits of the sum of two single bit values represented by optical signals supplied to its input ports. The output ports (5, 6A) of the leading p devices (Fig. 5) are each connected to respective input ports (A, B) of the adjacent downstream device and the input ports of the leading device each receive, in use, respective optical signals representing in series the bits of two p bit values to be summed. A delay (11 Figs. 3, 5) is built into the path of the most significant bit between adjacent devices so that the least significant bit supplied to the input port (A) of each device is summed with the most significant bit of the previous sum generated by the corresponding leading device. With combination of signals at the B port of the second device (Fig. 5), two p-bit values may be added using two summing devices. In order to reduce the intensity of the signal relating to the most significant bit when two binary one values are summed, a Y-coupler (7) is positioned upstream of the output port (6A) to reduce the intensity by 50%. <IMAGE>

Description

ARITHMETIC ASSEMBLY The invention relates to an arithmetic assembly for use in summing signals representing p bit values.

Many arithmetic adders have been proposed in the past but these commonly make use of transistor type devices leading to complex arrangements and components, and relatively slow operation.

In accordance with one aspect of the present invention, an arithmetic assembly comprises p + 1 summing devices arranged in series, each summing device having two input ports and two output ports and being adapted to generate signals at its output ports representing the least significant and the most significant bits respectively of the sum of two single bit values represented by signals supplied to its input ports, whereby the input ports of the trailing p devices each receives signals related to the signals generated by respective output ports of the adjacent upstream device and the input ports of the leading device each receives, in use, respective signals representing in series corresponding bits of two p bit values to be summed; and control means for causing each of the trailing p devices to receive at one input port a signal representing the least significant bit of the sum generated by the adjacent upstream device together with a signal at the other input port representing the most signficant bit of the previous sum generated by the adjacent upstream device, the arrangement being such that the signal generated by one of the output ports of the last device represents in series-the bits defining the sum of the two p bit values.

This invention provides an arithmetic assembly which enables binary values represented by respective travelling waves to be summed simply by passing the waves through the assembly. This leads to the construction of very high speed devices.

Where the values are less than p bits they are made up to p bits with leading zeros.

The signals processed by each summing device could be generated in response to the signals from the output ports of the upstream device. This would allow changes in the type of signal (eg. optical or electrical) to be achieved.

Preferably, however, the summing devices are coupled together so that signals generated at the output ports of each. of the leading p devices are passed to the input ports of the respective adjacent downstream device.

The control means may comprise delay means provided in the path carrying the signal representing the most significant bit of the sum generated by all except the trailing device to impose a delay of one bit interval relatively to the path of the least significant bit.

This could be achieved in practice by constructing the path length for the most signficant bit signal to be larger than that for the least significant bit.

In accordance with a second aspect of the present invention, an arithmetic assembly comprises first and second summing devices arranged in series, each summing device having two input ports and two output ports and being adapted to generate signals at its output ports representing the least significant and the most significant bits respectively of the sum of two single bit values represented by signals supplied to its input ports, whereby the input ports of the first summing device receive, in use, respective signals representing in series corresponding bits of two p bit values to be summed, and wherein one input port of the second summing device is adapted to receive a signal representing the output from the least significant bit output port of the first summing device; summing means having two input ports and an output port and being adapted to generate signals at its output port representing the sum of values represented by signals received at its input ports, a signal representing this sum being fed to the other input port of the second device, and one input port of the summing means being adapted to receive a signal corresponding to the output of the most signficant bit output port of the second- device;; and control means for supplying to the other input port of the summing means a signal corresponding to the output generated at the most significant bit output port of the first device for the sum determined by the first device previous to the sum whose least signficant bit is received by the second device, the arrangement being such that the signal generated by the least signficant bit output port of the second device represents in series the bits defining the sum of the two p bit values supplied to the input ports of the first device.

With this aspect of the invention, binary representations of any length can be summed with just two summing devices. Furthermore, by interleaving binary representations in the form of digital pulse signals, very high steeds can be achieved.

As in the first case, the signals generated by-each summing device could be of a different type from the incoming signals.

Preferably, however, the least significant bit output port of the first device is coupled with the one input port of the second device and the most significant bit output port of the first device is coupled with the other input port of the summing means; and wherein the most significant bit output port of the second device is coupled with the one input port of the summing means and the output port of the summing means is coupled with the other input port of the second device.

The invention can be applied to signals at a wide variety of wavelengths. For example, binary values represented by electronic signals could be summed.

However, the invention is particularly applicable for use with optical signals. In either case different (usually binary) values may be represented by signals with different frequencies, phases or preferably intensities.

In the case of optical signals, each summing device preferably comprises a device based on that described in our copending British Patent Application No. 8625281 (Our Case A23536/GB). Such a device will comprise first and second optical waveguides connected between respective output and input ports of first and second coupling means, the first coupling means having two input ports and being adapted to sum optical signals received at the input ports to generate a single signal portions of which are coupled into its output ports in a predetermined coupling ratio, and the second coupling means having two output ports and being adapted to couple optical signals received at each input port into its output port in a predetermined coupling ratio, wherein the first and second waveguides define respective optical paths with substantially the same length, the waveguides being fabricated from materials which exhibit soliton effects when optical pulses at working intensities are injected into the waveguides whereby the portions of the optical signals coupled into the waveguides by the first coupling means will be phase shifted relatively to one another at the second coupling means after travelling along the waveguides.

In that earlier case, a single input port device is described and this can easily be modified for use with the present invention by coupling the "input port" with a pair of upstream input ports via a summing element such as an "optical tapered Y coupler". This is a device which has not yet been fabricated but which causes an input signal to switch between one of the two output ports in response to the intensity of the input signal.

Where the summing devices respond to the total intensity of the incoming signals, the assembly may further comprise compensating means for reducing the intensity of the signal generated by the device corresponding to the most significant bit of the sum for compatibility with the signal representing the least significant bit of the - sum. Alternatively, the compensating means could comprise means for boosting the intensity of the signal representing the least significant bit of the sum. This latter arrangement is less desirable since it would require a significant amount of power to be input to the assembly.

In the case of optical signals, the signal paths are preferably defined by optical waveguides such as optical fibres.

In this specification the term optical is intended to refer to that part of the electro-magnetic spectrum which is generally known as the visible region together with those parts of the infra-red and ultra-violet regions at each end of the visible region which are capable of being transmitted by dielectric optical waveguides such as optical fibres.

Two examples of optical arithmetic assemblies according to the invention will now be described with reference to the accompanying drawings, in which: Figure 1 illustrates a summing device; Figures 2a and 2b illustrate the variation in output power at each output port of the device relative to total input power for one combination of non-linearity and dispersion in the two waveguides of the summing device; Figure 3 illustrates one example of a one bit value (p = 1) arithmetic adder assembly having two summing devices similar to the device of Figure 1; Figure 4 illustrates a p bit arithmetic adder based on the Figure 3 example; and, Figure 5 illustrates a second example of an arithmetic adder assembly.

Figure 1 illustrates within a dashed line box a summing device which has at its input end a tapered Y coupler 3a which defines a pair of input ports A, B and an output port coupled with an optical path 12. The tapered Y coupler 3a has the property that an input signal of 1 unit in either A or B leads to a signal of 1 unit in 12; and, with suitable interferometric alignment of the relative phases, a signal of 1 unit in each of A and B leads to a signal of 2 units in 12. The path 12 is connected to the input port of a conventional 50:50 Y coupler 3b whose output ports are coupled to respective optical fibres 1, 2. The coupler 3b is adapted to split the signal in the path 12 equally into each of the fibres 1, 2. The signals in the fibres 1,2 are recombined at the output end of the device by an "X" coupler 4.This coupler is also adjusted to couple 50% of the signal on each fibre 1, 2 into each of its output ports 5, 6. A Y coupler 7 has its single input port coupled with the output port 6 and is adapted to couple 50% of the signal from the output port 6 into one output port 6A while the remaining 50% is coupled into its other output port 8 and discarded.

To understand the action of the summing device shown in Figure 1, consider the arrival of two optical pulses at the input ports A, B. The final output from each port 5, 6 depends on the relative optical phase of the pulses at the input ports A, B.

The lengths of the two arms 1, 2 must be chosen so that the optical path lengths (or flight times) are the same in both arms to within a fraction of the pulse duration distance so that the two pulses arrive in coincidence at the output coupler 4. However, two pulses arriving in coincidence would still have an arbitrary phase difference, due to sub wavelength differences in path length. This phase difference can be tuned by sub-wavelength adjustments to the'arm lengths.

The non-linearity in each fibre 1, 2 is a third order effect where the refractive index n depends on the light intensity through the formula n=n0 + n2 *I (1) where nO is the linear refractive index and n2 is the non-linear index of refraction which for silica is l.2*1022(m/V) 2 The propagation of pulse envelopes including this non-linearity in a fibre with negative group velocity dispersion is described by the Non-linear Schrodinger equation (NLS).

iuz + 1/2*utt +ulul2 = 0 (2) This is a normalised equation and there are transformations to take the units back to real units.

Here it is sufficient to point out that the normalised amplitude generated by a real pulse is proportional to (n2/k2)1/2 and the normalised distance, z, in the above is proportional to k2/T2*L where k2 is the dispersion, T is the pulse duration and L is the real distance. The NLS has soliton solutions of the initial form u(z=0,t) = N*sech(t) (3) with N integer. For all N(integer) the solitons have the property that the modulus of u returns to its original form every n/2 propagated. For N=1 the full solution is u(z,t) = exp(iz/2)*sech(t) (4) It is important to note in the above formula the phase factor exp(iz/2). This is an overall phase which is present in all solitons.That is for all solitons the solution can be written u(z,t) = exp(iz/2)*f(z,t) (5) where f(z,t) is periodic in z with period tor/2. It is this property of solitons which will be exploited in the device.

In Figure 1 the pulses representing corresponding bits of two p bit values are launched at A, B. The two arms L1 and L2 are chosen to have the same length (L1 = L2) but to have different non-linear coefficients, n2, or different coefficients of dispersion or combinations of these. These differences will mean that the pulses from Y coupler 3b will arrive at coupler 4 with different phases (see equation 4) where recombination will lead to interference depending on the relative phases.

The normalisation in the NLS is taken to apply to fibre 1. The ratio of dispersion in fibre 1 to that in fibre 2 is and the ratio of the non-linear refractive index coefficients is ss. Then if the pulse in fibre 1 is asech(t), the normalised pulse in fibre 2 is (a/ss)1/2a*sech(t). The soliton period in fibre 1 is it/2 and in fibre 2 is as/2, It should be remembered that these are the normalised pulses and the total energy in both arms is the same. Therefore when the pulses recombine at coupler 4 the pulses must be renormalised before adding. When both "a" and (a/B) / *a are integers pure solitons are launched in both arms 1,2. In this case the outputs from both arms are of the "sech" form, if the lengths of the arms correspond to an integer number of soliton periods for both launched solitons. In that case the normalised distance z=ml*r/2, where m1 = a*m and both m1 and m2 must be integers.

2 The device operates as follows. The arm length is chosen to fulfil the above condition for soliton periods in both arms. As the launched power is increased the threshold for generating solitons is reached, but the two emerging "sech" pulses will have different phase factors (foray1). If the output from fibre 1 entering the coupler 4, is A(t) and the output from fibre 2 is B(t), where A(t) and B(t) are the slowly varying envelopes of the carrier frequencies, then the outputs at ports 5 and 6 are given by #|A|+|B| + 2cos(#)Re(AB*) + 2sin(#)Im(AB*) dt (6) and # |A|+|B| + 2cos()Re(AB*) - 2sin()Im(AB*) dt (7) respectively, where all the arbitrary phase factors have been absorbed into a single angle, . This means that at a particular power level (when pure solitons are launched) we can switch all the power into one or other of the two arms by an appropriate choice of . At other power levels this will not be the case but periodically the exact soliton launch power will be reached and thus total switching will occur. It only remains to determine the switching characteristics at intermediate power levels.

Table 1 illustrates some possible choices of a and ss, and the required arm length for operation.

TABLE 1 a ss m1 m2 fibre length 1 1/4 1 1 n/2 4 1 4 1 2n 2 1 2 1 Ir The second-example (a=4, ss=1, etc) will be considered in detail. In this example the two arms 1, 2 have different dispersions but the same non-linear coefficients. This is a very practical situation since it is comparatively straightforward to fabricate fibres with different dispersions at the same wavelength. Table 2 shows the configuration TABLE 2 FIBRE 1 FIBRE 2 launched a*sech(t) 2*a*sech(t) i.e. 2*a*a input pulse output exp(i*s) exp(i(n/4+8) phase Thus if B is 3X/4 (added to arm 2), then the outputs are in phase when exact solitons occur in both arms i.e. for "a" integer.It should be pointed out that the input power is given in units for fibre 1 and since there is the same power in each arm it is convenient to use fibre 1 units for the total launched power at A i.e. twice the intensity in fibre 1.

Figures 2a and 2b, show the calcuated output characteristics of the two ports 5, 6 against the input power respectively. It can be seen that as expected for total input powers of 2 and 8 (i.e. a = 1 and 2) the input pulse is transmitted out of port 5 (i.e. the connection to port 5 is 100% transparent), but for input power of 4 (a = 22) almost all the power is transmitted out of port 6.

Now consider the case where the signals launched into the summing device to input ports A, B both represent binary 1. Such signals may be in the form of pulses with intensities of two units using the terminology defined above. (Binary zero is represented by zero units). These will be summed by Y coupler 3a to generate a signal of 4 units which is fed along path 12 to Y coupler 3b which splits the signal into two signals of 2 units fed along fibres 1,2. In that situation, a pulse with a total power of four units will be output from the port 6 of the X coupler 4 as shown in Figure 2b while no power will be coupled out of the port 5 (Figure 2a). The effect of the Y coupler 7 is to reduce the power output from the port 6 by a half so that the signal output from the port 6A has a value of two units corresponding to a value of binary 1.Thus it will be seen that the summing device shown in Figure 1 provides on its output ports 5, 6A the least significant and most significant bits respectively of the sum of the two single bit values supplied on the input ports A, B. The action of the summing device for different combinations of binary input is summarised in Table 3 set out below.

TABLE 3 Input Output A B 6A 5 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1 0 The device shown in Figure 1 is an example of the basic building block needed for a more generalised form of arithmetic adder. To form a single bit value (p = 1) binary adder, which gives as a series output the two bit binary sum of the two single bit input data from the same output port, it is necessary simply ta join two (p + 1) of the summing devices together as indicated by reference numerals 9, 10 (Figure 3) with a delay line 11 inserted between the output port 6A of the device 9 and the input port B2 of the device 10. The delay line 11 is chosen to impose a delay of exactly a one bit interval on the signal output from the port 6A. The output from the port 5 of the device 10 provides in series the two bits of the sum of the signals on the input ports A1,B1 of the device 9.

Although the Y coupler 7 has been shown as positioned within each device 9, 10, it could instead be positioned elsewhere in the path between the output port 6 of the adjacent X coupler 4 and the input port B of the next device.

To understand the operation of the assembly shown in Figure 3 consider once again the example previously described where binary values of one are input to both input ports of the summing device (summing device 9 in Figure 3). As previously explained, the signals output from the ports 5, 6A represent respectively the binary values 0 and 1. The binary value 0 from the output port 5 is fed directly to the input port A2 of the device 10 while the binary value 1 is delayed by the delay line 11.

Thus, when the binary value of 0 from the output port 5 arrives at the device 10 it will be summed with another binary value of 0 resulting in a signal being output from the port 5 of the device 10 also representing binary 0 (Figure 2a) since total input power to the device 10 is zero units. Subsequently, the signal representing binary 1 (two units) will arrive at the port B2 of the device 10 and will be summed with a 0 value signal on the port A2 since no further signal has arrived from the device 9. This will cause a signal representing binary 1 to be output from the port 5 of the device 10 (Figure 2a) since total input power to the device 10 is two units.

It will be seen that the series of signals binary 0 followed by binary 1 represents the sum of the original two binary values input to the device 9 in the order least significant bit, most significant bit.

The assembly shown in Figure 3 can be extended to make a p-bit binary adder (Figure 4), which gives the output at port 01 as the (p + 1) - bit binary sum of the two p-bit input data streams. This extended assembly will contain p + 1 of the summing devices and p delay lines, each delay corresponding to the bit interval.

Proof that the assembly performs this function follows by induction.

1) The device works for p=l, and the output is unchanged if a further basic device is added.

2) Let us assume that the adder, with p + 1 basic devices and p delay lines, works as a p-bit adder and gives the output as the (p + l)-bit binary sum, (cp+l for j = 1, p + 1), of the two input -streams (ap j, for j = l,p) and (bp j, for j = l,p). We then add a further basic device and delay line as in Figure 3. An inspection of the truth table for the addition of binary words of the form (a,ap j), (ss,bp j), where a, ss have values 0 or 1, then shows that this extended device works as an (p + 1) bit adder with the output of the (p + 2)-bit binary sum of the two inputs.

The device described above is suited for pipeline operation ie. performing a long uninterrupted sequence of additions on p-bit words from the two input ports A, B.

For example, for a soliton switch or device (Figure 1) with 56 fs pulses, the length of a single switch will be about 30 cm. Thus, a pulse would take about 1 ns to traverse the switch. A binary adder for a 32-bit-word would need 33 such switches and so a signal would take at least 33 ns to traverse the device. However, the bit rate is limited only by the pulse duration (ie. two consecutive pulses must not overlap) and a one ps bit interval would be sufficient to ensure adequate separation between pulses. Hence, the overall arithmetic unit would take 33 ns to make one addition, and 65 ns to make 1000 consecutive additions.

A second example of an arithmetic assembly is shown in Figure 5. This is identical to the assembly shown in Figure 3 except that the output port 6A of the second device 10 is fed back to one input port of a tapered Y coupler 13 whose other input port is connected to the output port 6A of the device 9. The output port of the Y coupler 13 is coupled with an input port B2 of the device 10 while the output port 5 of the device 9 is coupled with the other input port A2 of the device 10. The pathlength from the output ports 6A of device 9 to the input port B2 of device 10 is one bit interval longer than the pathlength frpm the output port 5 of the device 9 to the input port A2 of the device 10. The pathlength defined by the loop commencing at input port B2 of the device 10 via output port 6A and back to the input port B2 must be one bit interval.

The significant difference between the Figure 5 and Figure 3 examples is that the Figure 5 example can sum incoming words of any number of bits. Only two soliton switching devices are required.

This improvement results from the fact that the direction of switching by each device depends on the total input power so that two units of input power at either input A or input B (Figure 1) would switch the same way as one unit of input power at each port. In view of this, the truth table (Table 3) can be extended as follows: TABLE 4 Input Output A B 6A 5 2 0 1 0 0 2 1 0 An example of the operation of the device shown in Figure 5 will now be described with reference to Table 5 below.

TABLE 5 Device 9 Device 10 Step Input (A1) Output (5 ) Input (A2) Output (5 (B1) (6A) (B2 (6A) I 1 1 - 0 0 - - II 1 0 1 1 1 1 0 0 III 0 0 0 0 0 0 0 0 IV - - 0 1 - - 1 In this example, the binary number input to port A1 has the value 11 while the binary number input to the port B1 has the value 10. The signals representing these values may be- chosen as appropriate (cf Figures 2a and 2b).

In step I the least significant bits of each input binary number are applied to the device 9 which produces binary output digits 1, 0 on its output ports 5,6A respectively. In step II, the device 9 receives the most significant bits of each original binary number, which in this case are each binary 1 and produces output signals 0, 1 from its output ports 5, 6A respectively (cf. Table 3). In addition, during this step, the device 10 receives at its input ports a binary value 1 from the output port 5 of the device 9 and at its input port B2 a binary value 0. This produces a binary value 1 at its output 5 and a binary value of 0 at its output 6A which is fed back to the Y coupler 13.

In step III signals representing binary zero are applied to both input ports of the device 9 which produces signals representing binary zero at each of its output ports 5, 6A. At this stage, the device 10 receives at its input port A2 a signal representing binary zero corresponding to the output signal from the port 5 of the device 9 during step II, while the input port B2 also receives a signal representing binary zero corresponding to the sum of the fedback signal output previously by the output port 6A of the device 10 and a signal also representing binary zero output from the port 6A of the device 9 during step I and delayed by delay line 11. The two binary zero inputs to the ports A2, B2 result in binary zero outputs from the ports 5, 6A of the device 10 (see Table 3).

In step IV the input port A2 of the device 10 receives a signal representing binary zero output from the port 5 of the device 9 during step III while the input port B2 receives the sum of the previously output signal from the port 6A of the device 10 which is zero (see step III) and the signal output from the port 6A of the device 9 during step II (binary 1) resulting in a total input signal having a value binary 1. This results in an output signal representing binary 1 from the port 5 of the device 10 and a signal representing binary 0 from the port 6A.

It will be seen that the series of signals output from the port 5 of the device 10 101 represents the resultant of the sum of the two originally input binary numbers.

The proof that the device shown in Figure 5 can add numbers of any length follows by induction in an exactly similar manner to that described in relation to the Figure 3 example.

The device shown in Figure 5 can also achieve very high speeds. Consider a 56 fs pulse and a 30 cm length switch. This must have a bit interval of about 1 ns and hence in the Figure 5 design it will take about 34 ns to complete one addition on a 32-bit word. However, the high potential speed of the device can be accessed by making use of the very large amount of space between bits. Thus, instead of making different words consecutive in the bit stream, they can be interleaved.

As before, interleaved pulses could be placed one 'ps apart and therefore the Figure 5 device could make up to 1000 additions in parallel for the same amount of time as it would take for a single addition.

In both these devices, it is a very simple matter to subtract values by using the standard "2's complement minus 1" technique.

Typically, the summing devices 9, 10 will be coupled together with optical fibres or other optical waveguides.

Claims (13)

1. An arithmetic assembly comprising p + 1 summing devices arranged in series, each summing device having two input ports and two output ports and being adapted to generate signals at its output ports representing the least significant and the most significant bits respectively of the sum of two single bit values represented by signals supplied to its input ports, whereby the input ports of the trailing p devices each receives signals related to the signals generated by respective output ports of the adjacent upstream device and the input ports of the leading device each receives, in use, respective signals representing in series corresponding bits of two p bit values to be summed; and control means for causing each of the trailing p devices to receive at one input port a signal representing the least significant bit of the sum generated by the adjacent upstream device together with a signal at the other input port representing the most signficant bit of the previous sum generated by the adjacent upstream device, the arrangement being such that the signal generated by one of the output ports of the last device represents in series the bits defining the sum of the two p bit values.

2. An assembly according to claim 1, wherein the summing devices are coupled together so that signals generated at the output ports of each of the leading p devices are passed to the input ports of the respective adjacent downstream device.

3. An assembly according to claim 2, wherein the control means comprises delay means provided in the path carrying the signal representing the most significant bit of the sum generated by all except the trailing device to impose a delay of one bit interval relatively to the path of the least significant bit.

4. An arithmetic assembly comprising first and second summing devices arranged in series, each summing device having two input. ports and two output ports and being adapted to generate signals at its output ports representing the least significant and the most significant bits respectively of the sum of two single 'bit values represented by signals supplied to its input ports, whereby the input ports of the first summing device receive, in use, respective signals representing in series corresponding bits of two p bit values to be summed, and wherein one input port of the second summing device is adapted to receive a signal representing the 'output from the least significant bit output port of the first summing device; summing means having two input ports and an output port and being adapted to generate signals at its output port representing the sum of values represented by signals received at its input ports, a signal representing this sum being fed to the other input port of the second device, and one input port of the summing means being adapted to receive a signal corresponding to the output of the most signficant bit output port of the second device; and control means for supplying to the other input port of the summing means a signal corresponding to the output generated at the most significant bit output port of the first device for the sum determined by the first device previous to the sum whose least sign fi cant bit is received by the second device, the arrangement being such that the signal generated by the least signficant bit output port of the second device represents in series the bits defining the sum of the two p bit values supplied to the input. ports of the first device.

5. An assembly according to claim 4, wherein then least significant bit output port of the first device is coupled with the one input port of the second device and the most significant bit output port of the first device is coupled with the other input port of the summing means; and wherein the most significant bit output port of the second device is coupled with the one input port of the summing means and the output port of the summing means is coupled with the other input port of the second device.

6. An assembly according to claim 5, wherein the control means comprises delay means provided in the path carrying the signal representing the most significant bit of the sum generated by the first summing device to impose a delay of one bit interval relatively to the path of the least significant bit.

7. An assembly according to claim 5 or claim 6, wherein the signal path extending from the most significant bit output port of the second device, via the one input port of the summing means, the output port of the summing means, the other input port of the second device, and back to the most significant bit output port of the second summing device has a length defining one bit interval.

8. An assembly according to any of claims 4 to 7, wherein the truth table for the second device has the following form: Input 1 Input 2 Output 1 Output 2 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1 0 2 0 1 0 0 2 1 0

9. An assembly according to any of the preceding claims, wherein the summing devices are adapted to respond to the total intensity of the incoming signals, the assembly further comprising compensating means for reducing the intensity of the signal generated by the device corresponding to the most significant bit of the sum for compatibility with the signal representing the least significant bit of the sum.

10. An assembly according to any of the preceding claims, wherein the summing devices are adapted to respond to optical signals.

11. An assembly according to claim 10, when dependent on at least claim 4, wherein the summing means comprises a tapered Y coupler.

12. An assembly according to claim 10 or claim 11, wherein each summing device comprises first and second optical waveguides connected between respective output and input ports of first and second coupling means, the first coupling means having two input ports and being adapted to sum optical signals received at the input ports to generate a single signal portions of which are coupled into its output ports in a predetermined coupling ratio, and the second coupling means having two output ports and being adapted- to couple optical signals received at each input port into its output port in a predetermined coupling ratio, wherein the first and second waveguides define respective optical paths with substantially the same length, the waveguides being fabricated from materials which exhibit soliton effects when optical pulses at working intensities are injected into the waveguides whereby the portions of the optical signals coupled into the waveguides by the first coupling means will be phase shifted relatively to one another at the second coupling means after travelling along- the -waveguides.

13. An arithmetic assembly substantially as hereinbefore described with reference to either of the examples shown in the accompanying drawings.