GB2240202A - Copy protection for memory devices - Google Patents

Abstract

A memory device capable of storing data, the data having at least two logic states, has at least one specially encoded data area in which the logic state of the data is indeterminate. Apparatus for and a method of programming the memory device are also included within the present invention. These provide, 7, 8, for varying the duration and voltage of programming pulses to achieve the indeterminate state, as detected by a sampling procedure (Fig 2). Computer software to be protected checks for the presence of the indeterminate data in the memory device. <IMAGE>

Description

COPY PRaI ECIION FOR MEMORY D1DVICES This invention relates to copy protection of memory devices.

The making of unauthorised copies of software contained in memory devices, usually known as pirating, is one of the largest problems presently facing the computer industry. Numerous attempts have been made to provide copy protection for memory devices.

One method of providing copy protection is to provide additional hardware that provides suitably coded responses to queries by the software as it is running. This has disadvantages as additional hardware is required which is not only expensive, but can also be impractical as the user may wish to have a number of copy protected programs resident in the computer system. Accommodation of the additional hardware can therefore be difficult.

Another copy protection device is an integrated circuit device arrangement which comprises first and second devices mounted one over the other on a substrate that provides a coupling between the devices. The first device acts as a standard memory device wherein the second device, known as a PAL (program array logic), is operable to switch the outputs of the first device only upon the application of a certain code. This has disadvantages as a new integrated circuit device arrangement is required to be made and the ensuing copy protection cannot be applied to standard memory devices.

Furthermore space in electronic devices is usually at a premium and surface mount technology is often used. The use of the second device increases the height of the integrated circuit device which can be undesirable in some situations.

Another device capable of providing copy protection for memory devices is the keyed-access EPROM or KEPROM. Two such devices are needed to effect a protected system.Before the operational code and/or data stored on a EPROM can be accessed, an authentication handshake is required to pass between the two devices to 'unlock' the storage area of the device containing the operational code and/or data. A programmable delay counter within one of the KEPROMs slows attempts to break the code of the authenticated handshake. This system requires a separate hardware component as well as specialised components and cannot be utilised with standard EPROMs.

It will be desirable if there could be provided a copy protection system which does not require additional hardware to be incorporated into the system and can be used on existing standard memory devices.

Memory devices are used in a wide variety of applications and are usually used to store pure data and/or operational code for microprocessors, microcomputers, computers or digital systems. Memory devices can be a separate or an integral part of the microcomputer or microprocessor system. In this specification, reference shall be made to memories which are programmable types that retain data without the application of power.

These include semiconductor devices, magnetic media or optical media.

It should be appreciated however that the present invention could apply to other memory devices.

Some devices that this invention is applicable to include ultra-violet erasable programmable read only memories (EPROMs), one time programmable read only memories (OTP ROMs), electrically erasable programmable read only memories (EEPROMs), non-volatile random access memories (NOV RAMs) and microprocessors and microcomputers with any of the above types of memories incorporated as an integral part.

Discussion of memory devices shall now be restricted to semiconductor devices although the principles of the present invention can apply to other memory devices existing and in the future including optical, magnetic and read/write molecular devices.

Usually memory devices are used or designed for the storage of digital data, often in binary form. Data stored in binary form is in either one of two logic states commonly designated by '1' or '0'. The user is concerned to ensure that the two states are clearly defined and distinct from each other. Data is usually stored as a quantity of charge embedded in the memory device. For instance zero charge or a charge below a particular logic threshold is designated as the '1' state and a full charge or a charge above the designated logic threshold is designated as the '0' state.

The term logic threshold is defined herein as the conditions on a memory device at which the logic state is indeterminate.

The present invention can also be applied to multi-state logic systems as well, wherein there may be more than just two logic states, each represented by a different quanta of charge.

The quantity of charge stored is controlled by the duration and magnitude of applied programming voltages. The decision threshold for the logic states (logic threshold) is subject to variability due to a number factors such as electronic noise, temperature change, humidity and device voltage supply change.

It is an object of the present invention to provide both apparatus and a method which addresses the above issues.

Further objects and advantages of the present invention will become apparent from the following description which is given by way of example.

SUMMARY OF THE INVENTION According to one aspect of the present invention there is provided a memory device capable of storing data, the data having at least two logic states, wherein the memory device has at least one specially encoded data area in which the logic state of the data is indeterminate.

BRIEF DESCRIPTION OF TIE INVENTION The logic state of a bit which is programmed in accordance with the present invention at the logic state threshold level will vary according to such external parameters included but not limited to electrical noise, temperature change, humidity or device voltage supply change. Thus, when the contents of the memory device is copied in the usual way, each copy will differ according to the external parameters present when the copying is taking place. The copies themselves will not have indeterminate logic states as these will not have been programmed by apparatus operating in accordance with the present invention. The copies will instead have defined logic states as read at the time of copying the original memory device.

The copier will not immediately be aware that he has unsuccessfully tried to copy the memory device, unless the copier is sufficiently astute to notice that the checksum (CHKSUM) is different for each copy.

Problems occur for the copier when the operational software in the memory device is running. Within the operational software there may be routines which check the addresses which were originally programmed with indeterminate logic states and act accordingly. For instance, if the data detected from the addresses where the indeterminate logic states are expected is constant, then the operational software causes appropriate action to be taken. Appropriate action may also be taken if indeterminate data is found where constant data is expected. The action may be to render the use of the system to which the memory device is attached nonfunctional. Alternatively some other indication that unauthorised copying has been detected may be given - perhaps a warning. The appropriate action may be to cause the operation of the software to gradually break down over a period of time. The program will operate as normal if the indeterminate logic states are found in the expected format.

In some cases the operational code can check the actual format of the specially coded data areas as well as just determining whether the data logic state is indeterminate.

Although it may theoretically be possible for an unauthorised copier to work through the operational code and identify the checking routine or the indeterminate logic state addresses, the interlocking of the checking routine with the rest of the software by an innovative programmer would render this task extremely difficult to achieve.

The operational code may in some embodiments not be within the memory device itself but in the computer system or in another memory device.

It becomes apparent that the present invention has an advantage over the prior art in that it uses standard memory devices and does not usually require additional hardware to be incorporated into the system.

One embodiment of the present invention provides apparatus which can program areas of a memory device at the logic threshold value. A typical EPROM programmer comprises a central processing unit (CPU), read only memory (ROM) and random access memory (RAM). The ROM and RAM are used for calculations, data manipulation and general microprocessor execution requirements. A separate block of RAM is set aside for data storage to buffer data to be programmed into the memory device. The data to be programmed into the memory device is loaded into the data buffer via either a serial or parallel data link connected to a host computer. Alternatively the data may be loaded from a preprogrammed device installed in the programmer itself. The programmer may also be controlled via a serial communications port connected to either a terminal or host computer.

One embodiment of the present invention provides an encoder which has the above features as well as the ability to only program specific data areas or address locations or even specific bits within a single address location in the memory device at a logic threshold value. These data areas may be in the operational code and/or in the normal data areas. To achieve this, the encoder may have full control over the programming time.

Alternatively the encoder may have control over the programming voltage level. In some embodiments the encoder may have control over the programming time and programming voltage level. In addition to this, the software associated with the encoder may have the ability to change the data applied to the memory device during the programming of an address location, which also effectively results in another means by which the programming duration of a location may be varied.

The programming characteristics of memory devices vary from batch to batch and between different manufacturers. Thus, the logic threshold will differ for each memory device. The threshold characteristics may be apparent from manufacturers' specifications. As an alternative to relying on the manufacturers' specifications, the applicants have devised an algorithm which can be used to ensure accurate programming of many suitable memory devices by determining their particular threshold characteristics through the variation of parameters on the memory device..

In one embodiment of the present invention the encoder tests a small specified block of memory in the memory device to determine the optimum programming characteristics to produce indeterminate bits with respect to program voltage and program time. This is achieved by incrementally programming sample address locations by using a very short effective program pulse width, up to the point where the logic state of the bits become indeterminate. In order to gain greater control, should the incremental program pulse width be deemed too coarse, the program voltage may also have to be varied because as when the programming voltage is reduced, longer pulses will be required to program locations.

The encoder then starts the test routine on another area of memory until an indeterminate state is produced. Alternatively the block of memory can be reprogrammed. Standard statistical methods are then used to obtain the optimum programming characteristics from the sample locations already programmed.

A method of programming the memory device may include adjusting the range of programming pulses in either time and/or voltage so that the specially encoded data area has sufficient span of stored charges to ensure that when the device temperature, supply voltage, or other operational parameters change or the device ages or memory cells lose charge, there will continue to be data of an indeterminate logic state when the specially encoded data area is sampled.

The addresses on the memory device which are programmed with indeterminate logic states may be scattered throughout the memory device. Single bits only within an address may also be indeterminately programmed wherein the rest of the address may be programmed in a definite logic state. The data addresses for the specially encoded data can in some instances be determined by an encryption algorithm which has a particular starting seed or key. While the algorithm may be known to the users of the memory device, the seed or key will not, thus adding a further element of copy protection.

The present invention not only provides a memory device and apparatus and method for programming the memory device but also a computer system which includes the memory device. In one embodiment the computer system may contain the operational code and include a memory device with some data in indeterminate logic states. The term computer system should be interpreted in its broadest possible sense and be seen to cover all systems that operate on logic instructions.

Aspects of the present invention will now be discussed by example only with reference to the accompanying drawings in which: BRIEF DESCRIPIION OF THE DRAWINGS: Figure 1: is a block diagram of an encoder in accordance with one embodiment of the present invention, and Figure 2: is a flow chart of one possible algorithm for use in determining logic threshold characteristics of a memory device.

DESCRIPTION OF PREFERRED EMBODIMENTS OF THIS INVENTION: With respect to Figure 1, there is illustrated the block components which form part of an encoder in accordance with one possible embodiment of the present invention.

The encoder includes a microprocessor 1, an encoder memory 2 and a data memory 3, all of which are standard components that can be found in standard EPROM programmers. The microprocessor 1 is a sixteen bit microprocessor, however it should be appreciated that a microprocessor of a different size can be used. The encoder memory 2 includes both RAM and ROM and is used for data manipulation, calculations and general microprocessor execution requirements. The data memory 3 is comprised of RAM and is merely a buffer for data to be programmed into the memory device 4. In most embodiments, it is envisaged that the memory device 4 would be a semi-conductor integrated circuit chip.

The microprocessor 1, encoder memory 2 and data memory 3 are all connected by communication linkages to an address/data and control bus 5. A communications controller 6 which has serial and/or parallel ports for interface to a host computer or terminal is also connected to the control bus 5.

Also linked to the control bus 5 is a programmable timer 7 and a programmable voltage reference 8. It is these two components 7 and 8 that enable certain addresses and bits on the memory device 4 to be programmed to a logic threshold value.

Also included in the encoder is a buffer/driver 9 and data latches/buffer 10.

Figure 2 illustrates one possible algorithm by which the encoder can be operated. First, a small specified block of memory within the memory device is sampled. Initially each bit should read as logic state '1' and is not variable. Next a small programming pulse of a particular width (time) is sent to the bits which are resampled. If the logic state is not variable and has not changed from the original logic state, then the process of incrementing the programming pulse to the specified block of memory continues until there is a change. If an indeterminate logic state is reached, then by standard statistical methods the optimum programming characteristics are determined from identifying the parameters of pulse width and program voltage that lead to the indeterminate programming. If there is a definite logic change which is non-variable, then it is apparent that the program pulse widths used were too coarse to produce the required indeterminate programming. The program voltage is then reduced which means longer pulses will be required to program the locations.

A different area of memory is tested next and the procedure of sampling and incrementing the programming time is resumed until an indeterminate logic state is detected.

Aspects of the present invention have been discussed by way of example only and it should be appreciated that modifications and additions may be made thereto without departing from the scope thereof as defined in the appended claims.

Claims (21)

WHAT WE CLAIM IS:

1. A memory device capable of storing data, the data having at least two logic states, wherein the memory device has at least one specially encoded data area in which the logic state of the data is indeterminate.

2. A memory device as claimed in claim 1 wherein at least one of the specially encoded data areas is a bit within the data located at a particular address.

3. A memory device as claimed in either claim 1 or claim 2 wherein at least one of the specially encoded data areas is scattered throughout the normal data areas.

4. A memory device as claimed in any one of claims 1 to 3 wherein at least one of the specially encoded data areas is within the operational code.

5. A memory device as claimed in any one of claims 1 to 4 wherein the memory device contains operational code which, when executed, tests the specially encoded data areas.

6. A memory device as claimed in claim 5 wherein the operational code when executed causes appropriate action to be taken if an indeterminate logic state is not detected in the data areas the operational code expects an indeterminate logic state.

7. A memory device as claimed in either claim 5 or claim 6 wherein the operational code when executed causes appropriate action to be taken if a determinate logic state is not detected in the data areas the operational code expects a determinate logic state.

8. A computer system containing a memory device as claimed in any one of claims 1 to 7.

9. A computer system as claimed in claim 8 wherein the computer system contains operational code separate from the memory device which tests for the speciaily encoded data areas.

10. A method of programming a memory device capable of storing data which has at least two logic states, wherein at least one data area within the memory device is programmed so that the logic state of the data is indeterminate.

11. A method of determining the logic threshold state of a data area within a memory device characterised by the steps of: a) sampling a data area of the memory device, and b) programming the sampled data for a short duration, and c) sampling the data area to determine whether the logic state is indeterminate, and d) if the logic state is unchanged from that of step a), then steps b) and c) are repeated until an indeterminate state is reached.

12. A method of determining the logic threshold state of a memory device as claimed in claim 11 characterised by the further steps of: e) ascertaining if the logic state has changed and is not indeterminate, and if so, then f) reducing the programming voltage, and g) selecting an unprogrammed area of memory and applying steps a) to d) of claim 12 to same.

13. Apparatus for programming a memory device including means to vary parameters on the memory device which enables the memory device to be programmed with data in an indeterminate logic state.

14. Apparatus for programming a memory device as claimed in claim 13 including means to vary the programming time.

15. Apparatus for programming a memory device as claimed in either claim 13 or claim 14 including means to vary the input programming voltage.

16. Apparatus for programming a memory device as claimed in any one of claims 13 to 15 including means to make some data already programmed into the memory device indeterminate.

17. A method of programming a memory device as claimed in claim 9 including adjusting the range of programming pulses in either time and/or voltage so that the specially encoded data area has sufficient span of stored charges to ensure that when the device temperature, supply voltage, or other operational parameters change or the device ages or memory cells lose charge, there will continue to be data of an indeterminate logic state when the specially encoded data area is sampled.

18. A memory device substantially as herein described with reference to and as illustrated by the accompanying drawings.

19. A computer system substantially as herein described with reference to and as illustrated by the accompanying drawings.

20. A method of programming a memory device substantially as herein described with reference to and as illustrated by the accompanying drawings.

21. Apparatus for programming a memory device substantially as herein described with reference to and as illustrated by the accompanying drawings.