GB2247349A

GB2247349A - Method for fabricating MOS transistors

Info

Publication number: GB2247349A
Application number: GB9117195A
Authority: GB
Inventors: Kyoung-Tae Kim
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 1990-08-20
Filing date: 1991-08-08
Publication date: 1992-02-26
Also published as: GB9117195D0; ITRM910621A0; ITRM910621A1; FR2665980A1; IT1250463B; KR920005242A; DE4114166A1

Abstract

In a method for fabricating a transistor having the structure gate-insulator-semiconductor, a gate insulation layer 34 is formed on the surface of a semiconductor substrate 30 of a first conductivity type, in which a channel 32 having the first conductivity type or a second conductivity type is formed. Then, a first conductive layer 38 made of titanium nitride is formed on the surface of the gate insulation layer 34 followed by a second conductive layer 36 which has higher conductivity than the first conductive layer. The first and second conductive layers and gate insulation layer are then selectively etched and source and drain areas 40, 41 of the second conductivity type are formed by ion implantation or diffusion. <IMAGE>

Description

METHOD FOR FABRICATING A TRANSISTOR HAVING A STRUCTURE OF

GATE-INSULATOR-SEMICONDUCTOR The present invention relates to a method for fabricating a semiconductor device, and particularly, although not exclusively, to a method for fabricating a transistor having a gate- insu 1 ator-semiconductor structure (hereinafter, referred to as a gateinsulatorsemiconductor transistor).

Gate- insulator- semiconductor transistors are g enerally of the MOS (Metal Oxide Semiconductor) type, which is very useful in semiconductor integrated circuits. Active research is being currently conducted into fabricating such transistors having a gate- insulatorsemiconductor structure, with the aim of achieving better integration and higher performance.

In fabricating such gate- insul ator-semi conductor transistors, n' polycrystalline silicon is generally used. The n" polycrystalline silicon is formed by doping polycrystalline silicon with an impurity having an n type conductivity. However, where a gate- insulator- semiconductor transistor having a p-type region is formed on an n-type substrate, the n" polycrystalline silicon gate causes the channel to be buried.

FIG. 1 of the accompanying drawings shows a cross-sectional view of a conventional gate-insulator- semiconductor transistor with a p-type region and a buried channel. The transistor has a p-type ion-implanted region 3 where a p-type impurity is ion-implanted into an n-type semiconductor substrate 1. Source and drain areas 4 and 5 respectively are formed at each side of the p-type ion- implanted region 3. The buried channel 7 is formed between the p-type ion-implanted region 3 and the substrate 1.' An n"' polycrystalline silicon gate ii is disposed over the buried channel 7. An oxide layer 9 is formed between the buried channel 7 and n+ polycrystalline silicon gate 11, and an insulation layer 13 is coated over the substrate 1 and gate 11.

1 When the n+ polycrystalline silicon gate is formed over the n-type substrate, the transistor is formed with an absolute value of threshold voltage of around -1V to -2V which is much larger in magnitude than a desired magnitude of smaller than -1V, because the two semiconductor layers (the substrate 1 and the gate 11) each side of the insulation layer are both n-type so that there is no substantial difference between their respective work functions. Therefore, in order to operate the gateinsulator- s emi conductor transistor at a desired threshold voltage of a magnitude smaller than -1V, it is necessary to lower the magnitude of the absolute value of the threshold voltage by moving the threshold voltage towards a more positive value.

To fulfill the above desired condition, in conventional gate-insulatorsemiconductor transistors, a method f or ion-implanting boron into the substrate has been utilized. As a consequence, a p-n connection part is created at a distance from the surface of the substrate by the ion-implanted boron and phosphorus doping in the n type semiconductor substrate. Thus, when a voltage whose magnitude is of a greater value than the threshold voltage is applied to the gate, holes gather around the p-n connection part for forming the channel area 7.

The gate-insulator-semiconductor transistor having the buried-type channel as described above is very i 1 1 1! 1 1 i i 1 1 j I i 1 i j I 1 1 i i 1 1 1 1 sensitive to changes in fabrication process, so there have been problems in that it is difficult to control the threshold voltage, and punch- through phenomena occur quite easily. As a result, reductions in size of the transistors to achieve higher-integration has been limited.

To solve the problem, it has been proposed that the n' polycrystalline silicon gate should be replaced by a p' polycrystalline silicon gate, into which an impurity of a p-type conductivity is heavily doped.

FIG. 2 of the accompanying drawings shows a cross sectional view of a conventional gate-insulator- semiconductor transistor using a conventional p polycrystalline silicon gate. The transistor includes source and drain areas 22, 23 respectively disposed in an n-type semiconductor substrate 21, a channel area 25 between the source and drain areas 22, 23, a p polycrystalline silicon gate 28 over the channel area 25, a gate oxide layer 27 formed between the p' polycrystalline silicon gate 28 and the channel area 25, and an insulation layer 29 coated over the substrate 21.

In this case, where the gate of the gate-insulatorsemiconductor transistor is made of p"' polycrystalline silicon and the substrate thereof has n-type conductivity as illustrated in FIG. 2, the difference in work function between the gate and substrate is greater by one electron volt (eV) than in the case where an n+ polycrystalline silicon gate is provided on an n-type substrate. Thus the threshold voltage is more easily controlled in an enhancement mode.

J 1 1 - 4 However, if the gate insulation layer between the gate and the substrate is thin, i.e., in particular, if its thickness is below 20 nm, the boron in the gate passes through the thin gate insulation layer and diffuses into the channel area during heat treatment in the fabrication process. This causes the threshold voltage to become unstable, causing additional problems.

In another attempt to solve the problem associated" with the buried-type channel, it has been proposed that the conventional gate material be substituted for by a g ate material having a work function value of between approximately 4.1 electron volt (eV) and 5.2 eV; 4.1 eV, being the work function of n4' polycrystalline silicon, and approximately 5.2 eV being the work function of p+ polycrystalline silicon.

1 Specific metals, such as tungsten (W), cobalt (Co), titanium (Ti), have been used as these materials have 20 work functions meeting the aforementioned conditions. However, there is still a problem that such metals react with and destroy the thin gate insulation layer. This problem frequently leads to the failure of the entire transistor.

It is accordingly one object of the specific embodiments of the present invention to provide a method for fabricating a gate-insulatorsemiconductor transistor that is suitable for high-scale integration.

It is another object of the specific embodiments of the present invention to provide a method for fabricating a gate-insulator-semiconductor transistor in which a threshold voltage can be easily controlled.

1 1 1 i1 i 1 1, j 1 i i 1 i 1 i i 1 i i j 1 i 1 1 1: 1 1 i i j 1 i i i i i 1 1 i i It is a further object of the present invention to provide a gateinsu 1 ator- s em i conductor transistor having a gate electrode which is not reactive with a gate insulation layer and which provides improved conductivity.

According to one aspect of the present invention, there is provided a method for fabricating a transistor having a gate-insulator-semiconductor structure, said method comprising the steps of: forming a gate insulation layer on the surface of a. semiconductor substrate having a first conduct iv ity-type wherein a channel region having said first conductivity type or a second conductivity type is formed in or substantially at the surface of said substrate; forming a first conductive layer made of titanium nitride (TiN) on the surface of said gate insulation layer; and sequentially forming a gate electrode by selectively etching said first conductive layer and said gate insulation layer, and forming source and drain regions of a second conductivity type by way of ion implantation or diffusion.

Preferably, said first conductive layer has a thickness in the range 10 nanometers to 300 nanometers.

Preferably, said gate insulation layer is made of silicon oxide or silicon nitride, or a combination of said silicon oxide and said silicon nitride.

Preferably, said gate insulation layer has a thickness in the range 3.5 nanometers to 50 nanometers.

Preferably, the method further comprises a step of forming a second conductive layer after formation of said - 6 first conductive layer, said second conductive layer being of a material having a higher conductivity than a conductivity of said first conductive layer.

Preferably, said material of the second conductive layer is a metal or a silicide of a said metal.

Preferably, said metal has a melting point of above 1600 Kelvin.

is Said metal may include one or more of the following: tungsten (W), titanium (Ti), cobalt (Co), nickel (Ni), palladium (Pd), chromium (Cr), zirconium (Zr), tantalum (Ta), vanadium (V), hafnium (Hf).

Preferably, said second conductive layer has thickness in the range of 50 nanometers to 300 nanometers.

A structure of said source and drain areas may be one of the following:

a single structure; an LDD (lightly doped drain) structure; a DDD (doubly doped drain or doubly diffused drain) structure; or a combination of said single structure, LDD (lightly doped drain) structure and DDD (doubly doped drain or doubly diffused drain) structure.

According to a second aspect of the present invention there is provided a gate- insulator-semiconductor structure transistor having a semiconductor substrate, an insulation layer and a gate, wherein said gate includes a barrier material which acts as a physical barrier to a reaction 35 between a material of said gate and said insulation layer.

) i i 1 1 1 1 i 1 1 1 1 1 I - 7 Preferably, said barrier material has a work function of a value in the range 4.3 electron Volts to 4.8 electron Volts.

Preferably, said barrier material comprises titanium nitride (TiN).

Preferably, said barrier material has a thickness in the range 10 nanometers to 300 nanometers.

Said gate may further comprise a second conductive layer.

Preferably, said second conductive layer includes one or more of the following; tungsten(W), titanium(Ti), cobalt(Co), nickel(Ni), palladium(Pd), chromium(Cr), zirconium(Zr), tantalum(Ta), vanadium(V), hafnium(Hf).

Preferably, said second conductive layer is of thickness in the range 50 nanometers to 300 nanometers.

Preferably, said transistor has a gate insulation layer of thickness in the range 3.5 nanometers to 50 nanometers.

The invention includes a gate - insu lator- semiconductor structure transistor having a semiconductor substrate, an insulation layer and a gate, wherein said gate includes a barrier material which acts as a physical barrier to a reaction between a material of said gate and said insulation layer.

The invention includes a gate- insu 1 ator -semiconductor transistor of a substantially surface channel type.

-g- The invention also includes a single-layered gate electrode of titaninum nitride (TiN) which is formed by using said -titanium nitride as a gate material. The invention includes a two-layered gate electrode which is formed by disposing a high-melting-point metal or silicide of a highmelting-point metal, on a top surface of the titanium nitride.

The high melting point metal is preferably chosen from the following group: tungsten(W), titanium(Ti), cobalt(Co), nickel(Ni), palladium(Pd), chromium(Cr), zirconium(Zr), tantalum(Ta), vanadium(V), hafnium(Hf).

For a better understanding of the present invention is and to show how the same may be carried into ef f ect, reference will now be made, by way of example, to figures 3 and 4 of the accompanying diagrammatic drawings, in which:

Figure 3 is a cross sectional view of a gateinsu lator- semiconductor tfansistor according to a specific embodiment of the present invention; and Figures 4A and 4B show a fabrication process according to a specific method of the present invention, for fabrication of a gate-insulator-semiconductor transistor, for example, one as shown in Figure 3.

Referring to Figure 3 of the accompanying drawings, the gate - insulator-s emiconductor transistor has source and drain regions 40, 41 respectively, each having a second conductivity type and formed respectively on each of two sides of an impurity doped region 32. The region 32 is doped with an impurity f or controlling a threshold voltage of the transistor. The transistor is fabricated on a substrate 30 of a first conductivity type. A gate electrode 39 comprises a titanium nitride layer 38 and a i j! i 1 -1 Y.

1 i 1 i i i i 1 1 i 1 i i i j i i i i i i i 1 1 1 1 1 i 1 i I 1 i 1 1 i i i i i 1 layer 36 of a high-melting-point metal or a high-meltingpoint metal silicide, formed over a gate insulation layer 34 on an upper area of the impurity doped area 32. The gate insulation layer 34 is formed over the substrate 30, and an insulation layer 42 coats the substrate 30 and gate.

Referring to Figure 4A of the accompanying drawings, a fabrication process for forming the doped region and the gate insulation layer of a gate-insulatorsemiconductor transistor, for example, the specific embodiment shown in Figure 3 is illustrated. An impurity is implanted in the semiconductor substrate 30 in order to form the impurity doped region 32, with a density suitable for controlling the threshold voltage to a required value. Then the gate insulation layer 34 is formed on the substrate 30.

If the gate-insulator-semiconductor transistor is of an n-type, then the substrate is either a p-type silicon substrate or a p-type well formed in an n-type or p-type silicon substrate. If the gate- in su 1 atorsemiconductor transistor is of a p-type, then the substrate is either an n-type silicon substrate or an n-type well formed in an n-type or p-type silicon substrate. In addition, as mentioned above, the doped region 32 is doped with an impurity for controlling the threshold voltage of the transistor.

The gate insulation layer 34 is made of a silicon oxide layer (S'02) or a silicon nitride layer (S'3N,) or a combination of the the silicon oxide layer and the silicon nitride layer, and is of thickness in the range 3.5nm to 5Onm thick.

- 10 Referring to FIG. 4B of the accompanying drawings, there is illustrated a process for forming a gate electrode of the transistor. The gate electrode has a first conductive layer 35 made of titanium nitride which is formed on the surface of the gate insulation layer 34, and a second conductive layer made of a high-melting-point metal or a high-melting-point metal silicide layer 37 and which has a higher conductivity than the titanium nitride first conductive layer.

Referring to Figures 4A and 4B, the titanium nitride first conductive layer 35 has a thickness in the range lOnm to 30Onm and is formed on the surface of the gate insulation layer 34. Formation is effected by using is a reactive sputtering method which uses a reactive gas such as nitrogen, or by a normal sputtering method that directly sputters a titanium nitride target without using the reactive gas, or by a thermal vacuum evaporating method or a chemical vapor evaporating method. The work function of the titanium n itride 35 has a value of between 4.45 eV and 4.73 eV, which is intermediate between the aforementioned work functions of n"' polycrystalline silicon and p' polycrystalline silicon respectively.

Next, a high-melting-point metal layer or high- melting-point metal silicide layer 37 is formed with a thickness of 5onm to 30Onm on the titanium nitride layer 35, by using a normal sputtering method which directly sputters a high-melting-point metal or high-melting- point metal silicide target, or by a thermal vacuum evaporating method or chemical vapour evaporating method.

The high melting point metal is chosen from the following; tungsten (W), titanium (Ti), cobalt (Co), nickel (Ni), palladium (Pd), chrome (Cr), zirconium (Zr), tantalum ,I 9 i i i g i (Ta), vanadium (V), or halfnum (M), or a combination thereof.

Then, the gate electrode is formed by etching out a given area in the first and second conductive layers 35, 37 formed on the substrate 30 by employing a reactive ion etching method. Next, the source and drain areas are formed by implanting or diffusing an ionized impurity having a second conductivity type. In this case, the source and drain areas 40, 41 can be formed conventionally a.s a single structure, similar to those shown in Figure 1, or can be formed as an LDD (Lightly Doped Drain) structure or a DDD (Doubly Doped Drain or Doubly Diffused Drain) structure.

In the foregoing specific embodiment of the present invention, the twolayered gate electrode is made of the first and second conductive layers, however, in another specific embodiment of the present invention, a onelayered gate electrode can be made of only the first conductive layer. The one-layered gate electrode is formed by etching the titanium nitride layer on the gate insulation layer.

As described above, the specific embodiments of the present invention may form a surface-type channel, regardless of the conductivity type of the channel formed in the gate- insulator-s emiconductor transistor, by using as the gate material a material that has a work function of a value between the work function values of n" polycrystalline silicon and p+ polycrystalline silicon. Hence, specific embodiments of the present invention may overcome limitations in integration and size- reduction of conventional buried type channel transistors.

12 - The specific embodiments of the present invention may also provide another advantage, in that a threshold voltage can be prevented from becoming unstable by blocking the diffusion of impurities from the gate electrode into the channel area, and by the use of titanium nitride for a gate material which can serve as a barrier metal.

The specific embodiments of the present invention may also provide still another advantage of improving the r.eliability and performance of a transistor element by preventing a destruction ef f ect in the gate insulation layer due to the reaction of the metal f orming a gate electrode on the gate insulator layer, even if the gate insulation layer is thin, because the reaction between the metal forming the gate electrode with the gate insulation layer may be suppressed by the intervening titanium nitride layer.

The specific embodiments of the present invention may provide a further advantage in that distributing wires of low resistance can be realized by using titanium nitride as a gate electrode, the titanium nitride being a metal compound having a conductivity which is better than that of the n4' or p+ polycrystalline silicon.

The specific embodiments of the present invention may provide a still further advantage in that distributing wires of low resistance can be more readily realized by forming a high-melting-point metal layer or high-meltingpoint metal silicide layer on the surface of a titanium nitride layer, since titanium nitride is capable of making a good contact with other materials and is also a very stable compound.

X i 1 i I 1 1 1 i i 1 1 1 i i i I 1 i i While the invention has been particularly shown and described with reference to preferred specific embodiment, it will be understood by those skilled in the art that modifications in detail may be made without departing from the spirit and scope of the invention.

The reader's attention is directed to all papers and documents which are f iled concurrently with or previous to this specification in connection with this application and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference.

All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and/or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually exclusive.

Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.

The invention is not restricted to the details of the foregoing embodiment (s). The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed.

- 14

Claims

A method for fabricating a transistor having a gate-insulator-semiconductor structure, said method comprising the steps of:

forming a gate insulation layer on the surface of a semiconductor substrate having a first conduct ivity-type wherein a channel region having said f irst conductivity type or a second conductivity type is formed in or substantially at the surface of said substrate; forming a first conductive layer made of titanium nitride (TiN) on the surface of said gate insulation is layer; and 1 sequentially forming a gate electrode by selectively etching said first conductive layer and said gate insulation layer, and forming source and drain regions of a second conductivity type by way of ion implantation or diffusion.
2. A method as claimed in claim 1, wherein said f irst conductive layer has a thickness in the range 10 nanometers to 300 nanometers.
3. A method claimed in claim 1 or 2, wherein said gate insulation layer is made of silicon oxide or silicon nitride, or a combination of said silicon oxide and said silicon nitride.
4. A method as claimed in claim 3, wherein said gate insulation layer has a thickness in the range 3.
5 nanometers to 50 nanometers.

:E i i I i i i i 5. A method as claimed in any one of claims 1 to 4, further comprising a step of forming a second conductive layer after formation of said first conductive layer, said second conductive layer being of a material having a higher conductivity than a conductivity of said first conductive layer.
6. A method as claimed in claim 5, wherein said material of the second conductive layer is a metal or a silicide of 10 a said metal.
7. A method according to claim 6, wherein said metal has a melting point of above 1600 Kelvin.

is
8. A method as claimed in claim 6 or 7, wherein said metal includes one or more of the following: tungsten (W), titanium (Ti), cobalt (Co), nickel (Ni), palladium (Pd), chromium (Cr), zirconium (Zr), tantalum (Ta), vanadium (V), hafnium (Hf).
9. A method as claimed in any one of claims 5, 6, 7 or 8, wherein said second conductive layer has a thickness in the range of 50 nanometers to 300 nanometers.
10. A method as claimed in any one of the preceding claims, wherein a structure of said source and drain areas is one of the following: a single structure; an LDD (lightly doped drain) structure; a DDD (doubly doped drain or doubly diffused drain) structure; or a combination of said single structure, LDD (lightly doped drain) structure and DDD (doubly doped drain or doubly diffused drain) structure.

4
11. A gate- insulator-semiconductor structure transistor having a sem'iconductor substrate, an insulation layer and a gate, wherein said gate includes a barrier material which acts as a physical barrier to a reaction between a material of said gate and said insulation layer.
12. A transistor according to claim 11, in which said barrier material has a work function of a value in the range 4.3 electron Volts to 4.8 electron Volts.
13. A transistor according to claim 11 or 12, in which s aid barrier material comprises titanium nitride (TiN).
14. A transistor according to any one of calims 11 to 13, in which said barrier material has a thickness in the range 10 nanometers to 300 nanometers.
15. A transistor according to any one of claims 11 to 14, in which said gate further comprises a second conductive layer.
16. A transistor according to any one of claims 11 to 15, in which said second conductive layer includes one or more of the following; tungsten(W), titanium(Ti), cobalt(Co), 25 nickel(Ni), palladium(Pd), chromium(Cr), zirconium(Zr), tantalum(Ta),.vanadium(V), hafnium(Hf).
17. A transistor according to any one of claims 11 to 16, in which said second conductive layer is of thickness in the range 50 nanometers to 300 nanometers.
18. A transistor according to any one of claims 11 to 17, wherein said transistor has a gate insulation layer of thickness in the range 3.5 nanometers to 50 nanometers.

i i I i 1 i i 1 1: i 1 j i j I 1 i 1 1 1 i i i 1 j
19. A method of fabricating a gate-insulatorseminconductor structure transistor substantially as hereinbefore described with reference to figures 3 and 4 of the accompanying drawings.
20. A transistor substantially as hereinbefore described with reference to f igures 3 and 4 of the accompanying drawings.
21. A semiconductor device which includes a transistor as c ' laimed in any one of claims 10 to 18 or claim 20, or a transistor made according to a method as claimed in any one of claims 1 to 9 or claim 19.

Published 1992 at The Patent OffIce. Concept House, Cardiff Read, Newport. Gwent NP9 1RH. Further copies may be obtained from ltd. St Mary Cray. Kent.