GB2248352A - Suppressing power transients in a computer system bus - Google Patents

Abstract

In a computer system having peripheral devices and at least one CPU interconnected over a system bus having a plurality of signal lines and +5 volt and +12 volt power supply lines, the signal lines are connected to a peripheral interface via respective isolation switches (82), (Fig 3), the power supply lines are connected to the peripheral interface via a ramping circuit (Fig 2), and the isolation switches and ramping circuit are controlled by a timing circuit (Fig 5), operating so that when a peripheral unit is to be connected to a peripheral interface the supply voltages applied thereto are ramped up over a 5 to 10 m sec period and then the signal line isolation switches are closed, whereas when a peripheral unit is to be disconnected the isolation switches are opened and then the supply voltages are ramped down. Thus, the appearance of transients on the bus power and signal lines during connection and disconnection of a peripheral unit is minimised. An interlock alarm circuit, (Fig 7), gives a visual or audible alarm if an attempt is made to connect a peripheral device at an inappropriate time.

Description

METHOD AND APPARATUS FOR SUPPRESSING POWER TRANSIENT IN A SYSTEM BUS B ACKGROUND OF THE INVEFITION 1. FIELD OF THEINVENTION: This invention is a circuit for suppressing power transients in a system bus, and in particular for suppressing power transients on the power lines and the signal lines of an input and output (1/0) bus.

2. Ant BACXGROUND: When a computer system to which a plurality of peripheral devices are coupled goes through a power up or power down transition, the system-level signals such as Vcc or Vpp are not guaranteed to be valid. By power up transition the present invention refers to the moment when the user starts the computer system. On the other hand, by power down transition the present invention refers to the moment when the user turns off the computer system.

In the past, users adhere to the power up and power down sequence in order to guarantee the stability and validity of system-level signals such as Vcc and Vpp. Power up and power down sequence are steps recommended by the manufacturer of a computer system such as "turn off all peripheral devices before turning off the system or turn on the computer system before turning on the peripheral devices coupled to the computer system".

Failure to follow the recommended power up and power down sequence exposes the computer system to spurious system-level signals or transients.

Power transients are variations in voltages and currents from their steady state counterparts upon the occurrence of a switching operation such as a power up or power down sequence. Power transients often cause physical damage to peripheral devices and result in data corruption in most instances. With respect to a computer system which is coupled with a plurality of peripheral devices over a system bus, power transients are most likely to be introduced into a system bus where an optional peripheral device is inserted onto or removed from the same system bus while the computer system is performing readiwrite operations over the same system bus.

Computer system including multiprocessor and having a plurality of peripheral devices coupled to a system bus is most vulnerable to power transients when the peripheral devices are inserted or removed from the computer system when (1) the Central Processing Unit (CPU) is going through a power up and power down sequence, (2) the peripheral device coupled to the system bus is going through a power up and power down sequence, (3) the peripheral devices are inserted into a power up socket. It is therefore the object of the current invention to suppress the power transients in the computer system by electronically controlling the ramp-up and ramp-down voltages and currents of the power lines of the system bus connecting the power supply to the peripheral devices.

It is another object of the present invention to minimize the current transient on the power line of the system bus by moderating the voltage applied to the peripheral device.

It is yet another object of the present invention to generate reference signal for implementing a power up and power down sequence when the peripheral devices are inserted onto or removed from the computer system.

It is yet another object of the present invention to warn users when a drive socket for a peripheral device is powered up without a peripheral device installed.

The present invention provides a hardware solution to the power transients encountered in a computer system having a Small Computer System Interface (SCSI) The SCSI is a parallel. multimaster l/O bus that provides a standard interface between computers and peripheral devices. It is the method of choice for connecting disks, tape drives, CD ROM, optical disks, (WORM, M.O.) drives, communication devices and even bar code readers to computers of all sizes.

See, Burr W.E. Lohmayer, J.B., "Small Computer System Interface (SCSI), X3P9.2/82-2, Revision 14B", the American National Standards Institute, New York, New York, November 5, 1984; Glass, L.B., "The SCSI Bust, the Byte magazine, February-March, 1990. Although a computer system having an SCSI bus can perform complex concurrent I/O operations with ease, it is extremely sensitive to power transients. For instance, when a removable disk drive is inserted onto an SCSI bus when the CPU coupled to the bus is performing read/write operations the power transients generated by the insertions of the removable disk drive often cause the system bus to crash or to perform faulty read/write operations where the data is particularly harmed.The present invention comprises a bus isolation switch coupled between the system bus and the peripheral device for safe operations when a peripheral device is inserted onto or removed from the system bus. A transient switch is provided between the power lines of the system bus and the peripheral interface to ramp the applied voltage of the peripheral device to its final value in about five to ten milliseconds instead of sub-microsecond transient. This minimizes the current load transients on the power lines of the system bus. The transient switch is further coupled to an onloff timing circuit for generating a plurality of reference signals for implementing a power up and power down system automatically when a peripheral device is inserted onto or removed from this computer system.

Finally, an interlock alarm circuit is coupled to the on/off timing circuit for providing an audible warning signal to the users when a drive circuit is powered up without a peripheral device installed in it. This warns the users of potential data damaging circumstances.

SUMMARY OF THE INVENTION The present invention provides a hardware solution to the power transients encountered in a computer system having a Small Computer System Interface (SCSI) bus. The SCSI is a parallel, multimaster I/O bus that provides a standard interface between computers and peripheral devices. Although a computer system having an SCSI bus can perform complex concurrent I/O operations with ease, it is extremely sensitive to power transients. For instance, when a removable disk drive is inserted onto an SCSI bus when the CPU coupled to the bus is performing read/write operations the power transients generated by the insertions of the removable disk drive often cause the system bus to crash or to perform faulty read/write operations altering the data to be read/written to the disk.

The present invention comprises a bus isolation switch coupled between the system bus and the peripheral device for isolating power lines from the signal lines of the system bus. A transient switch is provided between the system bus and the peripheral interface for causing the voltage applied to the peripheral device to ramp to its final value in about five to ten milliseconds instead of submicrosecond transient. This minimizes the current load transients on the power lines of the system bus. The transient switch is further coupled to an on/off timing circuit for generating a plurality of reference signals for implementing a power up and power down system automatically when a peripheral device is inserted onto or removed from this computer system. Finally, an interlock alarm circuit is coupled to the on/off timing circuit for providing an audible warning signal to the users when a drive circuit is powered up without a peripheral device installed in it.

This warns the users of potential data damaging circumstances.

BRIEF DEscRIPTIoN OF THE DRAWINGS FIGURE 1 is a computer system having multiprocessors being coupled to a system bus and having a plurality of peripheral devices coupled thereto.

FIGURE 2 is a circuit diagram of the power supply ramping switch used in the preferred embodiment of the present invention.

FIGURE 3 is a circuit diagram of the system bus isolation switch being coupled to the system bus and the peripheral interface used in the preferred embodiment of the present invention. Also shown coupled to the isolation switch is a time on/off circuit used in the preferred embodiment of the present invention.

FIGURE 4 is a circuit diagram of a bus isolation switch used in the preferred embodiment of the present invention.

FIGURE 5 is a circuit diagram of the on/off timing circuit used in the preferred embodiment of the present invention.

FIGURE 6 is a timing diagram illustrating the power on and power off sequence generated by the reference signal of the onloff timing signal used in the preferred embodiment of the present invention.

FIGURE 7 is a circuit diagram of the interlock alarm circuit used in the preferred embodiment of the present invention DETAILED DESCRIPTION OF THE INVENTION A circuit is disclosed for suppressing the power transients in a computer system during the power up and power down transition when a peripheral device is inserted onto or removed from the computer system. In the following descriptions, numerous specific details are set forth such as specific circuit elements in order to provide a thorough understanding of the present invention.

In other instances, well known elements such as resistors, transistors and other well known devices are not described in detail in order not to unnecessarily obscure the present invention. It should be understood by one skilled in the art that a computer system refers to at least a CPU being coupled to a system bus and further having a plurality of peripheral devices coupled to a system bus.

Figure 1 illustrates a general purpose computer system having a system bus referred to generally by the number 10. As illustrated, bus 10 comprises power line 12 and a plurality of signal lines 14. The power line 12 is further coupled to power source 16 for supplying power to devices coupled to bus 10.

Signal lines 14 include signal lines found in most system buses such as, address lines, control lines and data lines. The bus 10 is further coupled to a plurality of Central Processing Units (CPU) 18 through N. The CPU 18 Is coupled to the bus 10 over system bus interface 22 for receiving power from power line 12 and for sending controlling signals to the peripheral devices attached to the bus 10.

Referring again to Figure 1, a plurality of peripheral devices 20 to N are shown coupled to bus 10 over peripheral interface 24 for receiving data address instructions and controlling signals from CPU 18 and optionally receiving power from power source 16. It should be understood by one skilled in the art that in some cases the peripheral devices represented by 20 has power sources independent from power source 16 as illustrated in Flgure 1. In the preferred embodiment of the present invention, peripheral devices 20 to N and the system bus 10 share the same power source 16.

When a computer system such as the one described in Figure 1 goes through a power up or power down transition, the system-level signals such as Vcc or Vpp are not guaranteed to be valid. In the past, users adhered to the power up and power down sequence in order to guarantee the stability and validity of system-level signals. Power up and power down sequence are steps recommended by the manufacturer of a computer system to minimize the impact of power transients from affecting the integrity of the computer system as well as the data on a data bus. Failure to follow the recommended power up and power down sequence exposes the computer system to spurious system-level signals or power transients. Power transients are variations in voltages and currents from the steady state counterpart upon the occurrence of a switching operation such as a power up or power down sequence.Power transients often cause physical damage to the CPU or the peripheral device coupled to a system bus and result in data corruption in most instances. With respect to a computer system which is coupled to a plurality of peripheral devices over a system bus, power transients are most likely to be introduced into a system bus where an optional peripheral device is inserted onto or removed from the same system bus while the computer system is performing read/write operations bver the same system bus.

In a preferred embodiment of the present invention, the CPU 18 and the peripheral devices 20 to N are coupled to a Small Computer System Interface (SCSI) bus. The SCSI is a parallel, multimaster I/O bus that provides a standard interface between computers and peripheral devices. See, Burr W.E. Lohmayer, J.B., "Small Computer System Interface (SCSI), X3P9.2/82-2, Revision t4B", the American National Standards Institute, New York, New York, November 5, 1984.

Although the SCSI bus can perform complex concurrent I/O operation with ease, it is extremely sensitive to power transients. For instance, when a removable disk drive is inserted onto an SCSI bus when the CPU coupled to the same bus is performing read/write operations, the power transients generated by the insertions of the removable disk drive often cause the system to crash or to perform faulty read/write operations that may alter data being read or written to the disk. It should be understood by one skilled in the art that the present invention is not limited to an SCSI system bus. It is within contemplation of the present invention that the apparatus and method disclosed in the present invention can be modified and adapted in a straightforward manner for a computer system having a system bus including at least a power line and a plurality of signal lines.

Figure 2 is a circuit diagram of the power supply ramping circuit using the preferred embodiment of the present invention. The power supply ramping circuit 30 limits the input current on the voltage inputs of the peripheral device to remove the power supply transients caused by the change in step load. The change in step load is most prominent when a peripheral device such as a removable disk drive is inserted onto or removed from the power supply of an expandable computer system such as a multidrive external expansion unit. The power supply attempts to respond to this change in step load and may eventually settle out to supplying the normal output supply voltages. In the interim, power supply transients would be induced in the output of voltages. The power supply transients cause the power supply to respond by going severely out of its normal output range.If other peripheral devices were coupled to the same power supply and were operating and transferring data at the same time, the integrity of the system data will be impaired. In the preferred embodiment of the present invention, a removable disk drive is inserted into the external multidrive external expansion unit of a 386 computer system. The current and voltage transients were measured with reference to the + 5 and + 12 volt output. The current transients into the + 5 volt terminal reached almost 13 amps peak. While the voltage transients dropped almost 2.5 volts. Similarly, the current transients into the + 12 volt terminal reaches a peak of almost 25 amps and the voltage transient falls almost 8 volts. The current and voltage transients last between 25 and 30 microseconds before the power supply returns to normal regulation. When the power supply drives the peripheral device, the power supply ramping circuit 30 has its input coupled to the power lines of a system bus over the Vcc terminal 32 and the VDD terminal 34. The power supply ramping circuit 30 further has its output coupled to the power line interface of the peripheral device at the + 5 volt drive terminal 38, the + 5 volt solenoid terminal 42 and the + 12 volt drive terminal 40. The power supply ramping circuit further comprises of two NPN transistors, 50 and 60, and PNP 44, 46, 48, 68, and 70. The transistor 60 and the transistor 58 form a Miller Integrator while the transistor 50 and transistor 48 form another. The capacitors 56 and 62 serve as the integrating capacitors while the resistors 64 and 76 serve as the integrating resistors.Upon receiving PSEN (Power Supply Enable) signal 98 from the on/off timing circuit 90 (to be described in sections below) and latched by the transistor 70, a DC step appears at input 50 and 60 to the output drive transistors 44, 46, 48, 68, and 58. The timing ramp takes place in the time approximately RC.

Eventually, both drive transistors 50 and 60 saturate and transistors 44, 46, 48, 58, and 68 are turned on until the PSEN signal is turned off and the output signals ramp down. The drive requirement is set by the maximum current through a series of transistors. This current is set by the resistors 52, 54, 74 and 79. The minimum assumed beta gain for saturation is assumed to be 20 for PNP transistors 44, 46, 48, 68 and 70. The actual gain of the output transistor stage is relatively close to unity. So, the ramp produced at each base produces a similar ramp at the output. Actual timing in the circuit 30 is not critical since the ramp is very slow compared to the power supply regulation and bandwidth. In the preferred embodiment of the present invention, the PNP power transistors 44, 46, 48, 68 and 70 are TIP 36. Preferably, the NPN power transistor 60 is TIP 120.

Finally, in the preferred embodiment of the present invention, the NPN transistor 50 is a 2N2222 transistors.

Figure 3 Is a circuit diagram of the system bus isolation switch used in the preferred embodiment of the present invention. A bus isolation switch 80 is shown coupled to each of a plurality of signal lines connecting the system bus 10 and the peripheral interface 24. The bus isolation switch 80 is shown further coupled to a on/off timing circuit 90 to be described in detail in Figure 5. The bus isolation switch 80 prevents random system failure during the insertion or removal of a peripheral device from the system device when other peripheral device coupled to the system bus is performing read/write operation concurrently. The bus isolation switch 80 comprise a plurality of switches, the representative of which are switches 82, 84, and 86.

Figure 4, is a partial view of a bus isolation switch 80 as implemented for one signal channel only. A gate drive 82 is coupled in parallel between all the gates for the rest of the channels. The gate drive 82 is preferably a high speed FET transistor of the VQ1001J type. The gate drive 82 is coupled at one of its input to the signal line of the system bus 10. The gate drive 82 is further coupled at its other input to transistors 84 and 86. Transistor 84 is coupled to the - 5 volt power line of the system bus. Transistor 86 on the other hand, is coupled to the set on/off timing circuit to be described in detail in Figure 5. In the preferred embodiment of the present invention, transistor 84 is a general purpose NPN transistor 2N2222A. Preferably, transistor 86 is a general purpose PNP transistor of the 2N2907A type.The transistor 86 receives an SCSI~EN (SCSI enable) signal (to be described further below) from the on/off timing circuit 90. The gate drive 82 is coupled at its output to the corresponding signal line of the peripheral interface 24. In the preferred embodiment of the present invention, the SCSI bus has 18 individual signal lines. As such, 18 gate drives 82 are needed to isolate the voltage transients caused by the insertion and/or removal of the peripheral device from the SCSI bus.

The bus isolation switch 80 prevents the insertion/removal of a peripheral device on an SCSI bus from asserting a logic TRUE (low) signal on the same bus.

The input characteristics of a powered down bus driver resembles a forward biased Schottky diode. The biased voltage of such a device will be nominally 0.2 to 1.1 volts. The SCSI TRUE state is a logic low at 0.0 to 0.8 volts DC. The SCSI FALSE state is a logic high at 2.0 to 5.25 volts DC. It follows when a powered down peripheral device Is connected to the SCSI bus, a TRUE signal will be asserted on the bus. A spurious TRUE state asserted onto the SCSI bus will cause the SCSI initiator (not shown, generally located with bus controller) to interpret either a valid or invalid state on the bus.As the spurious TRUE insertion is unknown, the SCSI initiator tends to Ignore the SCSI data or in some cases, intermittently cause a system failure or "hang.up". Thus, when a peripheral device is in a powered down state, the bus isolation switch 80 serves to prevent random system failures during the insertion/removal of a peripheral device.

Referring again to Figure 4, gate resistors 25 and 27 are included to drive or to abort the on/off current, giving the bus isolation switch turn-on turn-off times in the order of 100 milliseconds. It follows that the system bus isolation switch would effectively suppress any disturbance to the system bus or in this case SCSI bus when the switches are turned on or off.

Figure 5 is a circuit diagram of the onloff timing circuit using the preferred embodiment of the present invention. The on/off timing circuit 90 is coupled at its input to the + 12 volt DC power line of the system bus 10. The onloff timing circuit further generating four outputs, switch enable SW~EN 96, power enable PSEN 98, RESET 100 and SCSI enable SCSI~EN 102. The on/off timing circuit 90 is coupled to the bus isolation switch 80 as illustrated in Figure 4 for bringing the peripheral device which was recently asserted into the system bus into a known state automatically. The on/off timing circuit 90 further comprises a toggle switch 92, transistor 106, 110, and 114, inverters 104, 108, 112, and 118, and gates 116, and diodes 105 and 111. The SW~EN signal 96 is the master enable/disable line indicating whether the connection of the peripheral device to the system bus is on or off. When the toggle switch 92 is turned on, the 12 volt power line of the system bus is connected to the on/off timing circuit 90 over the resistor 101 to ground level and immediately changing the logic state of the inverter 104 from low to high, thus enabling SW~EN. The PSEN signal 98 permits the power on/off circuitry to change states in a controlled fashion. This signal line is coupled to a ramping circuit as shown in Figure 2, and is generated only when SW~EN is 10ed on at the gate of transistor 106. When the SOW YEN is turned off, the PSEN is deasserted after a delay of 100 milliseconds, allowing the ramping down to take place.The RESET signal 100 is used to reset the peripheral device to a known state before a connection can be established. Initially, this signal is assumed to be in a reset state, and forces the peripheral device to come up in a reset condition, until a stable state is achieved after 100 milliseconds, In a normal I/O operation, the RESET signal 100 is controlled by the RESET signal line of system bus. Finally, the SCSI~EN signal 102 is initially in the high state. This gives the peripheral device time to stabilize without being connected to the system bus 10.

The idea is to prevent any spurious system bus state from being asserted when the peripheral device is powered up. As such, the SCSI EN signal 102 is generated after a predetermined amount of delay subsequent to the assertion of RESET signal 100. Thus, when the power line of the system bus 10 is asserted over the resistor 109, inverter 112, and the inverter pairs 118, the SCSI EN signal is guaranteed to be asserted after the assertion of the RESET signal 100.

Figure 6 is a timing diagram showing the assertionldeassertions of the four timing signals generated by the on/off timing circuit as illustrated in Figure 5.

In the preferred embodiment of the present invention, the peripheral device to be coupled or removed from the system bus is a removable disk drive. Using that as an example, when the drive is inserted into the system bus, the SW~EN signal 96 is initially off. The user turns on the toggle switch 92 in the on/off timing circuit thus generating a step load. Simultaneously, PSEN signal 98 is asserted to guarantee that power is being applied to the removable disk drive. After 100 milliseconds the power on circuit is in a stable state, the RESET signal 100 is deasserted after additional millisecond propagation delay the SCSI~EN 102 will go from a high to a low state thus enabling the signal switches. This sequence of steps brings the drive to a known (RESET) state and connects the drive electrically to the SCSI bus.

Referring again to Figure 6, the on/off timing circuit 90 undergoes a reverse sequence of steps when the peripheral device is removed from the system bus. At the start of the disconnection, it is assumed that no transactions are occurring between the peripheral device and any other device on the system bus. Furthermore, a SW~EN signal 96 is high signifying that the system is enable.

Next, the PSEN signal 98 is low meaning that the power is still applied on the terminals of the peripheral device. Meanwhile, the RESET signal 100 is high showing that the peripheral device is in the non-reset state, thus turning off the on/off timing circuitry. Finally, the SCSI~EN signal 102 is low showing that the bus isolation switches are closed. At some point later in time, the users would toggle the SW~EN signal 102 from high to low state. This indicates to the computer system that a request is given to disconnect a peripheral device. The following sequence shall occur: the RESET signal 100 will immediately go from high to low, the peripheral device would immediately tri-state all its driver and will go into the reset state.After a short predetermined delay, the following shall occur: the SCSI~EN signal 102 will go from low to a high state allowing the settling for the RESET and the PSEN signal to occur. At this point, the peripheral device power control circuitry will ramp the peripheral device power down to the power off condition. Finally, the user may safely disconnect this peripheral device from the system.

Figure 7 is a circuit diagram of an interlock alarm switch used in the preferred embodiment of the present invention. The bus isolation switch 80 as described in Figure 3 can be defeated by connecting or disconnecting a peripheral device to the system bus when the SW~EN signal 96 is active. To prevent this, an interlock alarm circuit 120 is provided when the drive power is enabled and an attempt is made to insert a drive that has been previously removed. Referring again to Figure 7, the interlock alarm signal comprises of a transistor 122, a buzzle alarm device 124, a gate drive 126 and two diodes 125 and 127. The interlock alarm circuit 120 is driven by the SCSI EN signal 102.

When the transistor 122 is turned on, the power line of system bus 10 will activate the alarm if the gate drive 126 is driving. The only condition for activating the gate drive 126 is an SCSI ground connection from the peripheral interface over line 24, and this condition occurs only when the peripheral device is firmly connected and locked. The interlock alarm circuit has an automatic + 5 volt DC solenoid driver which engages a solenoid that prevents the peripheral device from being removed when the + 5 volt DC power is applied to the peripheral device. In the preferred embodiment of the present invention the output device 124 is a speaker that provides an audible alarm when appropriate. It should be understood by one skilled in the art that an LED or other suitable display device may be used in place of the speaker 124.If the SCSI enable signal is active, i.e. (the bus isolation is in close state), the peripheral device is not connected and an alarm will warn the users when the users try to connect or disconnect the peripheral device to the bus.

While the present invention has been particularly described with reference to Figures 1 to 7 and with emphasis on certain system bus and peripheral devices, it should be understood that the figures are for illustration and should not be taken as limitations upon the invention. In addition, it is clear that the methods and apparatus of the present invention has utility in any application where suppression of power transients in a system having a computer bus and a plurality of peripheral devices are desired. It is contemplated that many changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention as disclosed above.

Claims (12)

1. In an expandable computer system including at least one central processing unit, said processor being coupled to a first peripheral device over an input and output (I/O) bus, said l/O bus being optionally coupled to at least a second peripheral device, said I/O bus having a plurality of signal lines inclusive of a first voltage supply and a second voltage supply, a means for minimizing the transients throughout said computer system when said second peripheral device is being inserted onto or removed from said I/O bus while said first peripheral device remains in communication with said processor over said I/O bus, said means comprising:: bus isolating means coupled between each said signal lines of said I/O bus and said second peripheral device for isolating the power supply transients caused by the insertion or removal of said second peripheral device on said I/O bus, said switching means further minimizing the impedance mismatch created by the insertion or removal of said second peripheral device; on/off timing means coupled to said switching means and said second peripheral device for generating a plurality of timing signals to minimize the interference of power transients with the normal read/write operation of said I/O bus, said power transients being generated by said second peripheral device during the power up and power down sequence of said second peripheral device, said sequencing means further being coupled to said second voltage supply for receiving a reference voltage;; ramping means coupled to said timing means and to said second peripheral device for isolating the current transient through out said computer system when said first peripheral device is turned on, said iamping means being further coupled to said first voltage supply and said second voltage supply ; and warning means coupled to said timing means for alerting user of the invalid condition where user attempts to insert said second peripheral device on said I/O bus when said I/O bus is in an active read/write mode with said first peripheral device.

2. The computer system as defined in claim 1, wherein said I/O bus is a small computer system interface (SCSI) bus.

3. The computer system as defined in claim 1, wherein said first voltage supply Vcc is five volts.

4. The computer system as defined in claim 1, wherein said second voltage VDD is twelve volts.

5. The computer system as defined in claim 1, wherein said isolating means includes a field effect transistor (FET), the drain drive of said FET being coupled to said I/O bus, the source drive of said FET being coupled to said second peripheral device, the gate drive of said FET being coupled to said sequencing means over at least two device transistors.

6. The computer system as defined in claim 1, wherein said on/off timing means comprises a toggle switch being coupled to a first delay means, a second delay means, a third delay means and a fourth delay means for generating a switch enable signal, a power enable signal, a reset signal and a signal line enable signal, respectively.

7. The on/off timing means as defined in claim 6, wherein said first delay means is coupled to said toggle switch and said power line of said system bus for generating said switch enable signal, said first delay means having at least a resistor and an inverter, said switch enable signal further being coupled to said bus isolating means for indicating if said second peripheral device is inserted or removed from said system bus.

8. The on/off timing means as defined in claim 6, wherein said second delay means coupled at its input to said first delay means and said power line of said system bus for supplying power to said ramping means as soon as said second peripheral device is being inserted on said system bus, said second delay means further terminating power to said second peripheral device after the assertion of said reset signal and said signal line enable when said second peripheral device is being removed from said system bus.

9. The on/off timing means as defined in claim 6, wherein said third delay means is coupled at its input to said second delay means, said signal lines and said power lines of said system bus for putting said second peripheral device in a known state when said second peripheral device is being inserted onto or removed from said system bus, said second delay means having at least a transistor and AND gate.

1 0. The on/off timing means as defined in claim 6, wherein said fourth means is coupled to between the inputs of said second delay means and said third delay means for enabling and disabling said signal lines of said system bus, said fourth delay means further being coupled to said alarm means for activating said alarm means when user attempts to insert said second peripheral device on said I/O bus when said I/O bus is in an active readlwrite mode with said first peripheral device, said fourth delay means having at least a resistor coupled to an inverter.

11. The computer system as defined in claim 1, wherein said ramping means comprises at a plurality of Miller integrators, said Miller integrators being coupled at its input to said timing means for receiving said power enable signal therefrom, said Miller integrators generating a plurality of ramps until said power enable signal is deasserted, said Miller integrators further being coupled at its inputs to said power lines, said Miller integrators further being coupled at its outputs to the power lines of said second peripheral device.

12. The computer system as defined in claim 1, wherein said warning means comprises a gate drive, said gate drive having its gate coupled to said second peripheral device, said gate drive further having its drain coupled to a transistor over an audio output device, said transistor being coupled at its gate to said timing means, said transistor being coupled at its source to said power line of said system bus.