GB2249227A

GB2249227A - A voltage chopping converter with an improved control

Info

Publication number: GB2249227A
Application number: GB9122152A
Authority: GB
Inventors: Jean-Marc Mollard; Michel Nollet
Original assignee: Dassault Electronique SA
Current assignee: Thales SA
Priority date: 1990-10-25
Filing date: 1991-10-18
Publication date: 1992-04-29
Anticipated expiration: 2011-10-18
Also published as: GB2249227B; FR2668664B1; FR2668664A1; GB9122152D0

Abstract

The converter block OV comprises an input for a substantially direct voltage V+, V- including a first and second input terminal BE1, BE2 and an output including a first and a second output terminal BS1, BS2 for delivering between these terminals an output voltage VS with the desired characteristics. A circuit module has two controllable bidirectional current interrupting units TP1, TP2 disposed between the two input terminals. The control means PWM, CM1 and CM2 are capable of controlling the two interrupting units simultaneously and in opposition to each other in accordance with a control code linked to the desired characteristics of the output voltage and including, according to a chopping frequency, a succession of cycles of identical durations. An output filter includes an inductor LF and a capacitor CF and has a cut-off frequency chosen in accordance with the chopping frequency. The transistors TPI, TP2 may be VMOS devices and are controlled by pulse width modulation. Voltage limiting circuits ECR1, ECR2 limit excess voltage to protect components of the converter. Short circuit and excess current protection circuits MCC, MSI are provided. <IMAGE>

Description

A CHOPPING VOLTAGE CONVERTER WITH AN IMPROVED CONTROL The invention concerns the conversion of voltages.

It applies in particular, but not exclusively, to aeronautics where it may prove necessary to have an electric energy source available capable of supplying a voltage, generally a sinusoidal voltage, with a stable amplitude and frequency.

This voltage may be generated from an alternator connected to a motor or a turbine and whose rotational speed is intended to be kept constant by means of a hydraulic or mechanical coupling mechanism. However, the energy output of such a device is fairly low and only moderately reliable.

Moreover, when the alternator feeds an non-resistive load, the regulation of the supplied output voltage is disturbed and consequently, the current absorbed by the load is nonsinutoidal.

Another drawback lies in the fact that the voltage supplied by the alternator is liable to vary over a very considerable range, it being possible for the ratio between the maximum and minimum voltage levels to be higher than three in certain cases.

Moreover, since the output impedance of the alternator is inductive, the current harmonics absorbed by a load are transformed into voltage harmonics, the result of which is a modification of the output voltage which is no longer of a sinusoidal type.

It has been envisaged that these drawbacks can be overcome by using conventional static converters. However, the latter are unwieldy, heavy and bulky and they have therefore been shown to be incompatible with the constraints of weight and space generally necessary in the field of aeronautics.

Thus, in spite of its inherent drawbacks, the above described device with an alternator is generally used.

The invention aims to provide a more satisfactory solution to this problem.

It goes against the solutions currently adopted by proposing a voltage conversion device having a structure and operation radically different from the existing converters which makes it possible to overcome the drawbacks of weight and bulk of the earlier devices.

One object of the invention is to propose a device allowing an output voltage to be supplied with the desired characteristics, for example, a sinusoidal voltage, whose amplitude and frequency can be controlled independently.

Another object of the invention is to propose a voltage converter capable of operating as an energy receiver in the case of certain specific loads.

A further object of the invention is to supply a device having a very low output impedance.

According to a general characteristic of the invention, the voltage conversion device includes a converter block comprising: - an input for a substantially direct input voltage comprising a first and a second input terminal; - an output comprising a first and a second output terminal for delivering an output voltage between these terminals having the desired characteristics; - a circuit module having a first and second primary terminal respectively connected to the first and second input terminal and a secondary terminal, and comprising * a first controllable bi-directional current interrupting unit disposed between the first primary terminal and the secondary terminal; and * a second controllable bi-directional current interrupting unit, disposed between the second primary terminal and the secondary terminal; - control means capable of controlling the two interrupting units simultaneously and in opposition to each other in accordance with a control code linked to the desired characteristics of the output voltage and comprising according to a chopping frequency, a succession of cycles of an identical duration; and - a wave filter including an inductor disposed between the said secondary terminal of the circuit module and one of the output terminals, as well as a capacitor disposed between the two output terminals, this filter having a cut-off frequency chosen in accordance with the chopping frequency.

According to an embodiment of the invention, the first current interrupting unit includes a first controllable main switch, for example, a field effect power transistor connected to the first primary terminal and having a current blocking state as well as a passing state; similarly the second interrupting unit includes a second controllable main switch, for example also a field effect power transistor connected to the second primary terminal and having a current blocking state as well as a passing state; when each cycle of the control code is subdivided into a first segment and a second segment having respectively cyclic ratios modulable in accordance with the desired characteris tics of the output voltage, the control means are then capable of * assigning, during the first segment, to the first main switch one of its blocking and passing states and assigning to the second main switch one of its blocking and passing states in opposition to that assigned to the first main switch, and * of respectively assigning during the second segment their other state to the first and second main switches.

It is particularly advantageous, especially when the output voltage is a periodic voltage with a chosen frequency, for example a sinusoidal voltage, and when the chopping frequency is at least equal to 100 times the said chosen frequency, for the control means to comprise a pulse-width modulation circuit followed by a coupling transformer whose primary winding is connected to the two output terminals of the pulse-width modulation circuit, and having two secondary windings wound in opposite directions relative to each other for passing, to two control boxes, control signals intended to switch the switches of the bidirectional interrupting units.Such an arrangement allows in particular the correct transmission of a control code comprising, for example, a rectangular width-modulated signal at the chopping frequency of 100 kilohertz which signal has a low frequency, for example 400 hertz, without deformation of the shape of the square waves.

The device also very advantageously includes a safety assembly capable of managing any possible excess currents or short circuits in a load connected at the output of the converter block.

As regards the circuit module, it is particularly ad vantageous for it to comprise current inertia means capable of acting on the variation of the level of the current circulating in at least some of the switches during the switching.

These current inertia means may for example, include an inductive circuit. There may then be associated therewith voltage limiter circuits capable of limiting the excess current generated during the switching to a chosen threshold.

In order that the present invention may more readily be understood the following description is given, merely by way of example, with reference to the accompanying drawings, in which: - Figure 1 is a general schematic block diagram of a device in accordance with the invention, - Figure 2 illustrates purely schematically an example of obtaining the input voltage in the device of Figure 1, - Figure 3 is a more detailed schematic block diagram of a part of the device of Figure 1.

- Figure 4 represents diagrams illustrating the operation of the device of Figure 1 in a general way, - Figure 5 illustrates the part of the device illustrated in Figure 3 in greater detail, - Figures 6, 7, 8 and 9 illustrate parts of the block diagram of Figure 5 in detail, and, - Figure 10 represents other diagrams showing the operation of the device in accordance with the invention.

The drawings comprise in essence elements of a definitive nature. On this basis, they form an integral part of the description and may not only serve to render the description given below more readily understood but, if required, they may also contribute to the definition of the invention.

As illustrated in Figure 1, the conversion device comprises three converter blocks CV1, CV2, CV3 of a similar structure, each capable of delivering output voltages VS1, VS2, VS3 to a load CH from a substantially direct input voltage V+, V-.

It will here be assumed that these three output voltages are sinusoidal voltages having the same amplitudes and the same frequencies, but phase-displaced in relation to each other by 1200. These voltages are obtained from three reference voltages Vref, displaced by 1200 corresponding to the desired output voltage but at a level as compared with that desired for this output voltage. These three reference voltages are generated from the same generator and may be modified independently in their level and frequency. This generator GEN also supplies a clock signal SYNC so as to synchronize the chopping frequency of the three converter blocks.

When the conversion device is mounted on board an aircraft to supply the output voltage to various pieces of equipment of the aircraft, the input voltage V+, V- may be generated from the set-up illustrated in Figure 2. An alternator ALT, connected to a motor or a turbine MOT and having its neutral terminal connected to the aircraft earth, supplies a sinusoidal three-phase voltage whose nominal amplitude amounts to approximately 200 effective volts between the phases and whose nominal frequency is approximately 400 Hertz. However, the amplitude of this three phase voltage may vary between 100 volts and 311 volts between phases and the frequency may vary between 300 Hertz and 750 Hertz.

This voltage is rectified by a six phase diode system RDI which, after inductive-capacitive filtering FLT, provides the substantially direct input voltage V+, V- whose nominal level is approximately 280 volt, but may vary between 140 volts and 440 volts. Moreover, this direct voltage may have a residual ripple whose frequency is from 1,800 Hertz to 4,500 Hertz and whose level in the troughs is approximately 0.866 times the peak voltage.

For the sake of simplification, only one of the three converter blocks will now be described. This is represented in greater detail in Figure 3 and bears the reference CV.

The references BE1 and BE2 respectively designate the first and second input terminals capable of receiving the input voltage V+, V-. The output voltage VS is delivered between a first output terminal BS1 and another output terminal BS2.

According to a general characteristic of the invention, the converter block includes a circuit module MCOM having a first primary terminal BP1 connected to the first input terminal BE1, a second primary terminal BP2, connected to the second input terminal BE2 as well as a secondary terminal BSS. Provision is also made for a low pass wave filter LPF, comprising an inductor LF disposed between the secondary terminal BSS of the circuit module and one of the output terminals (here the terminal BSl), as well as a capacitor CF disposed between the two output terminals.

In the example described, the second output terminal BS2 is connected to the second input terminal BE2. However, it could be connected to the first input terminal BE1, the capacitor CF remaining disposed between the two output terminals.

In the case where a single converter block would be used for providing an output voltage, the connection 1 between the terminal BS2 and the terminal of the capacitor CF would preferably be eliminated, and the terminal BS2 would then be connected to the voltages V+ and V- by two electrolytic capacitors so as to provide at this terminal BS2 a fictitious zero reference voltage in relation to the voltages V+ and V-. The expert will nevertheless understand that the capacitor CF would in this case still be (indirectly) connected between the two output terminals.

The circuit module comprises a first bi-directional controllable current-interrupting unit I1, disposed between the first primary terminal BP1 and the secondary terminal BSS, as well as a second bi-directional current-interrupting unit I2, also controllable, disposed between the second primary terminal BP2 and the secondary terminal BSS.

The control means COMD are capable of controlling the two bi-directional interrupting units, simultaneously and in opposition to each other in accordance with a control code linked to the desired characteristics of the output voltage, this control code including, according to a chopping frequency, a succession of cycles of an identical duration.

The wave filter LPF then has a cut-off frequency chosen in accordance with the chopping frequency.

When the output voltage is a periodic voltage, for example, a sinusoidal voltage of a chosen frequency, the chopping frequency is very advantageously equal to at least 100 times the value of the chosen frequency which makes it possible, especially when the output voltage is sinusoidal, to minimize the rippling rate of the output voltage which occurs at the chopping frequency, whilst using a wave filter having a high cut-off frequency and being therefore not bulky.

However, in certain applications, one may permit a ratio of 50 between the chopping frequency and the chosen frequency, which then leads to reduced efficiencies.

As will be seen in greater detail below, the first interrupting unit I1 includes a first controllable main switch, connected to the first primary terminal BP1 and having a current blocking state as well as a passing state. Similarly the second interrupting unit I2 includes a second controllable main switch connected to the second primary terminal BP2 and also having a current blocking state as well as a passing state.

In general, each cycle of the control code is subdivided into a first segment and a second segment each having cyclic ratios modulable in accordance with the desired characteristics of the output voltage.

The control means are then capable of, * during the first segment, assigning to the first main switch one of its blocking and passing states and assigning to the second main switch one of its blocking and passing states in opposition to that assigned to the first main switch, and * during the second segment, respectively assigning their other state to the first and second main switches.

To obtain this function, it is particularly advantageous for the control means to comprise a pulse-width modulation circuit PWM whose two output terminals are connected to the two terminals of the primary winding EP of a coupling transformer with a unity ratio. The secondary SEC of the transformer has two windings connected respectively to two control boxes CMl and CM2 of the bidirectional interrupting units I1 and I2. This pulse-width modulation circuit thus delivers, from the reference voltage Vref, two base signals SB1 and SB2 whose characteristics depend on the control code and from which will be elaborated the final control signals to be delivered by the control boxes to the bidirectional interrupting units.It may already be observed that the coupling transformer ensures an electric installation between the pulse-width modulation circuit PWM and the control boxes. This function will be discussed in greater detail below.

These control means COMD also include attenuation means ATT connected to the output of a converter block, capable of receiving the output voltage VS and of delivering a corresponding auxiliary voltage VA having an attenuated level as compared with that of the output voltage. It will be seen below that this auxiliary voltage will be used by the pulse-width modulation circuit in conjunction with the reference voltage Vref to supply an image voltage of the desired output voltage but at an attenuated level as compared with that desired for the output voltage, and on the basis of which the first and second base signals SB1 and SB2 will be generated.

It is also particularly advantageous for the converter block CV to include a safety assembly CDS comprising means MSI capable of managing any possible excess currents as well as means SCC capable of dealing with possible short circuits at the output of this converter.

Before examining the structure of this converter block CV in detail, a brief description will be given of the general operation with reference to Figure 4 where the dimensions have been greatly exaggerated to provide a better understanding.

It is here assumed that the desired output voltage VS is sinusoidal. It is also assumed that the converter block reconstitutes a positive half cycle of the output sinusoidal wave and that a resistive load is connected at the output of this converter block.

The first diagram of this Figure 4 illustrates the different states assumed by the first main switch TP1. It is assumed that, during the first segment SG1 of the cycle CY, the switch TP1 is in its passing state (level 1), while during the second segment SG2, it is in its blocking state (level 0). It will here be observed that the duration of each cycle CY is equal to the chopping period TD.

The second diagram of this Figure 4 illustrates the various states assumed by the second main switch TP2 which is controlled in opposition as compared with the first main switch, and is therefore in its blocking state during the first segment SG1 of the cycle CY and in its passing state during the second segment SG2.

In consequence, during this first segment SG1, the voltage V+ is applied to the inductor LPF which is reflected by the flow through this inductor LF of a current IL which increases linearly up to a value IM depending on the characteristics of the inductor, the input and output voltages, and also the duration of the segment SG1. This increase is linear because the applied voltage is constant over the whole duration of the segment SG. During the segment SG2, it is the voltage V- which is applied to the inductor LF and is reflected in a decrease of the current IL.It should here be noted that the reference Vi designates the level of the intermediate voltage equal to

As a result, as illustrated in the last diagram of this Figure 4, the mean value of the output voltage VS during the period of the first cycle is equal to (V+) since the 2 duration of the segment SG1 is equal to three times that of the segment SG2. During the following cycle, the cyclic ratio of the segment SG1 is equal to 7/8 whereas that of the segment SG2 is equal to 1/8 which thus leads to a mean voltage VS equal to 3/4.V+. The general shape of the output voltage VS which is substantially sinusoidal is represented in dotted line in this diagram.

Reference will now be made more particularly to Figure 5 to describe in greater detail the constituent elements of the converter block CV.

An essential element of the control means lies in the pulsewidth modulation circuit PWM such as that marketed by the SILICON' GENERAL Company under reference 1526. For the sake of simplification, only the eighteen tags 1-18 of the box, as well as the main elements of its internal processing means, have been represented. The expert can refer to the technical specification for this circuit for more details, if required.

In the application herein described, the tags 45 and 8 are not used. The-tags 6 and 7 are together connected to earth, the tags 11 and 15 are individually connected directly to earth, and the tags 9 and 10 are respectively connected to earth by means of a resistor R69 and a capacitor C70.

The internal voltage of 5 volts is supplied via the tag 18 connected on the one hand to an external voltage of 5 volts and on the other hand to earth via a capacitor C78. The internal supply for this circuit PWM is drawn from the tag 17 connected on the one hand to a voltage of 15 volts via a resistor R77 and earthed, on the other hand, via a capacitor C77.

The tags 1, 2 and 3 define a control input of the circuit PWM. The reference voltage Vref supplied by the generator GEN is supplied to the tag 1 of the circuit after being offset by a resistance bridge R66, R67 and filtering by a capacitor C67.

The attenuation means ATT include a set of three resistors R61, R63, R65 disposed in series between the first output terminal BS1 and earth, as well as a resistor R64 connected on the one hand to the 5 volt voltage and the common terminal of the resistors R65 and R63. This same common terminal is connected to the tag 2. The set of these four resistors is capable of attenuating the output voltage VS, here in a ratio approximately equal to 200, as well as to displace it also by a threshold (offset) comparable to the displacement threshold of the reference voltage Vref. Thus one obtains in general an auxiliary voltage VA (available at the tag 2) at a level comparable to that of the reference voltage (available at the tag 1). These attenuation means also include a filter capacitor C61 disposed between the terminal common to the resistor R61 and the resistor R63 and the second output terminal BS2 of the converter block.

Finally provision is made for a second filter mounted in parallel at the terminals of the resistor R63 and consisting of a resistor R62 disposed in series with a capacitor C62.

The third tag of this control input is connected on the one hand to earth via a filter consisting of a resistor R68 in series with a capacitor C68 and on the other hand, to one of the outputs of the safety assembly CDS which will be described in detail below.

As regards the internal processing means of the circuit PWM, they include in essence a transconductance error amplifier AE whose two input terminals are respectively connected to the two tags 1 and 2 of the circuit PWM and whose output is connected to the first input of a comparator A2. The second input of this comparator is connected to one of the outputs of an oscillator OSC connected to the tags 9, 10 and 11 and capable of delivering a ramp signal RA at the chopping frequency. The first input of this comparator A2 is also connected to the third tag of this control input.

The internal processing means also include a logic unit UL connected on the one hand to the output of the comparator A2 and to the output of the oscillator, this logic unit being connected at the output to buffers BU. The latter are fed via the tag 14, itself connected to the 15 volt supply voltage and to earth via a capacitor C74. They are connected to the tags 16 and 13 of the circuit PWM, thus defining first and second output terminals capable of respectively delivering the first and second base signals SB1, SB2.

The synchronizing signal SYNC controls the grid of a field effect transistor T72 whose source is earthed and whose drain is connected on the one hand to the tag 12 of the circuit PWM and on the other hand, to the 5 volt voltage via a resistor R72.

In general, according to the invention, the two output terminals 16 and 13 of the circuit PWM are connected to the two terminals of the primary winding EP of the coupling transformer TR. However, it is particularly advantageous for the control means to include two current amplifier stages AMC1 and AMC2 having in principle a similar structure and being respectively disposed between the two output terminals 16 and 13 of the circuit PWM and the two terminals of the primary winding of the coupling transformer.

The structure of one of these current amplifiers AMC1 is illustrated in greater detail in Figure 6. The latter includes two complementary field effect transistors T7 and T8 mounted as inverters. The respective drains are interconnected to define the output terminal of this stage, whilst a Zener diode DZ3, to whose terminals there is connected a capacitor C21, connects the respective grids of these transistors in series. The source of the N channel transistor T8 is earthed, whilst that of the transistor T7 is connected to the +15 volt voltage. A filtering capacitor C20 is disposed between the earth and the +15 volt voltage.

Finally, between the grid and the source of the transistor T7, provision is made for a resistor R20 consequently disposed in series with the Zener diode DZ3, and for a diode D20 whose anode is earthed between the grid and the source of the transistor T8. The cathode of this diode D20 also defines the input terminal of this current amplifier stage.

Such an embodiment makes it possible to obtain a fast current amplifier, having a transit time of approximately 15 nanoseconds, capable of delivering a current of 10 amps, at a voltage of +15 volts. The Zener diode DZ3, whose threshold voltage is approximately 5.1 volts, prevents simultaneous transmissions from the two transistors T7 and T8.

The coupling transformer TR comprises on a magnetic core NY, apart from the primary winding EP already referred to, a secondary having a first secondary winding ES1 wound in the same direction as the primary winding EP, as well as a second secondary winding ES2 wound in the opposite direction. The winding direction is here used in relation to the progress direction of the electromagnetic flux through the windings.

It is also preferable for the coupling transformer to include protection means capable of protecting the control signals available at the secondary winding of the transformer, since voltage variation effects occur during the various switching operations of the bidirectional interrupting units. This point will be discussed in greater detail below.

Down the line from the coupling transformer TR, provision is made for two control boxes CM1 and CM2 capable-of respectively controlling the main switches TP1 and TP2 of the bidirectional current-interrupting units. The structure of these control boxes is illustrated in greater detail in Figures 7 and 8.

The first control box CM1, connected to the first secondary b winding ES1 wound in the same direction as the primary winding EP, will now be discussed in greater detail.

The centre point of the secondary winding ES1 is earthed.

The two ends of this secondary winding are connected to two terminals of a bridge of diodes D1-l, D2-1, D3-1, D4-1. The two other terminals of this diode bridge, that is to say, on the one hand, the cathodes of the diodes Dl-l and D3-1 and, on the other hand, the anodes of the diodes D2-1 and D4-1, are respectively connected to the positive electrode of an electrolytic capacitor COl-1 and to the negative electrode of an electrolytic capacitor C02-1. The negative electrode of the capacitor COl-l is earthed in the same way as the positive electrode of the capacitor C02-1. The two ends of the secondary winding ES1 are, moreover, respectively earthed via two filters, each formed by a capacitor in series with a resistor (C3-1, R3-1; C4-1, R4-1).This set of components forms a supply substage SEAL-1 which, con nected to the secondary winding ES1, allows a voltage of +15 volts to be delivered at the level of the positive electrode of the capacitor C01-1 and a voltage of -15 volts at the level of the negative electrode of the capacitor C02-l.

The two terminals of the secondary winding ES1 are, moreover, respectively connected to the anodes of two rectifiers (diodes) D5-1 and D6-1, whose cathodes are connected together so as to constitute the output terminal of a rectifier substage SETR-1.

This rectifier substage is followed by an impedance insulator substage SEIP-1 comprising two bipolar transistors T1-l and T2-1 mounted as inverters. In other words, the bases of these two transistors are together connected on the one hand to earth via a resistor R1-l and on the other hand, to the common terminal of two rectifiers D5-1 and D6-1. The respective emitters of these two transistors are interconnected so as to define the output terminal of this impedance insulator substage. Finally, the collector of the P channel transistor Tl-1 is connected to the +15 volt power supply, whilst the collector of the other N channel transistor is earthed.

The control box comprises moreover a level translator substage SETN-1. The latter includes firstly a resistor R51 connected in parallel to the terminals of a capacitor C71, the set of these two components being connected to two emitters of the two transistors T1-l and T2-1. This terminal will be designated below under reference 0. The other terminal of this set of components R5-1 and C7-1 is connected to the anode of a diode D7-1 whose cathode is connected to the +15 volt terminal.

This level translator substage includes secondly another capacitor C8-1 connected to the terminal 0. The other terminal of this capacitor C8-1 is connected to the -15 volt terminal, on the one hand via a resistor R6-1 and, on the other hand, via a diode D8-1 (the anode of this diode being connected to the -15 volt terminal).

Finally, the control box includes a final control substage SECF-1 connected to the output of the level translator substage.

This final control substage includes two complementary main field effect transistors T5-1 and T6-1 whose respective drains are interconnected to form the output terminal of this control box. The respective sources of these two transistors are respectively connected to the +15 volt and15 volt terminals. These two main transistors mounted as inverters are respectively controlled by two complementary auxiliary field effect transistors T3-1 and T4-1 themselves mounted as inverters. In other words, the drain of each auxiliary transistor is connected to the control grid of the main transistor of the same channel (T3-1, T5-1; T4-1, T61). The source of each auxiliary transistor is connected to the same voltage terminal as that connected to the source of the main transistor of the same channel.Moreover, the respective drains of these two auxiliary transistors T3-1 and T4-1 are interconnected via a resistor R2-1 in series with a Zener type rectifier DZ2-1 to whose terminals there is connected a capacitor C2-1.

The control grid of the P channel transistor T3-1 is connected to the anode of the diode D7-1 of the level translator substage. As regards the grid of the N channel transistor T4-1, it is connected to the cathode of the diode D8-1 of the level translator substage via a resistor R9-1 to whose terminals is connected another diode D9-1 mounted in a reverse configuration as compared with the diode D8-1.

Finally, provision is made for two isolating capacitors ClO- 1 and Cl 1-1 respectively disposed between the earth and the respective sources of the auxiliary transistors T3-1 and T41.

It will be seen below that this control box CMl is capable of controlling the corresponding main switch on the basis of a rectified signal comprising a succession of pulses at the level of +15 volts. On the other hand, the control box CM2 is capable of controlling the other main switch on the basis of a rectified signal comprising a succession of pulses at the level of -15 volts.

Consequently, although having a structure similar to the first control box, the second control box CM2 comprises some modifications. The constituent elements of this control box that are similar or have similar functions to those of the first control box bear references assigned the suffix 2.

Here only the differences between these two control boxes will be described.

The respective anodes of the two rectifiers D5-2 and D6-2 of the rectifier substage SETR-2 are this time interconnected to define its output terminal whilst the cathodes of these two rectifiers are respectively connected to the two ends of the secondary winding ES2.

The collector of the transistor T1-2, that is to say, the P channel transistor, is in this case earthed, whilst the collector of the N channel transistor T2-2 is connected to the -15 volt supply terminal.

The resistor R5-2 of the level translator substage is now connected in parallel to the terminals of the diode D7-2, whilst the resistor R6-2 is in this case connected in parallel to the terminals of the capacitor C8-2.

The structure of the circuit module MCOM will now be discussed in greater detail.

As has already been partly set out from a general point of view, according to the invention the first bidirectional current-interrupting unit includes a controllable first main switch TP1 connected to the first primary terminal of the circuit module and having a state for blocking the current and a passing state here permitting the current coming from the first input terminal BE1 (V+ voltage) to pass.

Provision is also made for a first auxiliary switch connected in parallel to the terminals of the main switch and capable of permitting a current to pass towards the first input terminal and to block flow of current in the other direction.

In practice, the first main switch includes: - a VMOS technology N channel field effect power transistor, such as that marketed by the UNITED STATES INTERNATIONAL RECTIFIER Company under reference IRF360, and whose drain is connected to the first input terminal, and - an additional first diode D30 whose anode is connected to the source of the transistor.

The first auxiliary switch is here a first auxiliary diode D31 mounted in reverse as compared with the passing direction of the current in the transistor TP1, that is to say whose cathode is connected to the first input terminal and whose anode is connected to the cathode of the additional diode D30.

Similarly, the second bidirectional interrupting unit I2 includes a second controllable main switch TP2 connected to the second primary terminal and having a current blocking state and a passing state here allowing the current to pass towards the second input terminal. Provision is also made for a second auxiliary switch connected in parallel to the terminals of the second main switch and being capable of allowing current coming from the second input terminal to pass and to block the flow of current in the other direction.

In practice, the switch TP2 is also a VMOS technology N channel field effect power transistor, for example, the same as the transistor TP1, whose source is connected to the terminal BE2. It is associated with a second additional diode D40 whose cathode is connected to the drain of the transistor TP2. The second auxiliary switch is a diode D41 mounted in reverse as compared with the passing direction of the current in the transistor TP2. In other words, the anode of the diode D41 is connected to the terminal BE2, while the cathode is connected to the anode of the diode D40.

The control grids of the two transistors TP1, TP2 are respectively connected to the output terminals of the corresponding control box whilst the sources of the transistors TP1, TP2 are connected to the -15 V input voltage. Moreover, two resistive-capacitive filters FC1, FC2 are respectively disposed between the grids and sources of the two transistors TP1, TP2.

The circuit module moreover very advantageously includes current inertia means capable of acting on the variation of the level of the current circulating in at least some of the switches of the bidirectional interrupting units during the switching.

In practice, these current inertia means include an inductive circuit comprising a first and a second auxiliary inductor L1, L2 disposed in series. The first auxiliary inductor L1 is connected to the cathode of the first additional diode D30, whilst the second inductor L2 is connected to the anode of the second additional diode D40.

The common terminal of the two inductors L1 and L2 here define the secondary terminal BSS of the circuit module connected to one of the terminals of the inductor LF of the wave filter.

It is then preferable to make provision for a resistor RP connected in parallel to the terminals of this inductive circuit, that is to say, connected between the cathode of the diode D30 and the anode of the diode D40. This crucial parallel resistor damps the inductive circuit to prevent the occurrence of an oscillating system constituted by the auxiliary inductors and the stray capacitances inside and outside the inductors.

The current inertia means are advantageously associated with voltage clipper means here including a first voltage limiter circuit ECR1 comprising a set of a plurality of diodes in parallel D50-1, the cathodes whereof are connected to the first primary terminal BP1 of the circuit module, hence to the V+ input terminal.

This voltage limiter circuit ECR1 includes - a Zerier diode DZ5-1 with a chosen threshold mounted in reverse as compared with the diodes D50-l, is disposed in series between the anodes of these diodes D50-1 and the anode of the second additional diode D40, and - a capacitor C50-1 connected in parallel to the terminals of the Zener diode.

A second voltage limiter circuit ECR2, with a structure similar to the voltage limiter circuit ECR1 is disposed between the primary terminal BP2 and the cathode of the first additional diode D30. This second voltage limiter circuit differs from the first by the mounting direction of the various diodes D50-2 and of the Zener diode DZ50-2.

Finally, provision is made within the voltage converter block for an auxiliary capacitor COO disposed between the first and second input terminals and whose function will be explained below.

The metallic screens ECS1 and ECS2 belonging to the protection means already referred to above and contained in the coupling transformer TR are schematically represented in Figure 5 by dashes. In practice, the primary winding EP of this coupling transformer is wound first of all on the magnetic core NY. The first metallic screen ECS1 connected to the source of the transistor TP1 is disposed round this primary winding. The first secondary winding ES1 is wound round this first screen whilst the second metallic screen ECS2, connected to the second input terminal of the converter block, that is to say, in this case the voltage V-, is disposed round the first secondary winding. The second secondary winding ES2 is then wound round this second metallic screen.

Reference will now be made to Figures 5 and 9 to describe the safety assembly CDS in greater detail.

This safety assembly includes, first of all, means MDEC capable of determining the current level at the output of the converter block. These means are, in practice, disposed down the line from the wave filter.

They include a subsidiary transformer TI having, on a magnetic core: a a primary winding EPTI connected in series between the common terminal of the inductor LF and the capacitor CF of the wave filter and the output terminal BS1.

* a secondary winding wound in the same direction as the primary winding whose centre point 2 is earthed. Thus between one of the end terminals of this secondary winding and the centre point there is a subsidiary voltage +VL which is connected to the current passing through the primary winding and therefore the inductor LPF. The opposite subsidiary voltage -VL is available between the other end terminal and the centre point, subject to the observation that the term "opposite" here means in phase opposition. It is here assumed that the subsidiary voltage is available between the terminals 1 and 2 and that the opposite subsidiary voltage is available between the terminals 2 and 3.

The short circuit means MCC include: - a first subsidiary comparator A82 whose reversing input is connected to the terminal 1 of the secondary winding EST1 delivering the subsidiary voltage +VL, and whose other input is capable of receiving a short circuit voltage threshold MAXCC here taken to be equal to approximately 700 millivolts, and, - a second subsidiary comparator A83 whose nonreversing input is connected to the terminal 3 of the secondary winding delivering the opposite subsidiary voltage -VL and whose other input is capable of receiving the short circuit voltage threshold MAXCC.

The outputs of these two comparators A2 are joined together to deliver a subsidiary control signal to the emitter of a unijunction transistor T90. One of the two bases of this transistor is connected to earth via a capacitor C90 and also to the third terminal of the secondary winding ESTI, that is to say, the one that is capable of delivering the opposite subsidiary voltage -VL. The other base of this unijunction transistor is connected to the common terminal of a resistor R91-capacitor C91 set. The other terminal of the resistor R91 is earthed whilst the other terminal of the capacitor C91 is connected to the third tag of the pulsewidth modulation circuit PWM.

The excess current means MSI include: - a third subsidiary comparator A80 whose reversing input is connected to the terminal 1 of the secondary winding ESTI and whose other input is capable of receiving a short circuit voltage threshold MAXS chosen for example, at approximately 400 millivolts, and - a fourth subsidiary comparator A81 whose nonreversing input is connected to the third terminal of the secondary winding ESTI whose other input is capable of receiving the short circuit voltage threshold.

The outputs of these two comparators are joined together for delivering to the generator GEN an excess current message ISI of the reference voltage Vref, the use of which will be seen below.

The operation of the device will now be described in detail with reference first of all to Figure 10 which illustrates in particular the characteristics of the base signals generated by the width modulation circuit PWM, taking into account the desired control code, as well as those of the final control signals delivered to the power transistors TP1 and TP2.

In this example, it is assumed that the output voltage VS is a sinusoidal voltage with a nominal frequency equal to approximately 400 Hertz and with a peak-to-peak amplitude equal to approximately 315 effective volts.

The reference voltage Vref is then a sinusoidal voltage with a nominal frequency of 400 Hertz with a peak-to-peak amplitude approximately equal to 2 volts.

It is also assumed that the converter block is operating under steady conditions delivering the desired output voltage VS chopped to the chopping frequency of 100 kilohertz according to the control code LC whose three cycles CY1, CY2, CY3 are given by way of example on the first diagram of Figure 10.

The attenuation means ATT provide, from the output voltage VS on the tag 2 of the circuit PWM, the auxiliary voltage VA which is also sinusoidal, and with a peak-to-peak amplitude approximately also equal to two volts. However, because of the time lags engendered by the various components of the converter block, this auxiliary voltage VA is temporally delayed in relation to the reference voltage Vref.

In general, the internal processing means of the circuit PWM are capable of generating the first and second base signals SB1 and SB2 from an image voltage of the desired output voltage but at an attenuated level as compared with that desired for this output voltage.

In a first operating state corresponding to the absence of a short circuit at the output of the converter block CV, the image voltage is the reference voltage Vref. It will be seen below that this is not the case when there is a short circuit.

The compensation signal at the output of the error amplifier AE is, because of the phase shift between the auxiliary voltage and the reference voltage, a sinusoidal signal which is also an image of the desired output voltage. The comparison of this compensation signal with the ramp generated at the chopping frequency by the oscillator OSC will enable the logic unit to deliver to the tags 16 and 13 respectively of the circuit PWM the first and second base signals SB1 and SB2 illustrated in the second and third diagrams of Figure 10.

Thus the first base signal SB1 comprises in general a first succession of the first pulses IMP1 at a higher level (here +15 volts), generated every other cycle of the control code (here during the first cycle CYl and the third cycle CY3) and having periods corresponding to the first segment SG1 of these cycles. The first base signal is at a base level (here 0 volts) between the pulses.

b In the same way, the second base signal SB2 comprises a second succession of the second pulses IMP2 at the upper level (here +15 volts) also generated every other cycle of the control code. However, these cycles are temporally offset by the chopping frequency in relation to the cycles generating the first pulses. In other words, here the second pulses are generated during the second cycle CY2, then during the fourth cycle and so on. These second cycles also have periods corresponding to the first segment of their generating cycle and the second base signal is also at the base level (0 volts) between the second pulses.

After amplification in the amplifier stages AMC1 and AMC2, the primary winding EP of the coupling transformer TR is traversed by a primary control signal SCP, illustrated in the fourth diagram of Figure 10, which is the difference between the two base signals SB1 and SB2.

This primary control signal SCP consequently includes a succession of primary pulses IMPP derived from the first and second pulses IMP1, IMP2. Thus these primary pulses are generated at each cycle of the control code and are alternately at the upper level (+15 volts) and at a lower level (-15 volts) in symmetry with the upper level in relation to the base level. These primary pulses are moreover interspaced by primary time intervals INTP corresponding to the second segment of the cycles and during which the primary control signal is at the base level (+0 volts).

On the basis of this primary control signal, the first secondary winding ES1 delivers a first secondary control signal SCS1 (illustrated in the fifth diagram on the left of Figure 10) comprising a succession of first secondary pulses IMPS1 interspaced by the first secondary time intervals INTS1. These first pulses and first secondary time intervals correspond temporally to the pulses and primary time intervals respectively of the primary control signal SCP.

The second secondary winding ES2 similarly delivers a second secondary control signal SCS2 (illustrated in the fifth diagram on the right of Figure 10) which is inverted in relation to the first secondary control signal SCS1. In other words, the second secondary pulses IMPS2 of this secondary control signal SCS2 are inverted in relation to the first secondary pulses IMPS1 of the first secondary control signal SCS1, that is to say, they have a level that is in symmetry with the level of the corresponding pulse in relation to the base level.

When the secondary control signal is received by the power supply substage SEAL-1 of the corresponding control box it allows it to maintain two control voltages of opposite levels here equal to +15 volts and -15 volts by means of the diode bridge and the electrolytic capacitors.

Each rectifier substage is then capable of delivering an intermediate signal rectified as compared with the corresponding secondary control signal. This rectified signal includes a succession of intermediate pulses corresponding respectively to the secondary pulses of the corresponding secondary control signal. Since all the intermediate pulses of one of the rectified signals are at the upper level, while all the intermediate pulses of the other intermediate signal are at the lower level, each intermediate signal is at the base level between the intermediate pulses.

In concrete terms, the rectifier substage SETR-1 of the control box CM1 delivers the rectified intermediate signal SRI1 (sixth diagram, on the left of Figure 10) comprising a succession of intermediate pulses IMPI1 all at the +15 volt level, the signal SRI1 being at the 0 volt level between the pulses In the same way, the intermediate signal SRI2 rectified by the rectifier substage of the second control box CM2 is consequently inverted as compared with the signal SRI1, that is to say, it comprises a succession of intermediate pulses IMPI2 all having the - 15 volt level.

If more particular attention is now paid to the first control box CM1, it will be seen that in the presence of a pulse IMPI1 at the input of the substage SEIP1, the transistor T1-1 is conductive whilst the transistor T2-1 is blocked. Consequently, a pulse level of +15 volts is present at the 0 terminal of this box. The capacitor C7-1 is being charged which has the effect that the transistor T3-1 is subjected to a grid-source voltage which is lower than the conducting threshold. This transistor T3-1 is therefore blocked. Consequently, the grid-source voltage of the transistor T5-1 is greater than the conducting threshold. This transistor T5-1 therefore becomes conductive and supplies at its output a level of +15 volts.

Simultaneously with the conduction of the transistor T5-1, the chain of components C8-1 to T4-1 will contribute to the blocking of the transistor T6-1.

In the presence of a level of 0 volts at the input of the substage SEIP-1, the transistor Tl-l is blocked, whilst the transistor T2-1 becomes conductive. This leads to a level of +0 volts at the terminal 0 of the box CM1. Consequently, the capacitor C7-1 is being discharged via the resistor R51, which leads to a voltage drop in the vicinity of the grid of the transistor T3-1 and consequently to a grid-source potential difference of the same transistor, which is greater than the conducting threshold. The transistor T3-1 thus becomes conductive, delivering a +15 volt level to the control grid of the transistor T5-1 which has the effect of blocking it.

Simultaneously with the blocking of the transistor T5-1 and in a way similar to that described above, the transistor T61 becomes conductive and supplies at its output a level of15 volts.

If required, the expert will know how to adjust the time constants of the resistor-capacitor circuits in accordance with the chopping frequency.

The expert will also understand that the Zener diode DZ2-1 prevents a simultaneous conduction of the two field effect transistors T5-1 and T6-1.

There is thus obtained, at the output of this control box CM1, a first control signal SCF1 illustrated in the seventh diagram on the left of Figure 10.

In general, this first final control signal has a succession of first final pulses IMPFl-l and IMPF1-2 having, during the first segment of each cycle, a first control level for conferring to the first main switch one of its blocking and passing states, and during the second segment of each cycle, a second control level for conferring its other state to the first main switch.

The assembly here obtained makes it possible to obtain from the first and second pulse levels, values that are substantially opposed and are here respectively equal to +15 volts and -15 volts.

The expert will observe that the first final pulses IMPFl-l correspond respectively to the first secondary pulses IMPS1 of the signal SCS1, whilst the first final pulses IMPF1-2, having the level of -15 volts, correspond respectively to the first secondary intervals INTS-1 of the signal SCS-l.

In a similar way there is obtained, at the output of the second control box CM2, a second final control signal SCF2 drawn from the second secondary control signal and having in general a succession of the second final pulses IMPF2-1 and IMPF2-2 having, during the first segment of each cycle, a third control level for conferring to the second main switch one of its blocking and passing states in opposition to that conferred to the first main switch and, during the second segment of each cycle, a fourth control level for conferring its other state to the second main switch.

There again, the third and fourth levels have values that are substantially opposed and are moreover respectively equal to the second and first levels.

The expert will here again observe that the second final pulses IMPF2-2 at the +15 volt level, correspond respectively to the second secondary time intervals INTS2 of the second secondary control signal SCS2, whilst the second final pulses IMPF2-1, at the -15 volt pulse level respectively correspond to the second secondary pulses IMPS2 of the second secondary control signal.

In conclusion, during the first segment of the cycles CY1 CY3, the field effect transistor TP1 is conductive whilst the transistor TP2 is blocked. During the second segment, the opposite is the case.

Thus the control code allowing the sinusoid to be reconstituted is duly encountered again.

The coupling transformer TR ensures the electric insulation between the control boxes CMi and the field effect trans is tors TP1 and TP2 on the one hand, and the width modulation circuit PWM on the other hand. Thus, this provides the correct control of the field effect transistors TP1 and TP2 on the basis of the base signals varying between 0 and 15 volts by means of the square waves varying between -15 volts and +15 volts, and in particular of the transistor TP1, the potential of whose source is floating and may here vary by 300 volts.

Moreover, the arrangement of the control boxes allows a generator of voltages +15 volts and -15 volts to be obtained having a very low output impedance providing very fast charging of the input capacitors of the power transistors and therefore their fast switching.

Moreover, the fact that a final control signal is delivered having pulses at a level of -15 volts offers good immunity in relation to the strays introduced into the set-up and therefore makes it possible to achieve the blocking state of these field effect transistors TP1 and TP2 in a reliable manner.

The applicant has, moreover, observed that the arrangement of these control means taken in conjunction with the special characteristics of the base signals SB1 and SB2 permitted the transmission through the coupling transformer TR of a control code LC having a succession of cycles at the chopping frequency, here 100 kilohertz, modulated in width with a low frequency, that is to say, in this case 400 Hertz without deformation of the shape of the pulses generated during each cycle.

Finally, it has also been observed that the presence of the metallic screens within this transformer TR made it possible to prevent the deformation of the control signals occasioned by considerable voltage variations (here of the order of 14 volts per nanosecond.) occurring during the switching of the transistors TP1 and TP2.

The operation of the circuit module MCOM will now be discussed in greater detail.

For this purpose it is here assumed that the load connected at the output of the converter block is a resistive load.

When, during the reconstruction of the positive half cycle of the sinusoid, the transistor TP1 is in its passing state, an increasing current IL flows from the V+ input terminal towards the output terminal successively through the diode D30, the first auxiliary inductor L1 and the inductor of the wave filter LF. The transistor TP1 is then blocked.

During the following cycle, the transistor TP1 is in its blocking state and the transistor TP2 is in its passing state. The current IL flows in the same direction while decreasing from the V- terminal towards the output successively through the diode D41, the second inductor L2 and the inductor LF.

During the following cycle, when the transistor TPl returns to its passing mode and with the transistor TP2 blocked, a short circuit occurs for a short space of time between the two input terminals because of the recovery time of the diodes, since the transistor TP1 becomes passing while the diode D41, not yet blocked, is still conductive. This results consequently in an a considerable variation in the current level flowing in the diodes D30, D41, and in the transistor TP1. The function of the inductive circuit L1, L2 is then to limit this variation of the level of the current, and thus to prevent a deterioration of the components.

The expert will know how the characteristics of the current inertia means should be adapted to ensure according to the application that a variation of the current level is compatible in particular with the characteristics of the transistors TP1 and TP2, as well as of the diodes D30, D31, 0 D40 and D41. The applicants have here chosen a value of 1.5 microhenry for each auxiliary inductor.

Correspondingly, when the diode D41 becomes blocked, a considerable excess voltage is created at the terminals of the transistor TP2 and of the diode D41 occasioned by the presence of the inductive circuit L1, L2. It is then the function of the limiter circuit ECR1 to limit this excess voltage to an acceptable level to ensure that the components are not destroyed. This level is here fixed at 20 volts.

During the reconstitution of the negative half cycle of the sinusoid and still under the hypothesis of a resistive load at the output, the current will flow when the transistor TP1 is passing from the V+ input terminal towards the output through the diode D31 and the first inductor L1. When this transistor is blocked, and the transistor TP2 is passing, the current will flow this time from the output terminal towards the terminal BE2 through the inductor LF, the inductor L2, the diode D40 and the transistor TP2.

The short circuit phenomenon referred to above will then occur, causing the diodes D40 and D31 to operate and the excess voltage phenomenon will then be channelled via the second limiter circuit ECR2.

The converter block can also function with a reactive load at the output. As regards the direction of the currents, the operation with such a load is, during the reconstitution of the positive half cycle of the sinusoid, similar to that of the reconstitution of a negative half cycle in the case of a resistive load and, in the case of the reconstitution of a negative half cycle, it is similar to that described with regard to a resistive load in the case of the reconstitution of a positive half cycle. Thus the converter can absorb energy via its output and restore it to the capacitor COO.

Moreover, the function of the capacitor COO disposed between the two input terminals of the converter block is also to absorb the drops of the input voltage during the switching and thus, as it were, to form an energy reservoir.

The choice of values for the inductors LF and the capacitor CF of the wave filter results from a compromise between the powers of the converter block on the one hand and its bulk on the other hand. Thus, for example, the lower the value of the inductance LF, the lower is the time constant of the reaction loop, but the current ripples in the inductor LF are the greater (the chopping frequency being equal).

Moreover, the higher the value of the capacitance, the lower the rate of ripples at the chopping frequency, but the greater is its bulk with an increasing capacitive current.

The expert will know how to adapt the inductance and filtering capacity values to each particular case. Here the applicants have deemed it desirable to adopt the values of 65 microhenry for the LF and 5 microfarad for the CF.

Such a converter block thus makes it possible to deliver the sinusoidal output voltage described above with a nominal current of 9 effective amps, that is to say, a power of 1 kilowatt with an efficiency of the order of 92 t.

Generally speaking, the converter block in accordance with the invention has the advantages set out below, apart from those already referred to: - a low output impedance; thus a load disposed at the output of this converter block absorbing a current having harmonics does not entail any substantial modification of the shape of the output voltage VS. In other words, the rate of the voltage distortion is very low.

- The space requirement of such a converter block is very small, typically of the order of one litre. That of a group of three converter blocks delivering a power of 2 kilowatts would be of the order of two litres.

- As has already been stated, the converter block is capable of functioning in the energy-receiving mode, for example, in the case of a reactive load connected at its output.

In order to prevent saturation of the amplifiers, when the converter block is being energized the level of the reference signal increases progressively from the zero value up to its nominal value which allows the value of the output voltage to be established progressively.

In the presence of an output current of the converter block revealing an excess current at the load level, the excess current means MSI then deliver the message ISI to the generator of the reference voltage Vref which has the effect of reducing the level of this reference voltage so as to reduce the voltage level at the output. The level of the reference voltage will then be lowered until the voltage level obtained at the output (which may possibly be virtually zero) leads to a delivered current that remains in the lower zone of the excess current threshold.

It will thus here be observed that the operation of the converter block under excess current conditions goes against a preconceived idea lying in the affirmation that the converter block must provide the higher current absorbed by the load causing the excess current. On the contrary, here the current will be indeed maintained just within the reference threshold possibly with a zero voltage. In other words, the converter block is capable of supplying a b considerable current virtually at a zero voltage without incurring an impaired efficiency because of this. Moreover, since the power delivered is virtually zero, the power consumed is also virtually zero and consequently the converter block can thus operate over a considerable period without excessive heating.

The expert will, moreover, observe that the particular arrangement of the two comparators A80 and A81 allows an excess current to be detected both on a positive half cycle as well as a negative half cycle of the sinusoid. Of course, when the excess current disappears, the reference signal Vref is again generated at its nominal level.

The converter block in accordance with the invention also makes it possible, in the presence of a short circuit in a load connected at the output of the converter, to provide a massive current without excessive heating. Its operation in this short circuit state will now be described.

It will be observed that when the pulse width modulation circuit is in its first state, the mean value of the compensation signal at the output of the error amplifier AE is stored in the capacitor C91 of the short circuit means MCC. This mean value corresponds to a cyclic ratio of 50%, that is to say, to an equal period of the first and second segments within each cycle.

When a short circuit current is detected by the two comparators A82 and A83 (this detection being possible, as in the case of the excess current means1 both in a positive half cycle and in a negative half cycle) the short circuit means MCC apply, by means of the transistor T90, to the tag 3 of the width modulation circuit PWM a direct voltage whose level is equal to the algebraic sum of the mean level stored in the capacitor C91 and of the level of the opposite subsidiary voltage -VL just before the short circuit and which was stored in its capacitor C90. Since the error amplifier AE is a transconductance amplifier, the presence of this direct voltage on the tag 3 of the control input of the circuit PWM is effectively imposed on the input of the comparator A2. This direct voltage is then the image voltage of the desired output voltage.Indeed, although the voltage at the output of the converter block is zero, because of the occurrence of a short circuit, one here seeks to impose a voltage opposite to that applied to the inductor LF just before the short circuit so as to produce a decrease of the current which had reached a high value at the moment of the short circuit.

More particularly, if the short circuit occurs when the output voltage VS was practically at its intermediate level Vi, that is to say, corresponding to a cyclic ratio of 50%, there is added to the mean value of the compensation signal stored in the capacitor C9l a virtually zero voltage which effectively leads to the preservation of a cyclic ratio of 50% so as to maintain the output voltage at the intermediate level.

On the other hand, if the short circuit occurs when the output voltage VS is practically at the level of its maximum peak (the crest of a positive half cycle) there is added to the mean value stored in the capacitor C91 a voltage having the opposite maximum peak value level (the crest of a negative half cycle).

After the operation of the short circuit means, the potential difference at the terminals of the inductor LF is zero, the cyclic ratio is maintained at 50% and the current provided is maintained, after decreasing just within the fixed short circuit threshold.

Here too, the operation of the converter block in the short circuit mode goes against a preconceived idea which is to stop all operations in the presence of a short circuit.

Here, on the contrary, a massive current is indeed provided by the converter block CV allowing the fuses of the load subjected to the short circuit to be destroyed.

Of course, when a short circuit is eliminated, the converter block reverts to its normal operation. This is particularly worthwhile when several loads are connected at the output of the converter block. Thus the converter block will pass into the short circuit mode when one of these loads does indeed reveal a short circuit, and when the short circuit has disappeared (for example, by the destruction of the fuses of the load), the converter block will continue to feed the other loads in the normal way.

The applicants have also observed that in certain cases it was possible to increase the power which the converter block was capable of providing. Thus when the desired output voltage V is a sinusoidal voltage, it is particularly advantageous to add to the corresponding sinusoidal reference voltage a third harmonic sinusoidal voltage whose amplitude is approximately equal to 1/6 of the amplitude of the fundamental frequency of the reference signal. One thus obtains an increase of approximately 15% of the power delivered.

The invention is not limited to the embodiment described above but does encompass all the variants contained within the scope of the claims set out below.

It is thus possible to provide output voltages with different characteristics having for example, the shapes of square, rectangular, or triangular waves even a direct output voltage by a suitable adaptation of the control code.

As has already been partly set out above, it is possible to couple several converter blocks in accordance with the invention so as to provide an overall two-phase, threephase, or multiphase output voltage.

In certain applications requiring high switching powers, it may be envisaged that the main switches include a plurality of power transistors mounted in parallel and associated with a plurality of auxiliary and additional diodes.

Other components could be used as switches according to the power and frequency constraints of the envisaged chopping requirements. Thus bipolar transistors may, for example, be considered in particular for lower chopping powers and frequencies.

Of course, some of the means described above may be omitted in the variants where they serve no useful purpose.

Claims

1. A voltage converter device including a converter block comprising: an input for a substantially direct input voltage comprising a first and a second input terminal; an output comprising a first and a second output terminal for delivering an output voltage between these terminals with the desired characteristics; a circuit module having first and second primary terminals respectively connected to the first and second input terminal and a secondary terminal, and comprising a first controllable bidirectional current-interrupting unit disposed between the first primary terminal and the secondary terminal, and a second controllable bidirectional currentinterrupting unit, disposed between the second primary terminal and the secondary terminal;; control means capable of controlling the two interrupting units simultaneously and in opposition to each other in accordance with a control code linked to the desired characteristics of the output voltage and comprising, according to a chopping frequency, a succession of cycles of an identical duration; and a wave filter including an inductor disposed between said secondary terminal of the circuit module and one of said output terminals, as well as a capacitor disposed between the two output terminals, said wave filter having a cut-off frequency chosen in accordance with said chopping frequency.

2. A device according to claim 1, wherein the output voltage is a periodic voltage of a chosen frequency, and the chopping frequency is at least equal to 100 times said chosen frequency.

3. A device according to claim 1 or 2, wherein the first interrupting unit includes a controllable first main switch connected to the first primary terminal and having a current blocking state as well as a passing state; wherein the second interrupting unit includes a controllable second main switch connected to the second primary terminal and having a current blocking state as well as a passing state; wherein each cycle of the control code is subdivided into a first segment and second segment respectively having cyclic ratios modulable in accordance with the desired characteristics of the output voltage; and wherein the control means are capable of during the first segment, assigning to the first main switch one of its blocking and passing states and assigning to the second main switch one of its blocking and passing states in opposition to that assigned to the first main switch and during the second segment respectively assigning their other state to the first and second main switches.

4. A device according to claim 3, wherein the control means include:- a pulse-width modulation circuit having a control input capable of receiving an image voltage of the desired output voltage at an attenuated level as compared with that desired for the output voltage, internal processing means, connected to the control input, and capable of generating the first and second base signals from the image voltage, a first output terminal capable of delivering the first base signal, and a second output terminal capable of delivering the second base signal;; a coupling transformer having, on a magnetic core, a primary winding whose two terminals are each connected to the two output terminals of the pulse-width modulation circuit, and a secondary comprising a first secondary winding wound in the same direction as the primary winding for delivering a first secondary control signal, and a second secondary winding wound in the opposite direction for delivering a second secondary control signal;; a first control box connected to the first secondary winding for delivering to the first main switch a first final control signal derived from the first secondary control signal and possessing a succession of first final pulses Saving, during the first segment of each cycle, a first control level for assigning to the first main switch one of its blocking and passing states and, during the second segment of each cycle, a second control level for assigning to the first main switch its other state; and a second control box connected to said second secondary winding for delivering to the second main switch a second final control signal derived from the second secondary control signal and possessing a succession of second final pulses having during the first segment of each cycle a third control level for assigning to the second main switch one of its blocking and passing states in opposition to that assigned to the first main switch and during the second segment of each cycle, a fourth control level for assigning to the second main switch its other state.

5. A device according to claim 4, wherein the first and second levels have substantially opposite values, and the third and fourth levels are respectively equal to the second and first levels.

6. A device according to claim 4 or claim 5, wherein the first base signal comprises a first succession of first pulses at an upper level of generated every other cycle of the control code and having periods corresponding to the first segment of these cycles, this first base signal being at a base level between the first pulses; and wherein in the second base signal comprises a second succession of second pulses at the upper level also generated every other cycle of the control code, these cycles being temporally offset by the chopping frequency period in relation to the cycles generating the first pulses, these second pulses having periods corresponding to the first segment of their generating cycle, and this second base signal being at the base level between the two pulses.

7. A device according to claim 6, wherein the primary winding is traversed by a primary control signal which is the difference between the two base signals; wherein the primary control signal comprises a succession of primary pulses derived from the first and second pulses of the two base signals and generated at each cycle of the control code, these primary pulses being alternately at said upper level and at a lower level in symmetry with the upper level in relation to the base level and being interspaced by primary time intervals corresponding to the second segment of the cycles and during which the primary control signal is at the base level; wherein the first secondary control signal comprises a succession of first secondary pulses interspaced by the first secondary time intervals corresponding temporally respectively to the primary pulses and time intervals; and wherein the second secondary control signal comprises a succession of second secondary pulses interspaced by the second secondary time intervals corresponding temporally respectively to the primary pulses and intervals, these second secondary pulses being inverted in relation to the first secondary pulses of the first secondary control signal.

8. A device according to claim 7, wherein the first final pulses of the first final control signal, having said first control level, correspond respectively to the first secondary pulses of the first secondary control signal, whilst the first final pulses having the second control level correspond respectively to the first secondary intervals of the first control signal; and wherein the second final pulses of the second final control signal, having the fourth control level, correspond respectively to the second secondary time intervals of said second secondary control signal, whilst the second final pulses having the third level correspond respectively to the second secondary pulses of said second secondary control signal.

9. A device according to any one of claims 4 to 8, further comprising a generator capable of generating a reference voltage corresponding to the desired output voltage at an attentuated level as compared with that desired for the output voltage; wherein the control means comprise attenuation means connected to the output of the converter block, capable of receiving the output voltage and of delivering a corresponding auxiliary voltage having an attenuated level as compared with that of the output voltage; wherein the pulse-width modulation circuit has a first operating state wherein the image voltage is the reference voltage; wherein the control input of the pulse-width modulation circuit also receives the said auxiliary voltage; and wherein the internal processing means of the pulse-width modulation circuit includes an amplifier capable of receiving the reference voltage and the auxiliary voltage for delivering a first compensation signal, from which the two base signals will be generated.

10. A device according to any one of claims 4 to 9, wherein the control means include means for determining the current level at the output of the converter block.

11. A device according to claim 10, wherein the means for determining the current levels include a subsidiary transformer having, on a magnetic core: a primary winding disposed in series between (i) the common terminal of the inductor and the capacitor of the wave filter and (ii) one of the output terminals, and a secondary winding wound in the same direction as the primary winding whose centre point is earthed, and whose two end terminals are respectively capable of delivering a subsidiary voltage representing the current at the output of the converter block and the subsidiary opposite voltage.

12. A device according to claim 10 or claim 11, wherein the control means include short circuit means which are capable of comparing the level of the current at the output with a predetermined short circuit level and, in the presence of a level higher than said level revealing the occurrence of a short circuit at the output of the converter block, capable of delivering to the control input of the pulse-width modulation circuit a chosen compensation voltage; and wherein, in the presence of this compensation voltage, the pulse-width modulation circuit has a second operating state wherein the image voltage is said compensation voltage.

13. A device according to claims 11 and 12 taken together wherein, when the pulse-width modulation circuit is in its first state, the short circuit means are capable of storing the mean value of the first compensation signal; and wherein said compensation voltage is a direct voltage whose level is equal to the algebraic sum of said mean value of the first stored compensation signal and of the level of the subsidiary opposite voltage stored during the first operating state of the pulse-width modulation circuit.

14. A device according to claim 13, wherein the short circuit means include : a first subsidiary comparator whose one input is connected to the terminal of the subsidiary secondary winding delivering the said subsidiary voltage, and whose other input is capable of receiving a short circuit voltage threshold corresponding to said short circuit level; a a second subsidiary comparator whose input, homologous to that of the first comparator receiving the short circuit threshold voltage, is connected to the terminal of the subsidiary secondary winding delivering said opposite subsidiary voltage and whose other input is capable of receiving said short circuit voltage threshold, the outputs of said first and second subsidiary comparators being joined together for delivering a subsidiary control signal;; a first subsidiary capacitor whose first terminal is earthed via a first subsidiary resistor, and whose second terminal is connected to the control input of the pulsewidth modulation circuit, said first subsidiary capacitor being capable of storing the mean value of the first compensation signal; a second subsidiary capacitor whose one terminal is earthed and whose second terminal is connected to the terminal of the subsidiary secondary winding delivering the opposite subsidiary voltage, said subsidiary second capacitor being capable of storing the opposite subsidiary voltage during the first operating state of the pulse-width modulation circuit; and a subsidiary switch, such as a unijunction transistor, controlled by the subsidiary control signal and capable of connecting the second terminal of the second subsidiary capacitor to the first terminal of the first subsidiary capacitor in the presence of a subsidiary control signal representing a short circuit.

15. A device according to any one of claims 10 to 14, wherein the control means include excess current means capable of comparing the current level at the output of the converter block with a predetermined excess current level and, in the presence of a level higher than the said excess a current level, of delivering to the generator of the reference voltage an excess current signal with the object of reducing the level of the said reference voltage.

16. A device according to claim 15, wherein the excess current means include a third subsidiary comparator whose one input is connected to the terminal of the subsidiary secondary winding delivering the said subsidiary voltage and whose other input is capable of receiving a short circuit voltage threshold corresponding to the said excess current level; and a fourth subsidiary comparator whose input homologous to that of said third subsidiary comparator receiving the excess current voltage threshold is connected to the terminal of the subsidiary secondary winding delivering said subsidiary opposite voltage, and whose other input is capable of receiving said excess current voltage threshold, the outputs of said third and fourth subsidiary comparators being joined together for delivering the excess current signal.

17. A device according to any one of claims 4 to 16, wherein each control box includes a power supply substage connected to the corresponding secondary winding of the coupling transformer, and is capable of providing two control voltages having respective levels equal to the two pulse levels of the final control signal delivered by the corresponding control box.

18. A device according to claim 17 wherein each control box moreover includes: a rectifier stage including two rectifiers, the respective anodes of the two rectifiers of one of the rectifier substages being respectively connected to the two terminals of the corresponding secondary winding of the coupling transformer whilst their respective cathodes are joined together, the respective cathodes of the two rectifiers of the other rectifier substage of the other control box being connected respectively to the two terminals of the other secondary winding of the coupling transformer whilst their respective anodes are joined together; an impedance insulator substage including two complementary transistors mounted as inverters joined to the output of the rectifier substage; a level translator substage connected to the output of the impedance insulator substage; and a final control substage connected to the output of the level translator substage and including two complementary main field effect transistors mounted as inverters, respectively controlled by two complementary auxiliary field effect transistors also mounted as inverters, the two control grids of the two main transistors being joined together via a resistor in series with a Zener type rectifier, whose terminals are joined to a capacitor.

19. A device according to any one of claims 4 to 18, wherein the control means include two current amplifier stages respectively disposed between the two output terminals of the pulse-width modulation circuit and the two terminals of the primary winding of the coupling transformer.

20. A device according to claim 19, wherein each current amplifier stage includes two complementary field effect transistors mounted in a reversing configuration, the a respective grids of these transistors being interconnected by a Zener diode whose terminals are connected to a capacitor.

21. A device according to any one of claims 4 to 20, wherein the coupling transformer includes protection means capable of protecting the secondary control signals from the effects of the voltage variations occurring during the various switching operations.

22. A device according to any one of claims 3 to 21, wherein the first main switch includes at least one field effect power transistor whose drain is connected to the first primary terminal; and wherein the second main switch includes at least one field effect power transistor whose source is connected to the second primary terminal.

23. A device according to claims 21 and 22 taken together, wherein the protection means include in the vicinity of the secondary of the coupling transformer a first metallic screen connected to the source of the first main switch, and a second metallic screen connected to the source of the second main switch.

24. A device according to claim 23, wherein the first metallic screen surrounds the primary winding of the transformer, the first secondary winding being wound round this first screen whilst the second screen is disposed round the first secondary winding.

25. A device according to any one of claims 22 to 24, wherein the first bidirectional switching unit includes a first auxiliary diode mounted in reverse in relation to the passing direction of the current in the corresponding field effect transistor as well as a first additional diode whose cathode is connected to the drain of the transistor; a wherein the second bidirectional switching unit includes a second auxiliary diode mounted in reverse in relation to the passing direction of the current in the corresponding field effect transistor, as well as a second additional diode whose cathode is connected to the drain of the transistor; wherein the circuit module includes: an inductive circuit including first and second auxiliary inductor disposed in series, the first auxiliary inductor being connected to the cathode of the first additional diode, while the second inductor is connected to the anode of the second additional diode, the common terminal of the two inductors being connected to the secondary terminal of the circuit module, a resistor connected in parallel to the terminals of the inductive circuit, a first voltage limiter circuit disposed between the anode of the second additional diode and the first primary terminal, a second voltage limiter circuit disposed between the cathode of the first additional diode and the second primary terminal; and wherein provision is made moreover for an auxiliary capacitor between the first and second input terminals.

26. A device according to any one of the preceding claims, wherein the output voltage is a substantially sinusoidal alternating voltage with a substantially constant amplitude and frequency.

27. A device according to claim 26, wherein the amplitude a of the output voltage is approximately equal to 315 effective volts peak to peak, its frequency is approximately equal to 400 Hertz, the chopping frequency is approximately equal to 100 kilohertz, and the cut-off frequency of the wave filter is approximately 10 kilohertz.

28. A device according to either of claims 26 and 27, wherein the generator is capable of adding to the reference voltage an additional third harmonic sinusoidal voltage whose amplitude is approximately equal to 1/6 of the amplitude of the fundamental frequency of the reference voltage.

29. A device according to any one of the preceding claims.

and including a plurality of converter blocks with a similar structure capable of delivering a plurality of multiphase output voltages.

30. A device according to claim 29, and including three converter blocks with a similar structure capable of respectively delivering three sinusoidal output voltages having substantially equal amplitudes and a substantially equal frequency, but being interspaced by substantially 1200.

31. A voltage convertor device substantially as hereinbefore described with reference to, and as illustrated in, the accompanying drawings.