HK1133335B - Interleaver apparatus and receiver for a signal prodyced by the interleaver apparatus - Google Patents

Description

Interleaver device and receiver for signals generated by an interleaver device

Technical Field

The present invention relates to digital transmission technology, in particular to transmission concepts as can be found in mobile radio and broadcasting, particularly suitable for time-varying transmission channels.

Background

As shown in fig. 6, time interleaving and/or frequency interleaving in combination with error correction codes (forward error correction, FEC) belong to the basic principle of transmission technology.

Here, an information word consisting of information bits is input into an FEC encoder, which builds a code word, i.e. a vector of code symbols or code bits, from the information word. The codewords and/or blocks thus formed are conveyed to an interleaver. The interleaver changes the order of the symbols and delivers the thus mixed symbols onto the transmission channel. The re-classification of the symbols (re-sort) may occur in the time axis ("time interleaving") and/or the frequency axis ("frequency interleaving").

The use of an interleaver is meaningful in case the transmission channel is not static (i.e. in case the characteristics of the transmission channel change over time and/or frequency). Thus, in a moving receiver, the signal power arriving at the receiver may vary strongly. Thus, some code symbols are erroneous with a higher probability (e.g., caused by superimposed thermal noise) than other symbols.

The channel characteristics may change more or less rapidly depending on the movement of the transmitter, receiver and/or objects along the transmission path and depending on the natural environment surrounding the transmitter, receiver and transmission path. The measure of time constancy (temporal constancy) of the transmission channel is the correlation time: during which time the channel does not change significantly.

The probability of transmission errors is typically estimated from the channel conditions. The channel state describes the quality of the received signal (e.g., the instantaneous ratio of signal strength to noise). The purpose of the interleaver is to distribute the information in time (and usually also in frequency) so that the ratio of "good" (low probability of transmission error) to "bad" (high probability of transmission error) symbols after the de-interleaver, which reverses the interleaver on the transmitting side, becomes approximately time-constant on average in the case of time-varying channel characteristics. In case of fast changing channel characteristics (e.g. high carrier speed), a relatively short interleaver is usually sufficient. In case of slow time-varying channel characteristics, a correspondingly larger interleaver length should be selected.

Changes in channel characteristics can have a variety of effects.

In the case of multipath propagation, the relative phase position of the signal portions (contributions) determines whether the signal portions add constructively or destructively. Here, even a small fraction of the wavelength of the carrier signal is changed in position, resulting in other phase positions. The channel characteristics may change rapidly accordingly. This is referred to as "fast fading".

The signal characteristics, however, also depend strongly on the surroundings. Thus, for example, walls attenuate the signal. Accordingly, the signal quality in the room is generally worse than outside. Changes in the signal characteristics related to the surrounding environment change slowly compared to fast fading. Accordingly, this is referred to as "slow fading".

Typically, only the characteristics of fast fading are considered in the interleaver design. However, as the cost of memory becomes lower, the current very long interleaver also becomes more interesting. Thus, there is a need in interleaver design to take into account the characteristics of slow fading to an ever greater extent.

The following may be presented as an example of slow fading:

-mobile reception of satellite signals. For a moving car, the reception scene is constantly changing in correspondence with the surrounding environment. For each reception scenario, 3 reception states may be defined.

There is a line-of-sight connection (e.g., an open road) to the satellite. This is referred to as a "line of sight" (LOS).

The signal is attenuated (e.g., by a tree). This state is commonly referred to as the "shadow state".

The signal is so severely attenuated that it is no longer useful. This is commonly referred to as a "blocking state".

-transmission over a cellular network using a relatively low transmission power transmitter.

In cellular networks, area coverage is achieved with many transmitters. For such networks, the fact that the reception conditions change relatively needs to be taken into account. Because the transmitter distance is short, the relative distance of the receiver can change rapidly. In this way, the signal characteristics in a long interleaver can vary strongly over the length of the interleaver.

In the receiver, the code symbol exchange (interleaving) performed in the transmitter is reversed again (i.e., deinterleaved). This leads to the following fact: burst errors occurring in transmission are distributed as individual errors to the entire data block after the deinterleaver so that they can be corrected more easily with the FEC decoder.

The following interleaver types will be distinguished:

-a convolutional interleaver

-block interleaver

The convolutional interleaver handles "inter-block interleaving," i.e., blocks are "blurred" in time such that consecutive blocks before the interleaver are interleaved (intrtwise) after the interleaver. Here, a block is composed of one or more codewords. The interleaver length does not depend on the block size but on the width of the ambiguity.

For example, in an exemplary convolutional interleaver, a block of FEC code symbols is divided into 4 partial blocks of different sizes and interleaved with upstream and/or downstream blocks using an interleaver.

The convolutional interleaver is characterized in that:

-dividing the output of the FEC encoder into a plurality of partial data streams via a de-interleaver (de-plexer). The principle is shown in fig. 7. Here, the data stream is typically distributed to the partial data streams in a bit-by-bit manner or in groups of bits ("symbols"). Each partial data stream is then delayed via a delay line (e.g., implemented via a FIFO).

For synchronization of the convolutional deinterleaver in the receiver, only the demultiplexer needs to be synchronized.

The length of the delay line can be regularly stepped (step). However, any arrangement may be chosen such that consecutive symbols are spread as far apart as possible, so that the channel characteristics are uncorrelated.

A block interleaver processes "intra-block interleaving," i.e., in a block-by-block manner, where a block is composed of one or more codewords. Here, the block size defines the interleaver length. Here, systematic FEC codes are frequently employed; the data block contains useful information (information to be transmitted) and additional redundancy in order to be able to correct transmission errors.

Various types of block interleavers are known.

The basic principle of a block interleaver is to rearrange (i.e. exchange) the elements of a data vector or matrix.

It is known to employ a variant for the blocks of the matrix. Here, for example, a row forms a codeword (e.g., a Reed-Solomon codeword). The information is then copied into the matrix row by row and read out column by column in the transmitter/receiver. As an example, the method according to etsisstandard EN301192 shown in fig. 8 will be mentioned here.

Fig. 9 shows the setting of useful data ("application data"). Then read and/or transmitted in datagrams, fig. 9 also shows a matrix arrangement by rows, where the matrix has a number of rows equal to "no _ of _ rows". Further, as an example, there are a plurality of columns from 0 up to 190. To fill the matrix, so-called padding bytes (cont.) are added after the last datagram, continuing up to the last padding byte.

The interleaver characteristics can be described, among other things, by the following parameters:

-end-to-end delay:

the parameter defines the time interval between the instant a symbol is available at the input of the interleaver up to the instant the symbol is available at the output of the deinterleaver.

- (receiver) access time

The time interval between the moment when the first symbol is available at the input of the deinterleaver and the moment when the codeword is available and decodable at the input of the FEC decoder (meaning at the output of the deinterleaver). According to the invention, it is only necessary to wait until a sufficiently large part of the codeword is available at the output of the deinterleaver, instead of waiting the full time of the end-to-end delay, as long as the received packet has a sufficient signal-to-noise ratio. For example, in a broadcast receiver, the parameter determines the time between turning on the receiver or switching to another program and the availability of a signal (e.g., an audio or video signal) to the user. For example, decoding of a video signal may mean an additional delay in some circumstances, which however should not add to the access time. Thus, it should be noted that the audio or video decoder may generate additional delays, which also have an effect on services that are not time-interleaved.

-memory requirements

The memory requirements are determined by the interleaver length and the interleaver type and the selected representation of the signal in the transmitter or receiver.

The interleaver concept described above is characterized by good scrambling (scrambling) within a codeword or block and beyond codeword boundaries in terms of time. As shown in fig. 7, the changing of the order of the individual symbols in the code words that successively enter the input side demultiplexer is implemented by means of delay elements in the outer interleaver. However, with regard to the transmission of these data, there is no need to be time scrambled, but frequency scrambling can be achieved therewith. For example, the data stream output by the multiplexer at the right side end of the outer interleaver is serial-to-parallel converted and frequency scrambled in association with a set of, for example, 1024 carriers in an OFDM symbol, such that the output side data stream always has 2 bits associated with the carriers in case QPSK mapping is used, so that the OFDM occupancy (occupancy) accommodates 2048 bits in the order as produced by the outer interleaver. This of course means that the bits and/or FEC symbols are arranged on other carriers as they would be if the outer interleaver was not already present, due to the delay elements in the outer interleaver.

Thus, depending on the subsequent implementation, the convolutional interleaver or the interleaver with delay is used as a time interleaver, or as a frequency interleaver, or as both a time interleaver and a frequency interleaver.

The interleaver structure shown in fig. 7 has the disadvantage of high costs and high memory requirements both at the transmitter side and at the receiver side. This drawback becomes more and more serious the larger the codeword becomes (i.e., more bits are input into and output from the FEC encoder as a block, as shown in fig. 6, for example). The FEC encoder always has a code rate less than 1. For example, as shown in fig. 6, a code rate of 1/3 means that the number of bits of a codeword output from the FEC encoder is 3 times the number of bits in an input block or information word input into the FEC encoder. Currently, the interleaver will perform time and frequency scrambling as good as possible, so that a multiplexer control and/or in general a "processing" on itself is required for each bit and/or byte (FEC dependent coding scheme).

This directly results in a corresponding deinterleaver control also being required at the receiver side. Furthermore, quality information (e.g. the value of the achieved signal-to-noise ratio, the bit error probability value, or the probability of the value of a bit and/or byte) needs to be generated for decoding per bit and/or per symbol, wherein such probabilities are used in particular in so-called soft decoders. Although this is not as important in relatively small codewords, the problem increases the longer the codeword becomes. For reduced transmitter complexity and in particular for reduced receiver complexity, which is particularly important for broadcast applications, this means that small codeword lengths are actually required, since the receivers are mass-produced and need to be inexpensively supplied. On the other hand, longer codeword lengths provide the advantage of slowly time-varying channel characteristics, since codewords can be "distributed" over a longer time period and/or a larger frequency range.

Disclosure of Invention

It is an object of the invention to provide an efficient and thus manageable transmission concept, which however also provides good results of the slowly varying nature of the channel.

This object is achieved with an interleaver apparatus according to claim 1, a transmitter according to claim 21, a method of processing codewords according to claim 22, a receiver according to claim 23, a reception method according to claim 32, or a computer program according to claim 33.

The present invention is based on the following findings: good efficiency can also be maintained with increased code words if the interleaver device providing the task of the convolutional interleaver does not perform interleaving in a FEC symbol-by-FEC symbol manner but works with Interleaving Units (IU) where one interleaving unit comprises at least 2 FEC symbols. In a particular FEC encoder, the FEC symbols are 1 bit. Thus, the interleaving unit includes at least 2 bits. In other FEC encoders, the FEC symbols are 1 byte. Then, the interleaving unit includes at least 2 bytes. The codeword comprising a sequence of interleaving units, each interleaving unit having at least 2 associated symbols, is fed to an interleaving means to obtain an interleaved codeword having a changed sequence of interleaving units. Specifically, interleaving is performed to change the sequence of interleaving units without changing the order of symbols within the interleaving units, such that at least one interleaving unit of a previous or subsequent codeword is disposed between 2 interleaving units of the same codeword, or such that the order of interleaving units in the interleaved codeword is different from the order of the sequence of interleaving units of the codeword before the interleaving means processes it.

The interleaving thus achieved is scalable, since the number of symbols in the interleaving unit can be arbitrarily adjusted. In other words, the codeword length can be arbitrarily increased or decreased in a fixedly present or fixedly designed interleaver that works with interleaving units and no longer with symbols. Thus, no change in the interleaver structure is required. Only the number of symbols in the interleaving unit needs to be changed. With a fixed number of interleaver taps, a larger codeword can be processed with an increased number of symbols in the interleaver, while the number of symbols in the interleaving unit can be reduced when smaller codewords are to be processed. The larger the number of symbols in the interleaving unit, the more efficient the receiver and transmitter side processing becomes. On the other hand, as the number of symbols in an interleaving unit increases, the advantageous effect of convolutional interleaving decreases. However, this effect may be weakened in the following cases: upstream of the convolutional interleaver a block interleaver is connected which does not operate in an interleaving unit by interleaving unit but actually performs block interleaving in an FEC symbol by FEC symbol manner before forming the interleaving units. Thus, in this preferred embodiment of the invention, a block interleaver is combined with a convolutional interleaver, where the block interleaver works symbol-by-symbol across the entire block, and the convolutional interleaver works only symbol-by-interleaving unit, not symbol-by-symbol.

In another embodiment, it is even possible to replace an efficient block interleaver with a specific FEC code that already enables a particularly good distribution of information over the entire codeword, e.g. as an FEC encoder with a Linear Feedback Shift Register (LFSR) having a very long shift register length, e.g. more than 25 memory cells.

The entire receiver can now be processed in interlace units according to the invention. Thus, there is no longer a need to determine the soft information (i.e., side information) associated with the received interleaved units on a symbol-by-symbol basis, but only on an interleaved unit-by-interleaved unit basis. For example, if the interleaving unit has 8 symbols, this means that the receiver consumption (cost) is reduced by a factor of 8.

Furthermore, the memory management can be significantly simplified not only on the transmitter side but also on the receiver side, since the memory can be read in and out substantially faster in bursts (bursts), which are particularly effective when they relate to adjacent memory addresses. Since the order within the interleaving units is not changed, the interleaving units can be read out in a burst-like manner from the receiver memory particularly efficiently to perform the interleaving function. In fact, the respective interleaving units are arranged at different memory addresses, wherein the memory addresses are well arranged far apart within the memory. However, the symbols within the interleaving unit are consecutive and thus also these symbols are continuously filed in the receiver memory, since the transmitter side convolutional interleaver does not touch the order of the interleaving unit symbols.

The management costs for the side information and the memory costs on the receiver side are strongly reduced, since the side information only needs to be generated, managed and used for the interleaving units and not for each individual symbol. Furthermore, in the interleaving unit it may also be determined whether the decoder has enough data to perform a low-error or error-free decoding after a certain time and/or after a certain number of received interleaving units in case of a relatively good transmission quality. The other interleaving units can then easily be ignored in the receiver and marked as so-called "cancellation". This results in a significant reduction in end-to-end delay.

Furthermore, efficient energy management can be performed with this, since the receiver or relevant parts of the receiver can be put in sleep mode starting from the reception of enough interleaving units for correct decoding.

In addition, better receiver access time can be achieved because the receiver is ready and decodes first when it has enough interleaving units, the receiver does not decode the entire codeword to be ready.

An input block, i.e. an information word having more than 5000 symbols, preferably having a length of more than 10000 symbols, is preferably used. For example, in the case of code rate 1/3, the FEC encoder then provides a codeword of more than 15000 symbols. Typically, a codeword size at the output of the FEC encoder of greater than 10000 bits is employed. The preferred interleaving units then have not only at least 2 bits/symbol but also at least 100 symbols, so that the number of interleaving units per codeword is less than 200 and optimally in the range from 10 to 50.

Drawings

Preferred embodiments of the invention will be explained in more detail below with reference to the accompanying drawings, in which:

FIG. 1 is a schematic diagram of an interleaver concept according to the present invention;

fig. 2 shows a preferred embodiment of a transmitter according to the present invention;

fig. 3 shows a preferred embodiment of a receiver according to the present invention;

FIG. 4 is a functional diagram of the receiver architecture of FIG. 3;

FIG. 5 illustrates a preferred embodiment of a processor that processes routines to improve receiver efficiency;

fig. 6 is a schematic diagram of a combination of an FEC encoder and an interleaver;

FIG. 7 shows a convolutional interleaver according to DVB-T EN 300744;

FIG. 8 shows a block interleaver structure according to EN 301192;

fig. 9 shows an arrangement of useful data "application data", which are read out and/or transmitted in a datagram;

fig. 10 shows a preferred embodiment of an interleaver apparatus according to the invention, which employs three groups of connecting lines with different delays;

FIG. 11 shows an equivalent interleaver overview;

fig. 12 shows an overview of an identical/late interleaver that is suitable for transmission channels with good reception conditions and allowing short access times (fast access).

Detailed Description

Before explaining the figures in detail, specific advantages of the preferred interleaver apparatus will first be shown, as will be described with respect to fig. 1. In particular, in the case of long convolutional interleavers, the invention allows for efficient implementations, which result in specific advantages not only in the invention itself, but also in combination with specific decoder strategies.

It is an object of the invention to consider an interleaver structure that is efficiently implemented, in particular in very long time interleavers. The advantage of this structure lies in the integration with the decoder strategy.

The decoder strategy can be subdivided into the following groups.

-no channel state information

There is a need to identify and correct errors without additional information.

-soft decoding

The probability of transmission error can be estimated for each bit or symbol.

-erasure decoding (erasure decoding)

It is known that no symbols have been received. This form can be considered as a special case of soft decoding. For bits or bytes that have not yet been received (or bits or bytes with a very low signal-to-noise ratio), this is done in a "guess" manner, i.e. the probability that a bit is "0" or "1" is set to 50% each.

In particular, the selected structure provides advantages for soft and erasure decoding. The chosen structure has the following advantages:

-forming channel state information necessary for cancellation and soft decoding for each block (interleaver unit ═ IU), and storing the channel state information together with IU.

The channel state information can also be used to reduce memory requirements. Thus, for example, only data with sufficient signal quality can be stored.

Since several (typically 100 or more) bits of IU are managed as one block in the receiver, e.g. modern memory chips can be used, which typically support more efficient access of data blocks than selective access to individual memory units.

This structure also allows better management of the memory in case of program changes or when the receiver is switched on. In order to avoid mixing data from old (previously selected) and new programs, the memory needs to be deleted (or wait for it until the memory is filled with new data) in case of a program change. With the proposed structure, it is sufficient if only the channel state information is set to "cancel".

The present invention describes an interleaver structure and the accompanying decoder strategy that is particularly relevant for systems employing long-term interleavers.

In connection with low rate error correction codes, the interleaver also allows for secure transmission in case of strong time-varying channels (e.g. typically in satellite transmission or also in cellular terrestrial networks). With appropriate parameters and decoder strategies, many of the typical disadvantages of interleavers, such as longer access times and larger memory requirements, are also reduced.

On the other hand, this is achieved with the data being further processed as small data packets (IU). This (as already mentioned above) allows for a more efficient management of the data. However, to achieve full interleaver gain, it is advantageous to interleave the data in a bit-by-bit manner. This is achieved via so-called mixers.

The advantage of bit-by-bit interleaving by concatenating two interleavers is combined with a more efficient implementation of data-packet-oriented processing.

Fig. 1 shows an interleaver apparatus according to the present invention for processing several codewords CW1, CW2, CW3, wherein the codewords CW1, CW2, CW3 are consecutively arranged and form an output data stream from a FEC encoder, e.g. as shown in fig. 6. Alternatively, the codeword may also be a codeword that has been output from a block interleaver or "mixer", as will be explained with reference to fig. 2. Each codeword is divided into a plurality of interleaving units IU each having 2 indices (i.e. index i and index j, for annotation purposes only). The index i indicates the sequence number of the code word in the sequence of code words and the index j indicates the sequence number of the interleaving unit in the code word i itself. Importantly, according to the FEC encoder, each interleaving unit comprises several symbols (i.e. several bits or bytes), wherein preferably the number of bits or bytes (i.e. in general the number of symbols) in the interleaving unit is larger than 50 and smaller than 400.

Furthermore, the number of symbols in an interleaving unit depends on the codeword length, so it is preferred that each codeword preferably has at least 50 or even more interleaving units. For clarity only, only codewords having 4 interleaving units are shown in the embodiment shown in fig. 1.

Using redundancy addition coding to obtain a codeword from an input block of symbols in an FEC encoder, where the codeword includes more symbols than the input block, is synonymous with the statement that the code rate of the redundancy addition encoder is less than 1. The codeword comprises a sequence of interleaved units, wherein each interleaved unit comprises at least two symbols.

The interleaver apparatus includes: an interleaving apparatus 10, which is a core interleaving apparatus 10 of the interleaving apparatus, is configured to change a sequence of interleaving units in a codeword to obtain an interleaved codeword, where the interleaved codeword includes the changed sequence of interleaving units. Specifically, the interleaving unit 10 changes the interleaving unit sequence without changing the order of symbols in the interleaving units, so that at least one interleaving unit of a preceding or following codeword is disposed between two interleaving units of the codeword, and so that the order of the interleaving units in the interleaved codeword is different from the order of the interleaving unit sequence. Preferably, the interleaving device is configured to have: an input demultiplexer 11, a plurality of connection lines 12 and an output multiplexer 13. After feeding a number of complete interleaving units to one connection line, the input multiplexer is used to switch to another connection line, wherein the number of complete interleaving units is equal to or greater than 1.

Further, in the embodiment shown in fig. 1, the first connecting line 12a has a delay value of substantially 0. Therefore, no delay element is arranged for the first connection line 12a itself in the form of a FIFO memory or a specific delay line. On the other hand, the second delay line 12b has a defined delay D, wherein the next connection line 12c has a further defined delay which is formed by two delay means D and which is different from the delay in the block 12 b. By way of example only, the delay in the connection line 12c is 2 times greater than in the delay line 12 b. As will be explained in detail in connection with fig. 10, any delay ratio may be adjusted, however an integer grid (raster) is preferred among at least a certain number of the plurality of connection lines, wherein the embodiment shown in fig. 10 comprises a plurality of connection lines, in which at least 2 groups (the embodiment shown in fig. 10 even comprises 3) of connection lines are comprised, which groups are characterized by a certain common delay value.

Fig. 2 shows a preferred embodiment for a transmitter, wherein the concept of embedding the interleaver apparatus of fig. 1 in a transmitter also derives from fig. 2. The transmitter apparatus shown in fig. 2 includes: an interleaver apparatus, indicated at 20 in fig. 2, in accordance with the present invention, and an upstream FEC encoder 22, and a downstream multiplexer 24 and a modulator 26 downstream of the multiplexer. In the preferred embodiment shown in fig. 2, the interleaver apparatus 20 further comprises the interleaving unit 10 shown in fig. 1. This interleaving unit 10 is called a "diffuser (disperser)" in fig. 2, however, has in principle the same functionality as the interleaving unit 10 in fig. 1. In the interleaver device 20 according to the invention, upstream of the diffusor 10 there is a mixer 18, said mixer 18 being further comprised in the preferred embodiment to perform a block interleaving function in which the symbol-by-symbol interleaving is performed, before the processing in the diffusor on an interleaving-unit-by-interleaving-unit basis, as is the changing of the order of the symbols in the code words output from the FEC encoder 22.

A further complementary receiver structure is shown in figure 3. The input signal is supplied to a demodulator 30, the demodulator 30 being supplied to a demultiplexer 32, the demultiplexer 32 being able to extract additional information as well as different data streams from the input signal. By way of example only, the processing of a data stream, which has been generated in the example shown in fig. 2, is denoted with the number i. For example, the processing on the transmitter and receiver side for the other data streams k, j (which are other broadcast or television programs or other sessions) can be done on the transmitter and receiver side, just as for data stream i. The data stream i extracted by the multiplexer 32 is supplied to a despreader 34, which demultiplexer 34 supplies Interleaving Units (IU) to a de-mixer 36, which de-mixer 36 then recovers the individual code words, which are then supplied to an FEC decoder 38 in order to create again a replica of the symbol input block (reproduction) identical (except for errors) to the symbol input block fed to the FEC encoder 22 of fig. 2 on the transmitter side, with sufficient transmission and/or with sufficient added redundancy.

The FEC encoder 22 is used to add redundancy to the input signal. Thus, for example, powerful codes are suitable, such as turbo codes known from the 3GPP2 standard, or LDPC codes, for example according to the DVB-S2 standard. However, other codes may also be used. The output of the FEC encoder 22 is a codeword. The use of relatively long codewords (typically greater than 10000 bits) is advantageous for transmission quality.

The mixer 20 is a block interleaver that exchanges the order of bits within a codeword in a character-by-character (i.e., bit-by-bit or byte-by-byte) manner. Therefore, multiplexing occurs in the interleaving unit. The output of the mixer is subdivided into Interleaving Units (IU). An interleaver unit is a group of bits or bytes, or generally a group of characters. Typically, the codewords should be subdivided into about 20 or more interleaving units. At codeword sizes greater than 10000 bits, 200 or more bits per interleaved unit result.

The diffuser 10 represents a convolutional interleaver for distributing the interleaver units in time. In contrast to a general convolutional interleaver, switching is performed not in a bit-by-bit or byte-by-byte manner but in an interleaved unit-by-interleaved unit manner.

As shown in fig. 2, the output of the diffuser 10 may then be multiplexed with other data (i.e., additional information, other programs, or groups of programs).

Modulator 26 then generates an RF signal therefrom. Different modulators may be used. Here, only OFDM or carrier modulation with n-PSK modulation is mentioned as an example.

The receiver shown in fig. 3 comprises a demodulator 30, said demodulator 30 comprising accompanying synchronizing means. Further, frame synchronization may be performed when the demodulator does not use any frame structure nor employ another frame length. The frame synchronization is used for synchronization of the demultiplexer and the deinterleaver.

As will be explained below with reference to fig. 4, the demultiplexer 32 provides a series of interleaving units at its output for the data stream, and also performs channel state estimation. Here, the channel state is estimated not in a symbol-by-symbol manner but in an interleaving unit-by-interleaving unit manner, or generally one piece of reception quality information is provided for each interleaving unit, which provides in some way a statement about the reliability or reception quality of the interleaving unit as a whole. Channel state, signal-to-noise ratio, bit error rate, and the like are such reception quality information. Reception quality information is not determined or used per symbol.

For example, the data stream is provided to a despreader, wherein the diffusor will still be explained and the section diffusor is implemented by memory management. At the output of the despreader, multiplexing is performed to produce again codewords according to an interleaving unit at the output of the despreader, which are then subjected to block deinterleaving in a de-mixer 36, in order then to finally perform decoding (e.g. Viterbi decoding or any other kind of decoding) in an FEC decoder 38. In general, the despreader 34 performs an operation complementary to the function of the diffuser 10, and the demixer 36 performs an operation complementary to the operation of the mixer 18. However, as will be explained later, the receiver-side elements 34 and 36 do not always need to process the entire codeword, but a specific interleaving unit may also be replaced with cancellation (erasure), so that the deinterleaver operation of the elements 34 and 36 is then performed using the cancellation information without using the actually received interleaving unit.

The mixer 18 will be explained in more detail later.

The mixer is a block interleaver that rearranges the bits within a shorter block (e.g., codeword).

In the interleaver scheme employing the scatterer, the de-mixer is used to distribute burst errors that inevitably occur after the despreader due to IU-wise de-interleaving over the blocks as advantageously as possible, so that the decoding process provides better results.

In one embodiment, interleaving from input bits a [ i ] to output bits b [ i ] is performed corresponding to the following equation:

b[i]＝a[(CILM_Inc*i)mod codewordLen]，

wherein:

codeworklen is the codeword length,

CILM _ Inc is a configurable parameter, an

mod is a modulo operation.

Subsequently, as is generally also shown in fig. 1, the diffuser 10 of fig. 2 will be explained.

The actual time interleaver (which may also be used as a frequency interleaver) is a scatterer. The diffuser distributes the blocks (e.g., codewords) output by the mixer over time (and/or over frequency). The diffuser is a convolutional interleaver that operates not in a bit-by-bit manner but in a block-by-block manner. The use of mixers is meaningful due to the block-wise functionality (see above).

Among other things, the advantages of block-wise interleaving will be appreciated in the receiver:

deinterleaving is usually performed by storing the incoming data in an intermediate storage and subsequently reading out in the order of deinterleaving. Storing and reading out in a block-by-block manner allows for efficient control of the memory. After all, dynamic Random Access Memory (RAM) can be written to and read from in bursts, which is much faster than when individual bytes are accessed non-contiguously (non-contiguously). Thus, in the case of block-wise interleaving, (a) slower/cheaper memory can be provided than in the case of bit-wise interleaving, or (b) memory can be shared with other users in a better way (arbitration of the shared memory), so that fewer memory packets are necessary. In both cases, cost savings can be realized.

More efficient management of the received data in the deinterleaver: only the channel state information (e.g., an estimate of the signal-to-noise ratio) needs to be stored per IU rather than per symbol/bit; thereby saving storage space. Furthermore, IU-by-IU storage enables interleaver management to delete individual IUs when they are not needed, e.g. when a sufficiently "good" (hardly disturbed) IU is received from a codeword, there is no longer a need to store a "bad" IU, and the IU that has been received can be easily released with intelligent interleaver management. Smart interleaver management here means that the interleaver control unit keeps the side information on each stored IU in a table in order to optimize the decoder results and the necessary memory. The interleaver control unit can always determine which IUs are needed and which IUs are not needed in the further decoding process. For decoding, the un-stored IU needs to be replaced with cancellation. The de-mixer thus gets multiple cancellations for these IUs from the despreader.

Fig. 10 shows the principle structure of a convolutional interleaver in a despreader for one embodiment. The interleaver is shown with an irregular delay line.

The diffuser comprises a noIlvTaps parallel delay line, where noIlvTaps corresponds to the quotient of the block size at the mixer output divided by one IU size (IU _ Len below). The lines are fed one by one using a Demultiplexer (DEMUX). The input to the demultiplexer is a stream of code bits or symbols from the mixer output. The DEMUX feeds each delay line with exactly one Interleaver Unit (IU) corresponding to the IU Len code bits or symbols from the mixer output. The DEMUX then switches to the next line, and so on. At the beginning of a block (e.g. codeword) processed by the mixer, the DEMUX always switches to the next line (index 0). The end of the block is reached when the DEMUX feeds the IU to the last line (subscript noIlvTaps-1).

The interleaver shown can be configured by 7 parameters noIlv-Taps, middleStart, lateStart, tapdiffMult, earlyTapDeff, middleTapDeff, lateTapDeff.

Each line includes a delay element. As can be seen in fig. 10, there are 3 possible elements:

-delay "E" comprises tapDiffMult earlyTapDiff IU (i.e. tapDiffMult earlyTapDiff IU Len bits/symbol)

-delay "M" comprises tapdiffMult midleTapDeff IUs

-delay "L" comprises tapdiffMult lateTapDeff IUs

At the output of the line, a Multiplexer (MUX) collects the output of the delay elements. Preferably, the multiplexer switches the lines in synchronization with the DEMUX.

The output of the MUX is thus a stream of IU's of interleaved codewords or blocks.

The IU in the first line (subscript 0) is always undelayed. The other IUs of the block/codeword with index 0 < i < noIlvTaps are delayed with respect to the first IU in the following way (see also FIG. 10):

for 0 < ═ i < middleStart: the delay in the block/codeword is i tapDiffMult earlyTapDiff

For middleStart < ≦ i < lateStart: the delay in the block/codeword is (middleStart-1) # tapdiff _ earlyTapDiff + (i-middleStart +1) # tapdiff _ middleTapDiff

For lateStart < ≦ i < noIlvTaps: the delay in the block/codeword is (middleStart-1) # tapdiff _ earlyTapDiff + (lateStart-middleStart) # tapdiff _ middletab + (i-lateStart +1) # tapdiff _ lateTapDiff

To do this, the first middleStart IU ("early part") of the block/codeword is distributed differently in time from the middle (lateStart-middleStart) IU ("middle part"), the last (noIlvTaps-lateStart) IU is distributed again differently:

-the distance between IUs of early parts belonging to the same block/codeword before interleaving is then tapdiffMult early tapdiff,

-the distance between the IU of the middle part is tapDiffMult midletapdiff blocks/codewords

The distance between the IU of the late part is tapDiffMult lateTapDiff blocks/codewords.

By configuring the 7 interleaver parameters, a suitable interleaver profile can be selected, i.e. an advantageous distribution of the content of the blocks/codewords over time (and/or frequency). For example, the IU may be delivered with a short delay in the late part (if this is required), or may be distributed evenly (unifomly) over a given period of time, or both may be combined, etc.

Fig. 10 shows a preferred embodiment of the aforementioned interleaver apparatus, also referred to as a diffuser. In particular, the interleaver device or the interleaving arrangement of the interleaver device shown in fig. 10 comprises an input multiplexer 11, said input multiplexer 11 serving as a demultiplexer in fig. 10 and being referred to as DEMUX. Furthermore, there is an output multiplexer 12, which is referred to as MUX in fig. 10. As already described, in the embodiment shown in fig. 10, between the two multiplexers 11 and 12, there are a plurality of connection lines subdivided into 3 groups. The first group is the early part 12 d. The second part is the middle part 12e and the third group is the late part 12 f.

Each delay line and/or connection line with delay has a specific delay unit, except for just the first connection line 12a, wherein, however, the delay units may be configured differently in 3 groups, i.e. via the parameter earlyTapDiff for group 12d, via the parameter midletapdiff for group 124 and via the parameter lateTapDiff for group 12 f.

Fig. 10 also shows that the delay is increased by an increment (E, M or L) from one connection line (Tap) to another connection line, so that, for example, connection line Tap middleStart-1 has multiple TapmiddleStart-1 delay elements E. Furthermore, each connection line of the second group 12E has the same number of delay cells E as the last connection line of the first group, and additionally each connection line of the second group 12E has a plurality of M delays that increase from one connection line to another. Correspondingly, each connection line of the late group also has the same number of E-delays as the last connection line of the first group, and the same number of M-delays as the last connection line of the second group, and a plurality of L-delay elements added from one connection line to another.

The first and second sets and the third set each comprise connection lines, wherein each of these connection lines has a defined amount of delay or an integer multiple of the defined amount of delay, except for just the first connection line of the first set, wherein the defined amount of delay (i.e., the increment E, M, L) may be different from one set to another, and importantly, as explained previously, is configurable by individual control parameters. As can be seen from fig. 10 and the description of E, M and L, the basic grid is the length of an interleaving unit, i.e., IU Len. Each delay E, M, L is an integer multiple of this delay corresponding to the length IU Len of an interleaving unit, if the interleaving unit thus has, for example, 20 symbols. The delay corresponding to the whole interleaving unit is given by the product of the period duration (period) of the processing clock and the number of bits or symbols, wherein the clock is the bit clock in case of processing bits, and wherein the clock is the byte clock in case of processing bytes into symbols.

Specific configuration examples will be shown later.

FEC parameter

A turbo code corresponding to the 3GPP2 standard is used as the FEC encoder.

Bits per block (including 6 tail bits) at the input of the FEC encoder	12288 bits	Bits
			Code rate R	1/4
Number of bits at the output of an FEC encoder	49152 bits	Bits
			IU size	512 bits	Bits
IU number per codeword	96

Mixer arrangement

codeWordLen is 49152 bits and CILM _ Inc is 217.

Diffuser arrangement

The following subsections (sub-chapters) illustrate various configurations representing different interleaver profiles and thus various application scenarios.

Equivalent extension (fig. 11)

The IUs belonging to a block (or code word) are distributed equally over time, i.e. the distance between the IUs is the same at the output of the diffusor.

Such a configuration is meaningful if the transmission channel generates a random short interruption (bad channel state) and then more or less randomly disturbs the individual IUs. In particular, this configuration is meaningful in the case of a high code rate.

One possible configuration would use only the early part of the usage, middleStart ═ noIlvTaps.

Early/late stage

The IU of one block is transmitted in 2 bursts (early or late), with a time interval between these 2 bursts in which the IU of the block is not transmitted or is transmitted very rarely.

This configuration should be used if the transmission channel generates very long interruptions (e.g. when driven under a bridge or through a tunnel). Here, in case of good reception, the early or late part must be sufficient by itself to decode the block. If this is the case, the interruption is allowed to be maximized (as long as the interval between early and late phases) without failure in decoding the block.

For parameterization of the configuration (parameterization), midletestart and noIlvTaps-lateStart (number in early and/or late parts) should be larger than lateStart-midletestart (size of middle part). For burst-like (burst-like) transmission, earlyTapDiff and lateTapDiff should be chosen at 0, tapDiffMult and middleTapDiff should be maximized in order to extend IU as far as possible in the middle part.

Equal/late (FIG. 12)

The partial IU is delivered according to a policy of "equal extension" (see above), the rest coming in burst-like form as late part.

Thus, in case of good reception conditions, the late part has to comprise a sufficient number of IU such that the late part alone is sufficiently error-free to decode. The interleaver profile is therefore suitable for fast access, so that the access time can be kept low, independently of the long interleaver. It is desirable that the remaining IU in the equivalence section provide protection against random failure of the IU (see "equivalence extension").

Parameterization may be performed in a similar manner as above for the early, intermediate and late parts.

Early stage/identity

This configuration is a time mirror of the "equal/late" configuration, i.e. there is a class burst early part for the remaining IU, which is followed by an "equal extension".

Here, advantageously, the end-to-end delay is small. In the earliest stages, the early part may have been decoded after it was received, which was entered into the transmitter immediately after the accompanying information.

Fig. 5 shows a functional implementation of a receiver device according to the invention. The receiver device receives the received signal with interleaved interleaving units as output from multiplexer 32 (e.g., from the data stream with number i in fig. 3) and as input into despreader 34. These interleaved interleave units are input to an interleave unit detector 40, which interleave unit detector 40 is used to receive the interleave units from the signal. It is detected that the interleaving unit needs to be controlled correctly by the despreader 34. Furthermore, a side information estimator 42 is arranged according to the invention, said side information estimator 42 communicating only with the interleaving unit detector 40 or additionally deriving the received signal, or may be controlled by another device, such as a channel estimator. The side information estimator is for estimating information for the extracted interleaved unit related to transmission of the entire interleaved unit. The side information estimator 42 and the interleaved unit detector 40 use the side information determined for the entire interleaved unit and provided from block 42 to the processor 44 for further processing of the interleaved unit. Here, in the preferred embodiment, the processor 44 combines the functions of the despreader 44 and the demixer 36 of fig. 3. However, as will be described with reference to fig. 5, in a preferred embodiment of the invention, the processor 44 does include other functionality to improve the efficiency of the receiver.

Specifically, processor 44 then checks if a reception quality better than a threshold is assigned to an interleaving unit when it has side information for the interleaving unit (step 50). If the question is answered in the negative, the entire interleaved unit is discarded (step 52), which may be achieved in particular, for example, by: nothing is stored in memory, but the discarded interleaved units are simply characterized with cancellation (i.e. with probability information signaling 50% probability for 0 or 1, for example, when doing de-spreading).

If the question in step 50 is answered in the affirmative, such an interleaving unit is stored in the receiver memory as set forth in step 54, which implements the despreader function 34 by being read from the memory in a different manner than the interleaving unit was written. Furthermore, if it is determined that sufficient good quality interleaving units have been received such that correct decoding of the codeword can be performed without receiving all interleaving units of the codeword, it is checked whether an interleaving unit stores in the receiver memory an interleaving unit of a quality inferior to the interleaving unit currently under consideration. If such an interleaved unit is found, it is overwritten with the currently detected, updated, better quality interleaved unit. However, in case it is determined that all stored interleaved units have a good quality, and in case it is also determined that sufficient interleaved units have been received, the relatively good quality interleaved units due to the estimated side information are still discarded, since they are no longer needed.

In this respect, in step 56 it is checked whether sufficient interleaving units have been stored, which means that correct decoding of the code word has taken place. If the question is answered in the affirmative, decoding begins with step 58, i.e. the codeword is provided to the de-mixer 36 in the presence of the mixer 36, or fed directly to the FEC decoder in the absence of the de-mixer 36 of fig. 3, with cancellation inserted for interleaved units that have been discarded or are no longer stored. If it is simultaneously determined in step 60 that the memory is still available, then parallel storage of interleaved units of another program in the receiver memory (for improving the duration that occurs in the case of program switching) can be started in the memory (step 62) so that the second program is also stored in the memory in full relation to the code words in the best case, so that switching from one program to another is achieved directly, i.e. without the end-to-end delay actually given by the long convolution interleaver.

All this becomes possible because according to the invention it no longer works in a symbol-wise or bit-wise manner, but in an interleaved unit-wise manner, so that only the quality information needs to be processed in an interleaved unit-wise manner. Furthermore, the receive memory can be read out in an interleaved unit-by-interleaved unit manner (i.e., in a burst-like manner), thereby not only significantly speeding up the despreader operation when using a general RAM memory, but also so that read-out enhancement occurs when using any other memory, because adjacent memory addresses can be read out in bursts to get individual symbols present in the interleaved units in order to perform the despreader operation. Furthermore, clear signaling can be maintained, since the number of time information to be managed no longer needs to be generated, managed and applied in a bit-by-bit manner but only in an interleaved unit-by-interleaved unit manner, which reduces the information to be managed by a factor of 128, for example, in the case where the interleaved unit includes 128 bits or more. Thus, the accuracy is indeed reduced, since there is no longer quality information per bit, but only quality information per interleaving unit (i.e. coarser granularity of quality information). This is not critical, however, because such precise quality information is not required and/or is not always represented at this fine granularity. According to the invention, the acquisition of the quality information is thus adapted to the interleaver, so that the complexity of the channel estimator can also be reduced equally in terms of reduced complexity without suffering from a quality reduction.

The decoder strategy according to the indications of fig. 4 and 5 will be explained in detail later. This side information in the despreader can be used to control other decoding steps, since the channel state is determined early for each IU. An implementation of memory optimization may be performed in the following manner.

The use of low-rate codes in time-varying transmission channels enables that only "good" (less disturbing) IUs need to be stored. There is no need to store the IU with low signal quality. As an example, the use of rate 1/4 codes will be mentioned, wherein the code words of said rate 1/4 codes consist of 96 IU's. In case of good reception, about 30% of the IU (i.e. 25% plus 5% redundancy of the code needed to represent the information in the rate 1/4 code) is enough to decode the code so that the decoder can work correctly. If a policy of "storing only the best IU" is made, the necessary memory can be reduced by up to 30%. Accordingly, only 30% 96 ═ 29 IU are stored for each codeword instead of 96 IU for which 29 IU the best channel state is estimated. If 29 IU's have been stored and another IU is received that is better than the worst IU received previously, the bad IU is simply replaced with the better IU. This is achieved by means of a suitable interleaver control unit in the diffusor.

Similar strategies are particularly useful in connection with diversity combining or where the multiplexer includes various programs.

Concept 1:

-storing as many IU's as needed for decoding with the selected program (see example above).

The rest for other programs, making fast program changes possible (see fast access). Thereby making optimal use of existing memory.

Concept 2:

in case of diversity combining, good IU's are stored only early. Thereby making the necessary memory smaller.

The strategy adopted alternatively or additionally for energy consumption optimization may be as follows:

the receiver can be switched off if a sufficiently "good" IU is received. The receiver thus continuously measures the quality of the received IU. If enough IU's with good signal quality have been received, the remaining IU's are no longer needed and can be replaced by "cancel". For example, if the transmission system is constructed so as to allow a certain range (maximum distance between the transmitter and the receiver), all receivers close to the transmitter receive data of higher quality. Thus, the receiver no longer needs all the IUs for error-free decoding. The accompanying parts of the receiver can be switched off repeatedly if a separate IU is no longer needed. Thus, since power consumption is reduced, the operating time of the portable device is extended. The management of the data is substantially simplified by the selected interleaver structure.

The strategy of optimization by fast access is best provided in case the interleaver is configured for strong late parts (i.e. in case the third set of the diffusors of fig. 10 is strongly weighted).

In the case of a convolutional interleaver, the sum of the delay line lengths in the transmitter and receiver is equal for all the tags (tab). If the delay line length is chosen in the transmitter, the delay line is correspondingly short in the receiver. A long delay line in the receiver means that the accompanying data is transmitted later ("late"). Whereas a short delay line in the receiver implies a short delay. So that the appended bits are available at the output of the despreader after a short delay time ("faster access"). This configuration is particularly advantageous when a relatively low code rate is used for the FEC encoder.

In summary, the invention thus comprises an interleaver apparatus implementing the functionality of a convolutional interleaver in an interleaving arrangement, which interleaver apparatus operates in an interleaving unit-by-interleaving unit fashion, wherein an interleaving unit comprises more than one symbol. Where the number of bits per symbol corresponds to the symbol length of the FEC encoder.

The interleaver structure of the present invention thus has the characteristics of: the codeword is decomposed into a series of smaller data packets, i.e., interleaved units. The interleaving unit comprises more than one information symbol, preferably at least 128 information symbols. These interleaved units are distributed via a demultiplexer to a plurality of connection lines with different delays, wherein the connection lines and/or the delay lines have various lengths or the various delays are implemented in some way (e.g. with a FIFO memory). After a corresponding delay, the output-side multiplexer multiplexes the outputs of the connecting lines again into a data stream, which is then fed to the modulator in order to finally generate the RF output signal.

In a preferred embodiment, the mixer is connected upstream of the diffusor. In this way, the disadvantages due to grouping in interleaved units are compensated for first. Furthermore, particularly for FEC codes which still have relatively good properties without mixers, the following implementation is also preferred: this implementation can be done for complexity reasons at both the transmitter side and the receiver side without mixers.

If a mixer is used, the mixer is used as a block interleaver which is connected upstream of the interleaving means and which arranges the data bits or data symbols of the code words separately (i.e. in a symbol-wise or bit-wise manner).

To improve the decoder function, the channel state is first determined at the decoder side for each interleaving unit. Thus, the series of interleaving units together with the channel state information is then turned into the original order via a despreader. The output of the deinterleaver is then further processed with the channel state information using an FEC decoder. As explained according to fig. 10, a diffusor is a configurable diffusor with several sections, wherein its length in an interleaving unit and its time spread in relation to the delay in the respective section can be chosen differently as desired. The configuration of the diffuser in three stages (i.e., the early stage, the middle stage, and the late stage) is a specific implementation. For certain applications, an early-late configuration or an equivalent-late configuration may be advantageous, where a low-rate FEC code and a strong late portion are preferred in the latter configuration to allow fast access. An alternative configuration in the case of transmit diversity is an early/equivalent configuration or a supplemental scatterer configuration. On the decoder side, a decoder algorithm is preferred which archives the good and needed for decoding in memory, while replacing the bad interleave units with better interleave units or without storing bad interleave units. The interleaving units are not stored if the channel is better than planned. The unusable interleaved units are referred to herein as "cancellations".

In particular, functionality may be used to improve energy management, which is advantageous for mobile devices that are battery operated and with which the active time of the mobile device may be increased. In particular, upon receiving a good enough interleave unit, the corresponding receiver section is switched off to save battery current.

Depending on the circumstances, the method of the present invention may be implemented in hardware or software. May be embodied on a digital storage medium, in particular a disk or CD having electronically readable control signals capable of cooperating with a programmable computer system such that the method is performed. Generally, the present invention thus also includes a computer program product for execution on a computer. In other words, the invention can thus also be implemented as a computer program having a program code for performing the method when the computer program is executed on a computer.

Claims (30)

1. An interleaver apparatus (20) for processing codewords comprising a sequence of forward error correction symbols derived from an input block of symbols using redundancy addition coding, the codewords comprising more symbols than the input block, the interleaver apparatus comprising:

a block interleaver (18) for changing the order of the forward error correction symbols in the codeword such that a changed codeword is obtained in which the order of the forward error correction symbols in the codeword is changed, wherein the changed codeword comprises a sequence of interleaving units; and

interleaving means (10) for changing the sequence of interleaving units in said changed codeword to obtain an interleaved codeword comprising a changed sequence of interleaving units, wherein the interleaving means (10) do not change the order of forward error correction symbols within an interleaving unit but change said sequence of interleaving units such that at least one interleaving unit of a preceding or a following codeword is arranged between 2 interleaving units of a codeword, and wherein each interleaving unit comprises at least two forward error correction symbols,

wherein the interleaving means (10) are arranged for changing the sequence in such a way that the order of the interleaving units in the interleaved codeword differs from the order in said sequence of interleaving units, without changing the order of the symbols within the interleaving units.

2. The interleaver apparatus as claimed in claim 1, wherein the size of the interleaving units is selected such that the code word comprises at least 4 interleaving units, and the interleaving means (10) are arranged for changing the order of the at least 4 interleaving units.

3. The interleaver apparatus of claim 1, wherein the symbols are bits and each interleaving means comprises at least 2 bits, or the symbols are bytes and each interleaving unit comprises at least 2 bytes.

4. The interleaver apparatus as claimed in claim 1, wherein the redundancy addition coding uses a combination of one or more symbols of the input block, working in a symbol-by-symbol manner to obtain symbols of the codeword, such that the codeword is based on a symbol grid, and the interleaving means (10) are adapted to perform the change of order in an interleaving unit grid, the interleaving unit grid being coarser than the symbol grid.

5. The interleaver apparatus according to claim 1, wherein,

the interleaving unit comprises at least 128 symbols, an

The interleaving means is used to change the order of the interleaving units.

6. The interleaver apparatus as claimed in claim 5, wherein the block interleaver (18) is configured to implement the following interleaver rules:

b[i]＝a[(CILM_Inc*i)mod codewordLen]，

where b [ i ] is the symbol at codeword position i at the output of the block interleaver, a [ x ] is the symbol value at codeword position x input to the block interleaver, CILM _ Inc is the configuration parameter, mod is the modulo operation, and Codewarlen is the length of the codeword.

7. The interleaver device according to claim 6, wherein the block interleaver (18) is configured to operate using configuration parameters CILM _ Inc.

8. The interleaver apparatus as claimed in claim 7, wherein the block interleaver (18) comprises configuration parameters depending on the code rate of the redundancy addition encoder, said parameters typically being prime numbers or products of prime numbers.

9. The interleaver apparatus according to claim 1, wherein in case that the redundancy-addition coding includes a turbo code, a Viterbi code, or an LDPC code, the symbols include bits; and in the case where the redundancy addition coding is Reed-Solomon coding, the symbols include bytes.

10. The interleaver apparatus as claimed in claim 1, wherein the interleaving means comprises:

a plurality of connection lines (10a, 10b, 10c), wherein each connection line is for providing a defined delay, said delay being different for each connection line or equal to 0 for a connection line;

an input multiplexer (11) for switching to one connection line after feeding a number of complete interleave units to another connection line, wherein the number of complete interleave units is equal to or greater than 1; and

an output multiplexer (13) for switching to one connection line after receiving a number of complete interleaving units from another connection line, wherein the number of complete interleaving units is equal to or greater than 1.

11. The interleaver apparatus of claim 10, wherein the plurality of connection lines comprises: a first set of connection lines (12d), in which first set of connection lines (12d) each connection line other than the first connection line is used to provide a defined first delay amount (E) or an integer multiple of the defined first delay amount, and

the plurality of connection lines comprises a second set of connection lines (12E), wherein each connection line in the second set is adapted to provide the same multiple of a defined first delay amount (E) and a defined second delay amount (M) different from the defined first delay amount (E) or an integer multiple of the defined second delay amount (M).

12. The interleaver device according to claim 11, wherein the plurality of connection lines further comprises a third group of connection lines (12f), wherein each connection line in the third group comprises the same multiple of a defined first delay amount and the same multiple of a defined second delay amount, and a defined third delay amount (L) different from the defined first delay amount or the defined second delay amount.

13. The interleaver apparatus of claim 11, wherein the defined first delay amount or the defined second delay amount is configurable using configuration parameters that allow configuration at integer multiples of an interleaving unit.

14. The interleaver apparatus as claimed in claim 12, wherein the third set of connection lines (12f) is for a third delay amount defined in an integer multiple configuration of interleaving units.

15. The interleaver apparatus of claim 1, wherein the interleaving means is configured to interleave such that the interleaved units of the codewords are transmitted uniformly over time, thereby implementing an equal stretch diagram.

16. The interleaver apparatus of claim 1, wherein the interleaving means is configured to interleave such that interleaved units of the codeword are transmitted stronger in a first or third time interval than in a second time interval located between the first and third time intervals, wherein no or fewer interleaved units are transmitted in the second time interval than in the first and third time intervals to achieve the early-late stretch pattern.

17. The interleaver apparatus of claim 1, wherein the interleaving means is configured to interleave such that a portion of the interleaved units are transmitted in a uniformly distributed manner over time, and a remaining portion of the interleaved units are transmitted in a burst-like manner in a subsequent time interval in which more interleaved units are transmitted per time unit than in the first time interval to achieve an equal-late stretch pattern.

18. The interleaver apparatus of claim 1, wherein the interleaving means is for interleaving such that a plurality of interleaved units are transmitted in a burst-like manner in a first time interval and such that a remaining portion of the interleaved units of the codeword are transmitted in a subsequent longer time interval, wherein more interleaved units are transmitted per time unit in the first time interval than in the subsequent time interval to obtain the early-equal spread graph.

19. The interleaver apparatus of claim 1 wherein the interleaving means is configurable and introduces configuration parameters into the transmission signal for detection by the receiver.

20. A transmitter for generating a transmission signal, comprising:

a redundancy addition encoder having a code rate less than 1 for generating a codeword including a plurality of forward error correction symbols more than the number of symbols of an input block according to a signal input block;

interleaving means according to claim 1; and

and a modulator for modulating the data stream output from the interleaving means onto a transmission channel.

21. A method for processing a codeword comprising a sequence of forward error correction symbols derived from an input block of symbols using redundancy addition coding, the codeword comprising more symbols than the input block, the method comprising:

changing (18) the order of the forward error correction symbols in the codeword such that a changed codeword is obtained in which the order of the forward error correction symbols in the codeword is changed, wherein the changed codeword comprises a sequence of interleaving units; and

changing (10) the sequence of interleaved units in the changed codeword to obtain an interleaved codeword comprising the changed sequence of interleaved units, wherein the changing (10) is performed such that the order of the forward error correction symbols within an interleaved unit is not changed but the sequence of interleaved units is changed such that at least one interleaved unit of a preceding or a following codeword is arranged between 2 interleaved units of the codeword and wherein each interleaved unit comprises at least two forward error correction symbols,

wherein in the step of changing (10) the sequence of the interleaved units in the changed codeword, the sequence is changed in such a way that the order of the interleaved units in the interleaved codeword is different from the order in the sequence of interleaved units, without changing the order of the symbols within the interleaved units.

22. A receiver for receiving a signal from an interleaver apparatus (20), the signal being derived from an input block of symbols using redundancy-adding coding and being based on a codeword comprising a sequence of interleaved units, wherein an order of the interleaved units has been changed by the interleaver apparatus (20), wherein an order of forward error correction symbols in the codeword has been changed before forming the interleaved units and the order of the forward error correction symbols within the interleaved units has not been changed after forming the interleaved units, and at least one interleaved unit of a preceding or following codeword is arranged between 2 interleaved units of the codeword, wherein each interleaved unit comprises at least two forward error correction symbols, the receiver comprising:

a detector (40) for detecting an interleaving unit from the signal;

a side information estimator (42) for estimating side information for the entire interleaved unit in relation to transmission of the entire interleaved unit; and

a processor (44) for further processing the interleaved unit in dependence on the side information determined for the entire interleaved unit, wherein the processor is adapted to store the entire interleaved unit for further processing solely in dependence on the side information; or the entire interleaving unit is completely ignored for further processing.

23. The receiver of claim 22, wherein the processor (44) is configured to store the interleaving unit for further processing if the side information indicates a reception quality above a threshold (50).

24. The receiver of claim 22, wherein the processor (44) is configured to store the interleaving units for further processing if the processor (44) determines that sufficient interleaving units for decoding at a particular error rate have not been stored for the codeword.

25. The receiver of claim 24, wherein the processor is configured to: in case that enough interleaving units have been stored for the codeword and in case that side information indicating a reception quality of an interleaving unit better than the already stored reception quality has been estimated for the interleaving means, the already stored interleaving unit with the worse reception quality is overwritten (54) in the memory.

26. The receiver of claim 22, wherein the signal comprises a plurality of programs, and

a processor (44) is configured to: in case enough interleaved units (62) have been stored for the code word of the selected program and in case a free memory is still available (60), interleaved units of another program are stored without storing interleaved units of the code word of the selected program.

27. The receiver of claim 22, wherein the receiver further comprises a receiver,

wherein the processor (44) is configured to place the receiver in a power saving mode if sufficient interleaving units are stored for correct decoding of the code.

28. The receiver of claim 22, wherein the signal is interleaved such that there is a late time duration in which more interleaved units of the codeword are included than in another duration of the transmission, and

the processor (44) includes a fast access function to decode the codeword based on the interleaved units found from the late time interval without waiting for interleaved units from another time interval.

29. The receiver of claim 22, wherein the signal is encoded back at a code rate equal to or less than 0.5, and the late time interval has a proportion of interleaved units such that the number of interleaved units in the late time interval is sufficient to decode at a particular error rate for a particular channel quality.

30. A method of receiving a signal from an interleaver apparatus (20), the signal being derived from an input block of symbols using redundancy-adding coding and being based on a codeword comprising a sequence of interleaved units, wherein an order of the interleaved units has been changed by the interleaver apparatus (20), wherein an order of forward error correction symbols in the codeword has been changed before forming the interleaved units and the order of the forward error correction symbols within the interleaved units is not changed after forming the interleaved units, and at least one interleaved unit of a preceding or following codeword is arranged between 2 interleaved units of the codeword, wherein each interleaved unit comprises at least two forward error correction symbols, the method comprising:

-detecting (40) an interleaving unit from the signal;

estimating (42) side information for the entire interleaving unit related to the transmission of the entire interleaving unit; and

further processing (44) the interleaved unit in dependence on the side information determined for the entire interleaved unit, wherein the processor is adapted to store the entire interleaved unit for further processing in dependence on the side information at all; or the entire interleaving unit is completely ignored for further processing.