HK1243223B - Method for making 3d interconnect component for fully molded packages - Google Patents

Description

Method for preparing 3D interconnect components for full mold packaging

CROSS-REFERENCE TO RELATED APPLICATIONS

This disclosure claims the benefit of U.S. Provisional Patent Application No. 62/154,218, filed April 29, 2015, entitled “3D Interconnect Component for Fully Molded Packages,” including the filing date, the disclosure of which is incorporated herein by reference.

Technical Field

The present disclosure relates to three-dimensional (3D) interconnected components or component assemblies, including spin-weldable component assemblies, for use in fully molded packages. The fully molded packages may include multiple integrated semiconductor devices, including component assemblies, for use in wearable technology, Internet of Things (IoT) devices, or both.

Background Art

Semiconductor devices are common in modern electronic products. Semiconductor devices have varying numbers and densities of electrical components. Discrete semiconductor devices typically contain a single type of electrical component, such as a light-emitting diode (LED), small-signal transistor, resistor, capacitor, inductor, and power metal-oxide-semiconductor field-effect transistor (MOSFET). Integrated semiconductor devices typically contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, microprocessors, charge-coupled devices (CCDs), solar cells, and digital micromirror devices (DMDs).

Semiconductor devices perform a wide variety of functions, such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronic devices, converting sunlight into electricity, and creating visual projections for television displays. Semiconductor devices are found in entertainment, communications, power conversion, networking, computers, and consumer products. They are also found in military applications, aviation, automobiles, industrial controllers, and office equipment.

Semiconductor devices exploit the electrical properties of semiconductor materials. The atomic structure of semiconductor materials allows their conductivity to be manipulated by applying an electric field or base current, or through a doping process. Doping introduces impurities into the semiconductor material to manipulate and control the conductivity of a semiconductor device.

Semiconductor devices contain both active and passive electrical structures. Active structures (including bipolar and field-effect transistors) control the flow of current. By varying the level of doping and the level of applied electric field or base current, transistors facilitate or restrict the flow of current. Passive structures (including resistors, capacitors, and inductors) establish the relationship between voltage and current required to perform a variety of electrical functions. Passive and active structures are electrically connected to form circuits, which enable semiconductor devices to perform high-speed computing and other practical functions.

Semiconductor devices are generally manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing, each of which may involve hundreds of steps. Front-end manufacturing involves forming multiple semiconductor dies on the surface of a semiconductor wafer. Each semiconductor die is generally identical and contains a circuit formed by electrically connecting active and passive components. Back-end manufacturing involves singulating individual semiconductor dies from the finished wafer and packaging the die to provide structural support and environmental isolation. As used herein, the term "semiconductor die" refers to both the singular and plural forms of the word, and thus may refer to both a single semiconductor device and a plurality of semiconductor devices.

One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices generally consume less power, have higher performance, and can be produced more efficiently. Furthermore, smaller semiconductor devices have a smaller footprint, which is desirable for smaller end products. Smaller semiconductor die sizes can be achieved through improvements in front-end processes, resulting in semiconductor dies with smaller, higher-density active and passive components. Back-end processes can also achieve semiconductor device packaging with a smaller footprint through improvements in electrical interconnects and packaging materials.

The back-end processing of the semiconductor die may also include a plurality of surface mount devices (SMDs), passive components, or the integration of the two, which are used to connect the semiconductor die or integrated circuit to the substrate surface and the PCB without using through-holes in the PCB. A quad flat package (QFP) uses an SMD that includes leads extending from each of the four sides of the package, which are sometimes referred to as "gull-wing leads." The QFP leads provide electrical input/output (I/O) interconnections between the semiconductor die in the package and the PCB or substrate on which the QFP is mounted. Other SMD packages are prepared without leads and are often referred to as flat leadless packages. Examples of flat leadless packages are quad flat leadless packages (QFNs) and double-sided flat leadless (DFN) packages. A QFN package conventionally includes a semiconductor die connected to a lead frame for package I/O interconnections by wire bonding.

The integration of passive components in fan-out wafer-level packaging (FO-WLP) is generally performed by placing the passive components directly onto a temporary carrier tape before molding or encapsulating the passive components. In the case of embedded wafer-level ball grid array (eWLB), the active surface of the semiconductor die and the passive components can be attached to a tape and then overmolded or encapsulated to form and reconstruct the wafer or board. After releasing the tape, the terminals or contact pads of the semiconductor die and passive components can be exposed, and a redistribution layer can be applied to the board so that conductive traces can be made to connect to the passive components. Typically, SMD passives soldered to the substrate are attached to the core layer within the substrate to form an application of embedded die in the substrate.

Summary of the Invention

Opportunities exist to improve semiconductor manufacturing. Accordingly, in one aspect, a method of preparing a semiconductor component package may include providing a substrate including conductive traces; soldering a plurality of surface mount devices (SMDs) to the substrate using solder; encapsulating the plurality of SMDs on the substrate using a first molding compound over and around the plurality of SMDs; and singulating the plurality of SMDs by separating the substrate to expose the conductive traces and form a plurality of component assemblies including exposed conductive traces on a first side of the component assemblies and on a second side of such component assemblies, the second side of such component assemblies being opposite the first side of such component assemblies. The method may further include providing a temporary carrier, mounting at least one of the component assemblies to the temporary carrier, wherein the first side of the at least component assembly and the exposed conductive traces are oriented toward the temporary carrier, mounting a semiconductor die including conductive interconnects to the temporary carrier, the semiconductor die being adjacent to at least one of the component assemblies, encapsulating the at least one of the component assemblies and the semiconductor die with a second molding compound while the at least one singulated component assembly and the semiconductor die are mounted to the temporary carrier to form a reconstituted sheet, and exposing the conductive interconnects and the exposed conductive traces at the first side or the second side of the at least component assembly relative to the second molding compound. The method may further include forming a first redistribution layer over the second molding compound to electrically connect the conductive interconnects and the exposed conductive traces, and singulating the reconstituted sheet.

The method of preparing a semiconductor component package may further include a substrate comprising two laminate layers, a printed circuit board (PCB), or a blank molding compound sheet. The component assembly may include a passive device. The semiconductor die may be an embedded semiconductor die comprising a conductive interconnect coupled to the semiconductor die and exposed relative to the second molding compound. The conductive interconnect may include a copper bump, a pillar, a stud, or a thick RDL trace. Solder coupling at least one of the singulated component assemblies to the substrate may be contained within the semiconductor component package and not exposed relative to the semiconductor component package.

In another aspect, a method for preparing a semiconductor component package may include: providing a substrate comprising conductive traces; attaching an SMD to the substrate using solder to form a component assembly; mounting the component assembly to a temporary carrier, wherein a first side of the component assembly is oriented toward the temporary carrier; mounting a semiconductor die comprising conductive interconnects to the temporary carrier adjacent to the component assembly; encapsulating the component assembly and the semiconductor die with a molding compound when the component assembly and the semiconductor die are mounted to the temporary carrier to form a reconstituted sheet; and exposing the conductive interconnects and the conductive traces at the first side or the second side of the component assembly relative to the molding compound.

The method of preparing a semiconductor component package may also include a substrate comprising two laminate layers, a PCB, or a blank mold compound sheet. Before the component assembly is mounted on the temporary carrier, the SMD on the substrate may be encapsulated over and around the SMD using an additional mold compound. The semiconductor die may be an embedded semiconductor die comprising conductive interconnects coupled to the semiconductor die and exposed relative to the mold compound, wherein the conductive interconnects comprise copper bumps, pillars, columns, or thick RDL traces. Solder coupling the component assembly to the substrate may be contained within the component assembly and not exposed relative to the component assembly. The conductive interconnects and conductive traces may be exposed by removing the temporary carrier from the reconstructed sheet and grinding the reconstructed sheet. A first redistribution layer may be formed over the reconstructed sheet to electrically connect the conductive interconnects and the conductive traces, and a second redistribution layer may be formed opposite the first redistribution layer to electrically connect the exposed conductive traces to form an electrical connection through the thickness of the semiconductor component package.

In another aspect, a method of preparing a semiconductor component package may include: providing a substrate comprising conductive traces; attaching a SMD to the substrate using solder; mounting the SMD and the substrate to a temporary carrier; mounting a semiconductor die comprising conductive interconnects adjacent to the SMD; dispensing a molding compound over the temporary carrier; and exposing the conductive interconnects and such conductive traces relative to the molding compound.

The method of preparing a semiconductor component package may further include mounting a semiconductor die including a conductive interconnect adjacent to a temporary carrier. The semiconductor die including the semiconductor interconnect may be mounted adjacent to the SMD. A molding compound may be dispensed to encapsulate the SMD and the semiconductor die, thereby forming a reconstructed sheet. The method may further include singulating the substrate to expose the conductive traces at a first side of the substrate; and mounting the SMD and the substrate to a temporary carrier, wherein the first side of the substrate and the exposed conductive traces are oriented toward the temporary carrier. The substrate may include two laminate layers, a printed circuit board (PCB), or a blank molding compound sheet. The conductive interconnects may include copper bumps, pillars, columns, or thick RDL traces.

The foregoing and other aspects, features, and advantages will become apparent to those skilled in the art from the detailed description, accompanying drawings, and claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows embedded semiconductor dies singulated from a reconstituted sheet 30 .

2A to 2F illustrate the formation of a component assembly, an SMD component assembly, or a 3D interconnect component.

3A to 3F illustrate the formation of a semiconductor component package including a solderable component assembly, an SMD component assembly, or a 3D interconnect component.

DETAILED DESCRIPTION

The present disclosure includes one or more aspects or embodiments in the following description with reference to the accompanying drawings, wherein like numerals represent identical or similar elements. It will be understood by those skilled in the art that the description is intended to cover alternatives, modifications, and equivalents that may be included in the essence and scope of the present disclosure as defined by the appended claims, as well as equivalents as supported by the following disclosure and the accompanying drawings. In the description, many specific details, such as specific configurations, compositions, and procedures, etc., are set forth to provide a thorough understanding of the present disclosure. In other cases, in order not to confuse the present disclosure, the specific details of well-known procedures and manufacturing techniques are not described. In addition, the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

The present disclosure, its aspects, and embodiments are not limited to the specific devices, material types, or other system component examples or methods disclosed herein. Many additional components, manufacturing, and assembly processes known in the art, consistent with manufacturing and packaging, are contemplated for use with specific embodiments of the present disclosure. Thus, for example, although specific embodiments are disclosed, such embodiments and components of implementations may include any components, models, types, materials, versions, quantities, and/or the like, as known in the art, for such systems and components of implementations, consistent with the intended operation.

The words "exemplary," "exemplary," or various forms thereof are used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as "exemplary" or "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects or designs. In addition, the examples are provided for clarity and understanding only and are not intended to limit or define the disclosed subject matter or relevant portions of this disclosure in any way. It should be understood that numerous additional or alternative examples of varying scope may be presented, but are omitted for the sake of brevity.

Where the following examples, embodiments and implementations refer to examples, it will be understood by those skilled in the art that other manufacturing devices and examples may be intermixed with or substituted for the provided devices and examples. Where the above description refers to specific embodiments, it will be apparent that various modifications may be made without departing from the spirit thereof, and it will be apparent that these embodiments and implementations may also be applied to other technologies. Accordingly, the disclosed subject matter is intended to encompass all such alterations, modifications, and variations that fall within the spirit and scope of this disclosure and the knowledge of those skilled in the art.

Semiconductor devices are typically manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves forming multiple dies on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional circuit. Active electrical components, such as transistors and diodes, have the ability to control the flow of electrical current. Passive electrical components, such as capacitors, inductors, resistors, and transformers, establish the relationship between voltage and current required to perform the circuit's function.

Passive and active components are formed above the surface of a semiconductor wafer through a series of process steps, including doping, deposition, photolithography, etching, and planarization. Doping introduces impurities into the semiconductor material through techniques such as ion implantation or thermal diffusion. The doping process modifies the conductivity of the semiconductor material in active devices, turning it into an insulator, a conductor, or dynamically changing its conductivity in response to an electric field or base current. Transistors contain regions configured with the desired type and degree of doping to enable the transistor to promote or restrict the flow of current when an electric field or base current is applied.

Active and passive components are formed from layers of materials having different electrical properties. The layers can be formed by a variety of deposition techniques, which are determined in part by the type of material being deposited. For example, thin film deposition can involve chemical vapor deposition (CVD), physical vapor deposition (PVD), electrolytic plating, and electroless plating procedures. Each layer is typically patterned to form part of an active component, part of a passive component, or part of an electrical connection between components.

The layer can be patterned using photolithography, which involves depositing a photosensitive material (e.g., a photoresist) over the layer to be patterned. Light is used to transfer the pattern from a photomask to the photoresist. In one embodiment, a solvent is used to remove the portion of the photoresist pattern that was exposed to light, thereby exposing the portion of the underlying layer to be patterned. In another embodiment, a solvent is used to remove the portion of the photoresist pattern that was not exposed to light (negative photoresist), thereby exposing the portion of the underlying layer to be patterned. The remainder of the photoresist is removed, leaving the patterned layer. Alternatively, some types of materials are patterned by directly depositing the material in the area or gap formed by the previous deposition/etching process using techniques such as electroless and electrolytic plating.

Patterning is a basic operation that removes portions of the top layer on the surface of a semiconductor wafer. Portions of a semiconductor wafer can be removed using photolithography, photomasks, masks, oxide or metal removal, photography, and stencil printing, as well as microetching. Photolithography involves forming a pattern in a photomask or mask; and transferring the pattern to the surface layer of the semiconductor wafer. Photolithography forms the horizontal dimensions of active and passive components on the surface of a semiconductor wafer in a two-step process. First, the pattern of the photomask or mask is transferred to a photoresist layer. Photoresist is a photosensitive material that undergoes changes in structure and properties when exposed to light. The process of changing the structure and properties of the photoresist occurs as a negative-acting photoresist or a positive-acting photoresist. Second, the photoresist layer is transferred to the wafer surface. The transfer occurs when etching removes the portions of the top layer of the semiconductor wafer that are not covered by the photoresist. The chemical properties of the photoresist allow the photoresist to remain substantially intact and resist removal by chemical etching solutions when removing portions of the top layer of the semiconductor wafer not covered by the photoresist. The procedures for forming, exposing, and removing the photoresist, as well as the procedures for removing a portion of the semiconductor wafer, can be modified depending on the specific photoresist used and the desired results.

In negative-acting photoresists, the photoresist is exposed to light and changes from a soluble state to an insoluble state in a process known as polymerization. In polymerization, the unpolymerized material is exposed to light or an energy source, and the polymer forms a cross-linked material, which is the resist. In most negative photoresists, the polymer is polyisoprene. Removing the soluble portion (i.e., the portion not exposed to light) with a chemical solvent or developer leaves holes in the photoresist layer that correspond to the opaque pattern on the photomask. A photomask in which the pattern exists in the opaque areas is called a clear-field photomask.

In positive-acting photoresists, the photoresist is exposed to light and changes from a relatively insoluble state to a more soluble state in a process known as photosolubilization. In photosolubilization, the relatively insoluble photoresist is exposed to appropriate light energy and converted to a more soluble state. In a developing process, the photosolubilized portions of the photoresist can be removed by a solvent. The basic positive photoresist polymer is a phenol-formaldehyde polymer, also known as phenol-formaldehyde novolac. Removal of the soluble portion (i.e., the portion exposed to light) with a chemical solvent or developer leaves holes in the photoresist layer that correspond to the transparent pattern on the mask. A photomask in which the pattern exists in the transparent areas is called a dark field photomask.

After removing the top portion of the semiconductor wafer not covered by the photoresist, the remainder of the photoresist is removed, leaving behind a patterned layer. Alternatively, some types of materials are patterned by depositing the material directly into areas or voids formed by a previous deposition/etching process using techniques such as electroless and electrolytic plating.

Depositing a thin film of material over an existing pattern can increase the pattern below and create a non-uniform flat surface. A uniform flat surface can be beneficial or necessary for producing smaller and more densely packed active and passive components. Planarization can be used to remove material from the surface of a wafer and produce a uniform flat surface. Planarization involves polishing the surface of a wafer with a polishing pad. During polishing, abrasive materials and corrosive chemicals are added to the surface of the wafer. Alternatively, without the use of corrosive chemicals, mechanical grinding is used for planarization. In some embodiments, pure mechanical grinding is achieved by using a belt grinder, a standard wafer back grinder, or other similar machines. The combined grinding mechanical action and chemical etching remove any irregular topography, thereby resulting in a uniform flat surface.

Back-end manufacturing refers to cutting or singulating the finished wafer into individual semiconductor dies and then packaging the semiconductor dies for structural support and environmental isolation. In order to singulate the semiconductor dies, the wafer is cut along non-functional areas of the wafer called saw streets or scribe lines. The wafer is singulated using a laser cutting tool or a saw blade. After singulation, the individual semiconductor dies are mounted to a package substrate that includes pins or contact pads for interconnection with other system components. The contact pads formed above the semiconductor die are then connected to the contact pads within the package. Electrical connections can be made using solder bumps, stud bumps, conductive paste, redistribution layers, or wire bonding. Encapsulant or other molding material is deposited over the package to provide physical support and electrical isolation. The finished package is then inserted into the electrical system, and the functionality of the semiconductor device is made available to other system components.

An electrical system may be a stand-alone system that uses semiconductor devices to perform one or more electrical functions. Alternatively, the electrical system may be a subcomponent of a larger system. For example, the electrical system may be part of a cellular radiotelephone, part of a personal digital assistant (PDA), part of a digital video camera (DVC), or part of other electronic communication devices. Alternatively, the electrical system may be a graphics adapter, a network adapter, or other signal processing card that can be inserted into a computer. The semiconductor package may include a microprocessor, memory, an application-specific integrated circuit (ASIC), logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor dies or electrical components. Miniaturization and weight reduction may be beneficial or necessary for a product to be accepted by the market. To achieve higher density, the distance between semiconductor devices must be reduced.

By combining one or more semiconductor packages onto a single substrate, manufacturers can incorporate prefabricated components into electronic devices and systems. Because semiconductor packages include complex functionality, electronic devices can be manufactured using less expensive components and streamlined manufacturing processes. The resulting devices are less likely to malfunction and cost less to manufacture, resulting in lower costs for consumers.

However, when packaging one or more semiconductors on a single substrate, forming an RDL layer on top of standard solderable passive components with solder or tinned (Sn) terminations may be impractical because the solder or Sn may melt during subsequent processing, causing electrical failures. Therefore, other alternatives are used to reduce failures, such as using more expensive components with bare Cu terminations rather than using Sn or solderable components, thereby reducing costs by reducing failures. Another alternative to using standard solderable passive components in the case of solder or Sn soldering includes placing SMD passives on the substrate core layer to form embedded dies, devices, or components in the substrate, which allows the use of solderable passive components while reducing the risk of melting solder and Sn during subsequent processing and the resulting failures. However, placing SMD passives in the substrate increases the thickness of the package and requires a much larger prefabricated substrate area, thereby increasing size and cost, both of which are undesirable.

FIG1 shows a cross-sectional view of a plurality of semiconductor dies 14 formed according to the front-end manufacturing methods and processes described above and included in a reconstructed slab, slab, reconstructed wafer, or wafer 30. More specifically, the semiconductor dies 14 can be formed from, or formed as part of, a semiconductor wafer or native wafer having a base substrate material for structural support, such as, but not limited to, silicon, germanium, gallium arsenide, indium phosphide, or silicon carbide. The plurality of semiconductor dies or components 14 can be formed on a native wafer and can be separated by inactive inter-die wafer regions or saw streets as described above. The saw streets provide a dicing area for singulating the semiconductor wafer into individual semiconductor dies 14 for inclusion in the reconstructed slab or wafer 30, which can also include embedded die slabs.

Each semiconductor die 14 has a backside or back surface 18 and an active surface 20 opposite backside 18. Active surface 20 contains analog or digital circuitry implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuitry may include one or more transistors, diodes, and other circuit elements formed within active surface 20 to implement analog or digital circuitry, such as a DSP, ASIC, memory, or other signal processing circuitry. Semiconductor die 14 may also include IPDs for RF signal processing, such as inductors, capacitors, and resistors.

A conductive layer 22 is formed over active surface 20 using PVD, CVD, electrolytic plating, an electroless plating process, or other suitable metal deposition procedures. Conductive layer 22 may be one or more layers of aluminum (Al), copper (Cu), Sn, nickel (Ni), gold (Au), silver (Ag), or other suitable conductive materials. Conductive layer 22 serves as contact pads or bonding pads that are electrically coupled or connected to circuits on active surface 20. Conductive layer 22 may be formed as contact pads arranged side by side at a first distance from the edge of semiconductor die 14, as shown in FIG1 . Alternatively, conductive layer 22 may be formed as contact pads offset in multiple columns such that a first column of contact pads is arranged a first distance from the edge of the die, and a second column of contact pads alternating with the first column is arranged a second distance from the edge of the die.

FIG1 also shows an optional insulating or passivation layer 26 conformally applied over active surface 20 and over conductive layer 22. Insulating layer 26 may include one or more layers applied using PVD, CVD, screen printing, spin coating, spray coating, sintering, thermal oxidation, or other suitable procedures. Insulating layer 26 may include, but is not limited to, one or _{more layers of silicon dioxide (SiO2), silicon nitride (Si3N4 ) ,} silicon oxynitride ( _SiON ), tantalum pentoxide ( _Ta2O5 ), aluminum oxide ( _Al2O3 ), _a polymer, a polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), or other materials with similar insulating and structural properties. Alternatively, semiconductor die 14 may be encapsulated without any PBO layer, and insulating layer 26 may be formed of a different material or omitted entirely. In another embodiment, insulating layer 26 comprises a passivation layer formed over active surface 20 and not over conductive layer 22. When insulating layer 26 is present and formed over conductive layer 22, an opening is formed completely through insulating layer 26 to expose at least a portion of conductive layer 22, thereby enabling subsequent mechanical and electrical interconnection. Alternatively, when insulating layer 26 is omitted, conductive layer 22 is exposed, thereby enabling subsequent electrical interconnection without forming an opening.

FIG1 also shows a conductive interconnect or electrical interconnect structure 28, which can be formed as a pillar, stud, column, thick RDLS, bump, or column formed of copper or other suitable conductive material, disposed above and coupled to or connected to conductive layer 22. Conductive interconnect 28 can be formed directly on conductive layer 22 using a patterning and metal deposition process such as printing, PVD, CVD, sputtering, electrolytic plating, electroless plating, metal evaporation, metal sputtering, or other suitable metal deposition process. Conductive interconnect 28 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, palladium (Pd), or other suitable conductive materials and can include one or more UBM layers. In some embodiments, conductive interconnect 28 can be formed by depositing a photoresist layer over semiconductor die 14 and conductive layer 22. A portion of the photoresist layer may be exposed and removed by an etch-develop process, and conductive interconnects 28 may be formed in the removed portion of the photoresist and over conductive layer 22 in the form of copper pillars using a selective electroplating process. The photoresist layer may be removed, leaving conductive interconnects 28, which provide subsequent mechanical and electrical interconnection and a standoff relative to active surface 20. Conductive interconnects 28 may include a height H1 in the range of 10 to 100 micrometers (μm), or a height in the range of 20 to 50 μm, or a height of approximately 35 μm.

The encapsulant 42 may be deposited around the plurality of semiconductor dies 14 using paste printing, compression molding, transfer molding, liquid encapsulant molding, lamination, vacuum lamination, spin coating, or other suitable applicators. The encapsulant 42 may be a polymer composite material such as a filled epoxy resin, a filled epoxy acrylate, or a polymer containing a suitable filler. The semiconductor dies 14 may be embedded together in the encapsulant 42, which may be non-conductive and environmentally protect the semiconductor dies 14 from external elements and contaminants.

Semiconductor die 14 may be oriented face-up with active surface 20 oriented away from a carrier to which semiconductor die 14 is mounted, or alternatively may be mounted face-down with active surface 20 oriented toward a carrier to which semiconductor die 14 is mounted. Accordingly, adhesive 41 may be included over back surface 18 of semiconductor die 14 or omitted from over back surface 18 of semiconductor die 14, depending on the process used to encapsulate semiconductor die 14 and form sheet 30, which includes semiconductor die 14 fully molded within a core of encapsulant 42 or within an epoxy core.

Sheet material 30 may optionally undergo a curing process to cure encapsulant 42. The surface of encapsulant 42 may be substantially coplanar with adhesive 41. Alternatively, encapsulant 42 may be substantially coplanar with backside 18, exposed by removing the carrier and interface layer. Sheet material 30 may comprise a footprint or form factor of any shape and size, including circular, rectangular, or square, such as a form factor similar to that of a 300 mm semiconductor wafer having a circular footprint with a diameter of 300 millimeters (mm). Any other desired size may also be formed.

The sheet 30 may undergo an optional grinding operation using a grinder to flatten the surface and reduce the thickness of the sheet 30. Chemical etching may also be used to remove and flatten a portion of the encapsulant 42 in the sheet 30. Thus, the surface of the conductive interconnect 28 may be exposed at the edge or periphery of the sheet 30 relative to the encapsulant 42 to provide an electrical connection between the semiconductor die 14 and a subsequently formed redistribution layer or interconnect structure. The sheet 30 may be singulated into individual embedded semiconductor dies 44 using a saw blade or laser cutting tool 32 through the gaps or saw streets 40. The embedded semiconductor dies 44 may then be used as part of a subsequently formed semiconductor component package, as discussed in more detail below. However, the embedded semiconductor dies 44 may also be fully testable after the conductive interconnect 28 is applied and before the embedded semiconductor dies 44 are singulated from the sheet 30 or assembled into the reconstituted sheet 112 shown in FIG. 3C .

In some cases, embedded semiconductor die 44 may be formed as described in U.S. patent application Ser. No. 13/632,062 (now U.S. Pat. No. 8,535,978), filed Apr. 29, 2015, and entitled “Die Up Fully Molded Fan-out Wafer Level Packaging,” the disclosure of which is incorporated herein by reference in its entirety.

2A illustrates a cross-sectional profile of a substrate, laminate, printed circuit board (PCB), or stock mold compound sheet 50. The substrate 50 may include conductive traces 54 formed over a first surface 56 of a substrate core or core material 52, and solder pads 58 formed over a second surface 60 of the substrate core or core material 52, opposite the first surface 56. When the substrate 50 is formed as a stock mold compound sheet, the core material 52 may include the same, similar, or functionally equivalent materials or material properties as the encapsulant 42, the encapsulant or first mold compound 78, or the second encapsulant or mold compound 110.

Conductive traces 54 and solder pads 58 may be patterned and deposited over substrate core 52 of substrate 50. In some cases, conductive traces 54 may be formed on both as one or more redistribution layers (RDLs) or RDL patterns, which may be formed on or over only first surface 56, only second surface 60, or both first surface 56 and second surface 60. Similarly, solder pads 58 may be formed on or over only first surface 56, only second surface 60, or both first surface 56 and second surface 60.

Conductive traces 54, solder pads 58, or both may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, Ti/Cu, TiW/Cu, or coupling agent/Cu or other suitable conductive materials. Conductive traces 54, solder pads 58, or both may be formed using PVD, CVD, electrolytic plating, electroless plating, or other suitable processes. In one embodiment, conductive traces 54, solder pads 58, or both may include a Ti barrier layer, a Cu seed layer, and a Cu layer formed over the Ti barrier layer and the Cu seed layer, and may provide electrical interconnection with components subsequently mounted to the substrate or laminate 50. In some cases, the substrate or laminate 50 may be purchased or obtained as a pre-formed or pre-fabricated item, and the two-layer laminate substrate 50 may include a core 52 of 130 microns (μm) or about 130 μm (such as in the range of 30 to 200 μm).

An insulating layer or passivation layer 62 may be disposed over conductive traces 54 and first surface 56. Similarly, an insulating layer or passivation layer 64 may be disposed over solder pads 58 and second surface 60. Insulating layers 62 and 64 may be one or more layers of SiO ₂ , Si ₃ N ₄ , SiON, Ta ₂ O ₅ , Al ₂ O ₃ , polyimide, BCB, PBO, epoxy, solder resist, or other materials having similar insulating and structural properties, formed by PVD, CVD, screen printing, spin coating, spray coating, lamination, sintering, or thermal oxidation. In some cases, insulating layers or passivation layers 62 and 64 may be included in a preformed or prefabricated substrate or laminate 50. Openings 68 in insulating layer 64 may be formed over portions of solder pads 58 to facilitate subsequent electrical interconnection with one or more terminals or contact pads 72 on a surface mount device (SMD), such as SMD 70 shown in FIG. 2B .

2B shows that the terminals 72 of the SMD 70 are surface mounted to the substrate or laminate layer 50 using solder or solder paste 74. The SMD 70 can have the desired size and include passive components, active components, solderable passive components (such as resistors or capacitors), other semiconductor dies, ICs, wafer-level chip scale packages (WLCSPs), and other components. The size of the SMD 70 can be set according to the JDEC standard using metric or imperial codes, where the metric code gives the length and width of the SMD component in tens of millimeters, and the imperial code gives the length and width of the SMD component in hundreds of inches, with some exceptions. In some cases, a 0201 SMD package size can be used, which includes a size of approximately 0.25mm×0.125mm (or .0098in×0.0049in). In other cases, the size of the 0201 package can include a size of 0.6mm×0.3mm (or 0.024in×0.012in). Regardless, in some cases, the size of the SMD may be selected to be consistent with the overall configuration and design of the final package, as described in more detail below.

Solder 74 may be placed on the solder pads 58 to facilitate electrical communication between the SMD 70 and the substrate 50. The solder 74 may include Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, along with an optional flux solution. For example, the solder 74 may be eutectic Sn/Pb, high-lead solder, or lead-free solder. The solder 74 may be deposited over the substrate 50 and on the solder pads 58 using evaporation, electrolytic plating, electroless plating, ball drop, or screen printing processes. In some embodiments, the solder 74 is a Sn solder paste that is deposited over the substrate 50 and on the solder pads 58 using screen printing. After the SMD 70 is coupled to the substrate 50 with the solder 74, the solder 74 may undergo a reflow process or be reflowed to improve electrical contact between the SMD 70 and the solder pads 58. After reflow, the substrate 50 and SMDs 70 may optionally undergo one or more of aqueous cleaning, automated optical inspection (AOI), and plasma cleaning.

FIG2C shows that a first encapsulant or molding compound 78 can be optionally deposited around the plurality of SMDs 70 using paste printing, compression molding, transfer molding, liquid encapsulant molding, lamination, vacuum lamination, spin coating, or other suitable applicators. Encapsulant 78 can be a polymer composite material, such as a filled epoxy resin, a filled epoxy acrylate, or a polymer containing an appropriate filler. In some cases, encapsulant 78 can be the same as or similar to the encapsulant 42 used in forming the embedded semiconductor die 44. The SMDs 70 can be embedded together on the substrate 50 in the encapsulant 78, which can be non-conductive and environmentally protect the SMDs 70 from external elements and contaminants. After molding or encapsulation, the molded substrate 50 and the SMDs 70 can undergo post-mold cleaning (PMC) and testing to identify and mark any bad, defective, or non-functioning SMDs 70 within the molded substrate. Although the encapsulant or first mold compound 78 is shown formed or disposed around the SMD 70 to facilitate or make it easier to mount the final component assembly 82 to the temporary carrier 100, as shown in FIG3A , the encapsulant or first mold compound 78 may be optional and may be omitted entirely. In some embodiments, where the encapsulant or first mold compound 78 is entirely optional, mounting the final component assembly 82 to the temporary carrier 100 may be performed in the absence of the encapsulant or first mold compound 78.

As shown in FIG2D , the molded substrate 50 can then be singulated between the SMDs 70 using a saw blade or laser cutting tool 80 into individual component assemblies, SMD component assemblies, or 3D interconnected components 82 including the mold cover of the encapsulant 78. Singulation of the molded substrate 50 can separate the substrate 50 to expose the conductive traces 54 and form a plurality of component assemblies or SMD component assemblies 82. The component assemblies 82 can include exposed conductive traces 84, including conductive traces 54, solder pads 58, or both. The exposed conductive traces 84 can be exposed on only a first side 86 of the component assembly 82, only a second side 88 of the component assembly 82, or both the first side 86 and the second side 88, wherein the first side 86 can be opposite the second side 88. For mounting the component assemblies 82, the first side 86 and the second side 88 can be flat, planar, or substantially so. Component assembly 82 may include a height H in the range of 0.4 to 0.8 mm, 0.5 to 0.7 mm, or approximately 0.6 mm (such as 0.62 mm). Height H may be the sum of mold compound height Hm and substrate height Hs. Mold compound height Hm may be in the range of 0.1 to 0.3 mm, or approximately 0.2 mm, such as 0.22 mm. Mold compound height Hs may be in the range of 0.2 to 0.6 mm, or approximately 0.4 mm. Component assembly 82 may also have a length L in the range of 0.9 to 1.3 mm, 1.0 to 1.2 mm, or approximately 1.1 mm.

FIG2E shows a cross-sectional profile view of component assembly 82, illustrating the width W of component assembly 82 and illustrating an orientation of component assembly 82 that is perpendicular or orthogonal to the orientation of the view shown in FIG2D . Width W of component assembly 82 may be in the range of 0.2 to 0.6 mm, 0.3 to 0.5 mm, or approximately 0.4 mm, such as 0.43 mm. Although exemplary measurements of length L, width W, and height H of component assembly 82 are given with reference to 0201 SMD 70, SMDs of different sizes may also be used, resulting in corresponding differences in the size of length L, width W, and height H of component assembly 82. The view of FIG2E also shows exposed conductive traces 84 on first side 86 of component assembly 82 and second side 88 of component assembly 82, which may be used for subsequent electrical connection and packaging integration, as discussed with respect to FIG3A through FIG3F .

2F shows a perspective view of component assembly 82 with exposed conductive traces 84 visible on a first side 86 of the component assembly. FIG2F also shows the relative positioning and orientation of the length L, width W, and height H of component assembly 82.

FIG3A shows a temporary carrier or substrate 100 comprising a temporary or sacrificial base material, such as silicon, a polymer, stainless steel, or other suitable low-cost rigid material for structural support. An optional interface layer or double-sided tape 102 may be formed over the temporary carrier 100 to serve as a temporary adhesive film or etch stop layer. In one embodiment, the carrier 100 may be an annular film frame with an open center portion that supports the tape 102 around its perimeter.

One or more (e.g., multiple) component assemblies 82 can be mounted to the temporary carrier 100 and the interface layer 102, with the first side 86 of the component assembly 82 and the exposed conductive traces 84 oriented toward the temporary carrier 100, and the conductive traces 54 oriented vertically. Accordingly, the second side 88 of the component assembly 82 and the opposite end of the exposed conductive traces 84 can be oriented away from the temporary carrier 100, or facing upward, to enable subsequent vertical interconnection within the final semiconductor component package. Thus, the component assembly 82 can be vertical from a horizontal position maintained on the unsingulated substrate 50, or rotated 90 degrees relative to the horizontal position. Thus, the conductive traces 54 can adopt a vertical orientation when mounted on the temporary carrier 100, rather than the horizontal orientation maintained when mounted on a portion of the unsingulated substrate 50, with both sides of the component assembly 82 including the exposed conductive traces 84, the exposed solder pads 58, or both.

FIG3B shows embedded semiconductor die 44 of FIG1 mounted face-up onto temporary carrier 100 and interface layer 102, with backside 18 oriented toward temporary carrier 100 and active surface 20 oriented away from temporary carrier 100. Semiconductor die 14 can be placed onto temporary carrier 100 using a pick-and-place operation or other suitable operation. As shown in FIG1 , adhesive 41 can optionally be disposed between backside 18 of semiconductor die 14 and temporary carrier 100. Adhesive 41, when present, can be a thermal epoxy, epoxy resin, a B-stage epoxy film, an ultraviolet (UV) B-stage film with an optional acrylic polymer, or other suitable material. In one embodiment, adhesive 41 can be disposed onto backside 18 before semiconductor die 14 is mounted onto temporary carrier 100. Alternatively, adhesive 41 can be disposed onto temporary carrier 100 before embedded semiconductor die 44 is mounted onto temporary carrier 100. In other embodiments, embedded semiconductor die 41 may be mounted directly to interface layer or support tape 102 or temporary carrier 100 without the use of adhesive 41 .

Each embedded semiconductor die 44 can be mounted to a temporary carrier 100, with each embedded semiconductor die 44 adjacent to or laterally contacting a corresponding component assembly 82. When mounted above the temporary carrier 100, the pairs of embedded semiconductor dies 44 and component assemblies 82 can be separated by spaces or gaps 104 to provide saw streets or spacings 104 for subsequently formed semiconductor component packages. In some cases, a portion of the spaces 104 can be used for subsequently formed fan-out interconnect structures. Although Figures 3A and 3B show that the component assemblies 82 are mounted to the temporary carrier 100 before the embedded semiconductor dies 44, in other cases, the embedded semiconductor dies 44 can be first mounted to the temporary carrier 100 before the component assemblies 82. During the process of mounting the embedded semiconductor dies 44 and component assemblies 82 to the temporary carrier 100, the component assemblies 82 can also be mounted, coupled, or attached to the embedded semiconductor dies 44. For mounting, component assembly 82 may also be flipped over, such as with its first side 86 oriented toward temporary carrier 100, so that conductive traces 54 are oriented vertically rather than horizontally, thereby allowing conductive traces 54 to provide vertical interconnects extending completely through final semiconductor component package 142, between front surface 116 and back surface 118 of reconstituted sheet 112 or semiconductor component package 142. In another instance, component assembly and SMD 70 may be mounted horizontally, or rotated 90 degrees relative to that shown in FIG3B , so that conductive traces 54 are parallel or substantially parallel to temporary carrier 100, such as within 0 to 10 degrees, 0 to 5 degrees, or 0 to 1 degree.

3C illustrates encapsulating a plurality of component assemblies 82 and embedded semiconductor dies 44 or 14 using a second encapsulant or mold compound 110 formed around component assemblies 82, embedded semiconductor dies 44, or 14 and formed within spaces 104 while singulated component assemblies 82, embedded semiconductor dies 44, and semiconductor dies 14 are mounted to temporary carrier 100 to form reconstituted sheet or wafer 112. Second encapsulant 110 may be similar to or identical to first encapsulant 78, encapsulant 42, or both, and may be deposited using paste printing, compression molding, transfer molding, liquid encapsulant molding, lamination, vacuum lamination, spin coating, or other suitable applicators. The second encapsulant 110 can be a polymer composite material, such as a filled epoxy, a filled epoxy acrylate, or a suitably filled polymer, which can be non-conductive and environmentally protect the embedded semiconductor die 44 and the component assembly 82 from external elements and contaminants. In some cases, the reconstituted sheet or wafer 112 can also include at least one via or vertical interconnect within the substrate, extending between a bottom surface 116 and a top surface 118 of the reconstituted sheet 112 and can be exposed at both the bottom surface 116 and the top surface 118 of the reconstituted sheet 112.

The reconstituted sheet 112 may undergo a grinding operation using a grinder 114 to planarize a front surface 116 of the reconstituted sheet 112 and reduce the thickness of the reconstituted sheet 112. Chemical etching may also be used to remove and planarize a portion of the reconstituted sheet 112. The grinding operation may expose the conductive interconnects 28 of the embedded semiconductor die 44 and the exposed conductive traces 84 at the first side 86 of the component assembly 82 relative to the second encapsulant 110. The reconstituted sheet 112 may also undergo a grinding operation using a grinder 114 to planarize a back surface 118 of the reconstituted sheet 112 and reduce the thickness of the reconstituted sheet 112. The grinding operation may also expose the exposed conductive traces 84 at the second side 88 of the component assembly 82 relative to the second encapsulant 110.

FIG3D shows a first build-up interconnect structure 120 formed over the front surface 116 of the reconstituted sheet 112. The build-up interconnect structure 120 can include any desired number of conductive and insulating layers, depending on the configuration, design, and routing requirements of the final device or semiconductor component package 142. A non-limiting example of the build-up interconnect structure 120 is shown and described with respect to FIG3D. The build-up interconnect structure 120 can include a conductive layer or redistribution layer (RDL) 124 patterned and deposited over the embedded semiconductor die 44 (including the conductive interconnects 28) and the component assembly 82 (including the solder pads 58 and the exposed conductive traces 84). In some cases, the conductive layer 124 can be formed directly over or in contact with the front surface 116 of the reconstituted sheet 112. In other cases, an intermediate insulating or passivation layer 122 can be formed over or between the conductive layer 124 and the front surface 116. When the intermediate insulating layer or passivation layer 122 is present, the insulating layer 122 may be one or more layers of SiO ₂ , Si ₃ N ₄ , SiON, Ta ₂ O ₅ , Al ₂ O ₃ , polyimide, BCB, PBO, or other materials having similar insulating and structural properties formed by PVD, CVD, screen printing, spin coating, spray coating, sintering, or thermal oxidation.

Conductive layer 124 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, Ti/Cu, TiW/Cu, or coupling agent/Cu or other suitable conductive materials. Conductive layer 124 may be formed using PVD, CVD, electrolytic plating, electroless plating, or other suitable procedures. In one embodiment, conductive layer 124 is an RDL comprising a TiW seed layer, a Cu seed layer, and a Cu layer formed above the TiW seed layer and the Cu seed layer. Conductive layer 124 may provide electrical interconnects between conductive interconnects 28, solder pads 58, exposed conductive traces 84, and other features within the completed semiconductor component package 142 in order to transmit electrical signals between points within the completed semiconductor component package.

When the position of the embedded semiconductor die 44 and component assembly 82 is shifted from its nominal position, such as during placement and encapsulation on the temporary carrier 100 to form the reconstituted sheet 112, the true or actual position of the embedded semiconductor die 44 and component assembly 82 may not be sufficiently aligned with the nominal design of the build-up interconnect structure 120 or the conductive layer 124 to provide the desired reliability of the package interconnect given the desired routing density and pitch tolerance. When the positional shift of the embedded semiconductor die 44 and component assembly 82 is small, it may not be necessary to adjust the position of the conductive layer 124 to properly align the conductive layer 124 with the embedded semiconductor die 44 and component assembly 82. However, when the position of the embedded semiconductor die 44 and the component assembly 82 within the reconstitution sheet 112 varies such that the nominal position does not provide adequate alignment with and exposure of the conductive layer 122, the position of the build-up interconnect structure 120 can be adjusted by Adaptive Patterning ^™ or cell-specific patterning (hereinafter, "cell-specific patterning") as described in more detail in U.S. patent application Ser. No. 13/891,006, filed May 9, 2013, the disclosure of which is incorporated herein by reference. Thus, the position, alignment, or both of the interconnect structure 120 and the conductive layer 124 can be adjusted by xy translation, by rotation through an angle θ, by both, or by relative to their nominal position or relative to a reference point or fiducial on the reconstitution sheet 112, thereby maintaining constant alignment between the embedded semiconductor die 44 and the module package outline and between the component assembly 82 and the module package outline.

FIG3D further shows an insulating layer or passivation layer 126 conformally applied over and in contact with the conductive layer 124 and the insulating layer 122 (if present). The insulating layer 126 may be one or more layers of SiO ₂ , Si ₃ N ₄ , SiON, Ta ₂ O ₅ , Al ₂ O ₃ , polyimide, BCB, PBO, dry film resist, or other materials having similar insulating and structural properties, applied using PVD, CVD, screen printing, spin coating, spray coating, sintering, thermal oxidation, or other suitable processes. The insulating layer 126 may be patterned, and portions of the insulating layer 126 may be removed by etching, laser drilling, mechanical drilling, or other suitable processes to form openings completely through the insulating layer 126 to expose the conductive layer 124. The openings in the insulating layer 126 may be used to receive bumps, balls, or interconnect structures 128.

Bump 128 can be formed by depositing a conductive bump material over a portion of conductive layer 124 (which can be formed as an under-bump metallization (UBM) pad) using evaporation, electrolytic plating, electroless plating, ball drop, or screen printing processes. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, along with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material can be bonded to conductive layer 124 using a suitable attachment or bonding process. In one embodiment, the bump material can be reflowed by heating the bump material to above its melting point to form bump 128. In some applications, bump 128 is reflowed a second time to improve electrical contact to conductive layer 124. Bump 128 can also be compression bonded or thermocompression bonded to conductive layer 124. Bump 128 represents one type of interconnect structure that may be formed over conductive layer 124. Bump 128 may also include a stud bump, a microbump, or other electrical interconnect.

3E shows the reconstituted sheet 112 with the first build-up interconnect structure 120 formed thereon, and the reconstituted sheet 112 removed from the temporary carrier 100, after which the temporary carrier may optionally undergo a grinding operation (similar to the grinding operation of FIG. 3C , but on the back surface 118 rather than the front surface 116) to planarize the back surface 118, thereby reducing the thickness of the reconstituted sheet 112 and exposing the exposed conductive traces 84 at the second side 88 of the component assembly 82 relative to the second encapsulant 110 or the back surface 118. Thus, in various embodiments, the exposed conductive traces 84 (e.g., conductive traces 54 and solder pads 58) may be exposed at only the first side 86, only the second side 88, or both the first side 86 and the second side 88. In some cases, the exposed conductive traces 84 are exposed relative to the second encapsulant 110, while in other cases, the exposed conductive traces 84 are exposed at the first side 86, the second side 88, or both.

With the exposed conductive traces 84 exposed at the second side 88 of the component assembly 82, a second build-up interconnect structure 130 can be formed over the back surface 118 of the reconstituted sheet 112. The build-up interconnect structure 130 can include any desired number of conductive and insulating layers, depending on the configuration, design, and routing requirements of the final device or semiconductor component package 142. A non-limiting example of the build-up interconnect structure 130 is shown and described with respect to FIG. 3E. The build-up interconnect structure 130 can include a conductive layer or redistribution layer (RDL) 134 that is patterned and deposited over the embedded semiconductor die 44 and over the component assembly 82 (including the solder pads 58 and the exposed conductive traces 84). In some cases, the conductive layer 134 can be formed directly on or in contact with the back surface 118 of the reconstituted sheet 112. In other cases, an intermediate insulating layer or passivation layer 132 may be formed on or between the conductive layer 134 and the back surface 118. When the intermediate insulating layer or passivation layer 132 is present, the insulating layer 132 may be one or more layers of SiO ₂ , Si ₃ N ₄ , SiON, Ta ₂ O ₅ , Al ₂ O ₃ , polyimide, BCB, PBO, or other materials having similar insulating and structural properties formed by PVD, CVD, screen printing, spin coating, spray coating, sintering, or thermal oxidation.

Conductive layer 134 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, Ti/Cu, TiW/Cu, or coupling agent/Cu or other suitable conductive materials. Conductive layer 134 may be formed using PVD, CVD, electrolytic plating, electroless plating, or other suitable procedures. In one embodiment, conductive layer 134 is an RDL or fan-out RDL comprising a TiW seed layer, a Cu seed layer, and a Cu layer formed above the TiW seed layer and the Cu seed layer. In order to transmit electrical signals between points within the completed semiconductor component package, conductive layer 134 may provide electrical interconnection between solder pads 58, exposed conductive traces 84, and other features within the completed semiconductor component package 142.

When the position of the embedded semiconductor die 44 and component assembly 82 is varied from its nominal position, such as during placement and encapsulation on the temporary carrier 100 to form the reconstituted sheet 112, the true or actual position of the embedded semiconductor die 44 and component assembly 82 may not be sufficiently aligned with the nominal design of the build-up interconnect structure 130 or conductive layer 134 to provide the desired reliability of the package interconnect given the desired routing density and pitch tolerance. When the position variation of the embedded semiconductor die 44 and component assembly 82 is small, it may not be necessary to adjust the position of the conductive layer 134 to properly align the conductive layer 134 with the embedded semiconductor die 44 and component assembly 82. However, when the position variation of the embedded semiconductor die 44 and component assembly 82 within the reconstituted sheet 112 is such that the nominal position does not provide adequate alignment with and exposure of the conductive layer 132, the position of the build-up interconnect structure 130 may be adjusted through cell-specific patterning. Thus, the position, alignment, or both of the interconnect structure 130 and the conductive layer 134 can be adjusted by x-y movement, by rotation through an angle θ, by both, or by relative to their nominal positions or relative to a reference point or fiducial on the reconstitution sheet 112 to maintain constant alignment between the embedded semiconductor die 44 and the module package outline and between the component assembly 82 and the module package outline.

FIG3E further shows an insulating layer or passivation layer 136 conformally applied over and in contact with the conductive layer 134 and the insulating layer 132 (if present). The insulating layer 136 may be one or more layers of SiO ₂ , Si ₃ N ₄ , SiON, Ta ₂ O ₅ , Al ₂ O ₃ , polyimide, BCB, PBO, dry film resist, or other materials having similar insulating and structural properties, applied using PVD, CVD, screen printing, spin coating, spray coating, sintering, thermal oxidation, or other suitable processes. The insulating layer 136 may be patterned, and portions of the insulating layer 136 may be removed by etching, laser drilling, mechanical drilling, or other suitable processes to form openings 138 extending completely through the insulating layer 136 to expose the conductive layer 134. The opening 138 in the insulating layer 136 can expose a portion of the conductive layer 134 (which is formed in the form of a package-on-package (POP) solder pad or SMD solder pad 139 on the top routing layer of the second build-up interconnect structure 130) for receiving bumps, balls, or interconnect structures 128 and other devices, packages, SMDs, surface mount devices (SMDs), surface mount components (such as packaged ICs, passive components, connectors, mechanical parts, EMI shielding), or mounting to a substrate or other device.

After forming the first build-up interconnect structure 120 and the second build-up interconnect structure 130 , the reconstituted sheet and the first build-up interconnect 120 and the second build-up interconnect 130 may be singulated into individual semiconductor component packages 142 using a saw blade or laser cutting tool 140 .

FIG3F shows an enlarged view of semiconductor package 142 of FIG3E . As shown, reconstituted sheet or wafer 112 may include a height H1 of approximately 0.43 mm, and an overall package height H2, including the heights of first and second build-up interconnect structures 120, 130, may be 0.5 mm, or approximately 0.5 mm, such as 0.3 mm to 0.7 mm. First and second build-up interconnect structures 120, 130 may be coupled to through-mold conductive traces 54 and solder pads 58 of SMD 70 and directly electrically connect to through-mold conductive traces 54 and solder pads 58 of SMD 70, thereby providing vertical electrical interconnection between bottom surface 144 of package 142 and top surface 146 of package 142. In some cases, component assembly 82 may be sawn to slightly greater than the finished height or thickness H1 so that conductive traces 54 running vertically through the mold may be exposed during top and bottom grinding steps, such as during grinding of front surface 116 using grinder 114 as shown in FIG. 3C and during grinding of back surface 118 before forming second build-up interconnect structure 130, as shown in FIG. 3E .

The improved integration and reduced size of the semiconductor package 142, including the inclusion of component assemblies 82 with solder or Sn connections 74, is particularly suitable for small electronic systems (such as smart meters) and other IoT devices that require a reduced form factor or the smallest possible form factor. A method of embedding the solderable component 82 within the core of a 3D fan-out wafer-level package or semiconductor component package 142 may include: attaching passive or active components 70 to a substrate or PCB strip 50 using solder reflow; overmolding the strip to encapsulate the components 70; dicing the strip to form discrete molded components 82; and placing at least one molded component assembly 82 on a temporary carrier 100 such that the conductive traces 54 within the component assembly 82 are vertically oriented and the first side surface 86 is oriented toward and attached to the carrier 100.

The method may also include placing at least a semiconductor die 14 having conductive interconnects 28 or plated Cu bumps on a temporary carrier 102, the semiconductor die 14 being adjacent to a component assembly or molded passive component 82; encapsulating the temporary carrier 100 to form a reconstructed sheet or wafer 112; grinding the reconstructed sheet 112 to expose the conductive interconnects or Cu bumps 28 on the semiconductor die 14 and the conductive traces 54 within the molded component 82 (at least two of the conductive traces 54 being electrically connected to the SMD, passive component, or active component 70) without exposing the solder 74 within the embedded component assembly or molded component 82; and forming a first build-up interconnect structure or redistribution layer 120 on the reconstructed sheet 112 to electrically connect at least one contact pad 22 on the semiconductor die 14 to at least one terminal 72 on the SMD or embedded passive component 70. Optionally, a second build-up interconnect structure or redistribution layer 130 may be formed on an opposite second surface or side 118 of the reconstituted sheet 112 to contact at least one of the conductive traces 54 within the component assembly or discrete molded assembly 82, such that an electrical connection is made through the height H1 or thickness of the semiconductor component package 142 to the contact pads or bonding pads 22 on the semiconductor die 14.

As shown in FIG. 3F , the semiconductor component package 142 may include one or more semiconductor dies 14 and SMD technology 70, which may include other semiconductor dies, ICs, passive devices, wafer-level chip scale packages (WLCSPs), and other components, mounted to the embedded semiconductor die 44 and included within the semiconductor component package 142, rather than having the SMD 70 mounted to a well-known substrate or PCB and offset from the semiconductor die 14 or embedded semiconductor die 44, which is also mounted to the well-known substrate or PCB.

Thus, the semiconductor component package 142 can provide many advantages, including: integration and use of standard, low-cost 0201 passive components with Sn terminations; the SMD 70 includes a flat first side surface 86 for easy mounting to the interface layer or carrier material 102; the conductive traces 54 pass through the height H1 of the semiconductor component package 142 to be used or operated as a 3D or vertical interconnect structure to achieve a PoP configuration; the 0201 passive components are integrated into a body thickness of 0.5 mm; it is compatible with fully molded wafer-level fan-out semiconductor package designs (including Deca M-Series ^™ packages); and external component assembly does not require additional internal procedures or equipment and does not require additional cycle time.

In some variations of semiconductor component package 142, the length L of component assembly 82 can be extended to include more SMDs or passives 70 and more through-mold conductive traces 54. In some cases, substrate 50 can be formed as a multi-layer substrate to add additional through-mold conductive traces 54. In other cases, SMDs or passives 70 can be mounted on opposing first surface 56 and second opposing surface 60 of substrate 50 or substrate core 52. When SMDs 70 are mounted on opposing surfaces of substrate 50, one or both sides of substrate 50 with SMDs 70 can be molded or encapsulated. In other cases, small active Si semiconductor dies can be incorporated into substrate 50 with SMDs 70. Furthermore, in the case where the SMD 70 is included within a semiconductor component package 142 including a single-sided (2D) package structure, the 2D package structure can be formed without a second build-up interconnect structure or RDL 130 such that the component assembly 82 can be mounted to the interface layer or sheet carrier 102 in a horizontal orientation, and the substrate or lead frame 50 can face upward such that the POP or SMD solder pads 139 are exposed during a sheet grinding process or pre-grinding process, as shown in FIG. 3C .

Although the present disclosure includes multiple embodiments in different forms, the details of specific embodiments are presented in the accompanying drawings and the description written below, and it is understood that the present disclosure is regarded as an example and principle of the disclosed method and system, and is not intended to limit the broad aspects of the disclosed concepts to the illustrated embodiments. In addition, it should be understood by those skilled in the art that other structures, manufacturing devices and examples can be mixed with or replace the provided devices and examples. Where reference is made to specific embodiments in the above description, it should be apparent that various modifications can be made without departing from their essence, and it should be apparent that these embodiments and embodiments can also be applied to other technologies. Therefore, the disclosed objects are intended to encompass all such changes, modifications and variations, which all fall within the spirit and scope of the present disclosure and the knowledge of those skilled in the art. Therefore, it is apparent that various modifications and changes can be made to them without departing from the broader spirit and scope of the present invention as set forth in the appended claims. Therefore, the description and the accompanying drawings should be viewed in an illustrative sense rather than a restrictive sense.

Claims (20)

1. A method for preparing a semiconductor component package, comprising: A substrate including conductive traces is provided; Multiple surface mount devices (SMDs) are soldered to the substrate using solder. The plurality of SMDs on the substrate are encapsulated over and around the plurality of SMDs using a first molding compound; The plurality of SMDs are individually cut by separating the substrate to expose the conductive traces and form a plurality of component assemblies, the plurality of component assemblies including exposed conductive traces at a first side and a second side of the component assembly, the second side of the component assembly being opposite to the first side of the component assembly; Provide temporary carriers; At least one of the component assemblies is mounted to the temporary carrier, wherein the first side of the at least one component assembly and the exposed conductive trace are oriented toward the temporary carrier; A semiconductor wafer including conductive interconnects is mounted to the temporary carrier adjacent to at least one of the component assemblies; When the at least one diced component assembly and the semiconductor wafer are mounted onto the temporary carrier, the at least one of the component assemblies and the semiconductor wafer are encapsulated with a second molding compound to form a reconstructed substrate; The conductive interconnect and the exposed conductive trace are exposed relative to the second molding compound at the first or second side of the at least one component assembly; A first redistribution layer is formed over the second molding compound to electrically connect the conductive interconnects and the exposed conductive traces; and The reconstructed plate is cut into single sections. 2. The method according to claim 1, wherein the substrate comprises two laminates, a printed circuit board (PCB), or a preform molding compound substrate. 3. The method of claim 1, wherein the component assembly includes a passive device. 4. The method of claim 1, wherein the semiconductor wafer is an embedded semiconductor wafer, the embedded semiconductor wafer including the conductive interconnects coupled to the semiconductor wafer and exposed relative to the second molding compound. 5. The method of claim 1, wherein the conductive interconnect comprises copper bumps or pillars. 6. The method of claim 1, wherein the solder coupling at least one of the single-cut component assemblies to the substrate is contained within the semiconductor component package and is not exposed relative to the semiconductor component package. 7. A method for preparing a semiconductor component package, comprising: A substrate including conductive traces is provided; Surface mount devices (SMDs) are attached to the substrate using solder to form component assemblies; The component assembly is mounted to a temporary carrier, wherein a first side of the component assembly is oriented toward the temporary carrier; A semiconductor wafer including conductive interconnects is mounted adjacent to the component assembly to the temporary carrier; When the component assembly and the semiconductor wafer are mounted to the temporary carrier, the component assembly and the semiconductor wafer are encapsulated with a molding compound to form a reconfigurable substrate; and The conductive interconnects and conductive traces are exposed relative to the molding compound on the first or second side of the component assembly. 8. The method of claim 7, wherein the substrate comprises two laminates, a printed circuit board (PCB), or a preform molding compound substrate. 9. The method of claim 7, further comprising, prior to mounting the component assembly to the temporary carrier, encapsulating the SMD on the substrate above and around the SMD using an additional molding compound. 10. The method of claim 7, wherein the semiconductor wafer is an embedded semiconductor wafer, the embedded semiconductor wafer including conductive interconnects coupled to the semiconductor wafer and exposed relative to the molding compound, wherein the conductive interconnects include copper bumps or pillars. 11. The method of claim 7, wherein the solder that couples the component assembly to the substrate is contained within the component assembly and is not exposed relative to the component assembly. 12. The method of claim 7, wherein exposing the conductive interconnects and the conductive traces further comprises removing the temporary carrier from the reconstructed substrate and grinding the reconstructed substrate. 13. The method of claim 7, further comprising: A first redistribution layer is formed over the reconstructed substrate to electrically connect the conductive interconnects and the conductive traces; and A second redistribution layer is formed opposite to the first redistribution layer to electrically connect with the exposed conductive traces to form an electrical connection through the thickness of the semiconductor component package. 14. A method for preparing a semiconductor component package, comprising: A substrate including conductive traces is provided; Surface mount devices (SMDs) are attached to the substrate using solder; The SMD and the substrate are mounted onto a temporary carrier; A semiconductor module comprising conductive interconnects is mounted adjacent to the SMD. The molding compound is dispensed above the temporary carrier; and The conductive interconnects and the conductive traces are exposed relative to the molding compound and on the same surface of the molding compound. 15. The method of claim 14, further comprising mounting the semiconductor wafer including the conductive interconnects adjacent to the temporary carrier. 16. The method of claim 14, further comprising mounting the semiconductor wafer including the conductive interconnect adjacent to the SMD. 17. The method of claim 14, further comprising dispensing a molding compound to encapsulate the SMD and the semiconductor wafer, thereby forming a reconstructed substrate. 18. The method of claim 14, further comprising: The substrate is diced to expose the conductive traces on a first side of the substrate; and The SMD and the substrate are mounted to the temporary carrier, wherein the first side of the substrate and the exposed conductive traces are oriented toward the temporary carrier. 19. The method of claim 14, wherein the substrate comprises two laminates, a printed circuit board (PCB), or a preform molding compound substrate. 20. The method of claim 14, wherein the conductive interconnect comprises copper bumps or pillars.