HK1243825A1 - Integrated device package comprising a magnetic core inductor with protective ring embedded in a package substrate - Google Patents

Description

Integrated device package including magnetic core inductor with guard ring embedded in package substrate

Cross Reference to Related Applications

This application claims priority and benefit from provisional application No.62/112,527 filed at united states patent office on day 5/2 2015, and non-provisional application No.14/836,733 filed at united states patent office on day 26/8 2015, which are incorporated herein by reference in their entirety.

Background

FIELD

Various features relate generally to integrated device packages and, more particularly, to integrated device packages including a magnetic core inductor with guard rings embedded in a package substrate.

Background

Fig. 1 illustrates a configuration of an integrated device package including a die. In particular, fig. 1 illustrates an integrated device package 100 that includes a first die 102 and a package substrate 106. The package substrate 106 includes a dielectric layer and a plurality of interconnects 110. The package substrate 106 is a laminate substrate. The plurality of interconnects 110 include traces, pads, and/or vias. The first die 102 is coupled to the package substrate 106 through a first plurality of solder balls 112. The package substrate 106 is coupled to a Printed Circuit Board (PCB)108 by a second plurality of solder balls 116. Fig. 1 illustrates that inductor 120 is mounted on PCB 108. The inductor 120 is located outside of the integrated device package 100 and occupies a large amount of occupied space on the PCB 108.

One drawback of the inductor 120 shown in fig. 1 is that it creates a device with a form factor that may be too large for the requirements of a mobile computing device and/or a wearable computing device. This can result in devices that are too large and/or too thick. That is, the combination of the integrated device package 100, the inductor 120, and the PCB 108 shown in fig. 1 may be too thick and/or have too large a surface area to meet the needs and/or requirements of the mobile computing device and/or the wearable computing device.

Accordingly, there is a need for an integrated device package having a better form factor while meeting the needs and/or requirements of a mobile computing device and/or a wearable computing device.

SUMMARY

Various features relate to an integrated device package including a magnetic core inductor with a guard ring embedded in a package substrate.

One example provides an integrated device package that includes a die and a package substrate coupled to the die. The package substrate includes at least one dielectric layer, a magnetic core in the dielectric layer, a first guard ring, and a first inductor including a plurality of first interconnects. A first inductor is in the package substrate to at least partially surround the magnetic core. The first guard ring includes at least one interconnect of the plurality of first interconnects of the first inductor.

Another example provides a method for manufacturing an integrated device package. The method forms a package substrate, wherein forming the package substrate comprises: forming at least one dielectric layer; providing a magnetic core in the dielectric layer; forming a first metal layer to define a first protection ring in the package substrate; and forming a plurality of first interconnects to define a first inductor in the package substrate. Forming the plurality of first interconnects includes: forming the plurality of first interconnects in the package substrate such that the plurality of first interconnects at least partially surround the magnetic core; and forming an interconnect of the plurality of first interconnects using at least a portion of the first metal layer to define a first inductor. The method couples the package substrate to a die.

Drawings

The various features, properties and advantages will become apparent upon reading the following detailed description in conjunction with the drawings in which like reference characters identify correspondingly throughout.

Fig. 1 illustrates an integrated device package.

Fig. 2 illustrates a cross-sectional view of an example of an integrated device package including a magnetic core inductor with guard ring(s) embedded in a package substrate.

Fig. 3 illustrates a plan view (e.g., top view) of an inductor.

Fig. 4 illustrates an oblique view of the core and guard ring.

Fig. 5 illustrates a plan view (e.g., top view) of a magnetic core, an inductor, and a guard ring.

Fig. 6 illustrates a plan view (e.g., top view) of a magnetic core, an inductor, and a discrete guard ring.

Fig. 7 illustrates a close-up cross-sectional view of a magnetic core inductor with guard rings embedded in a package substrate.

Fig. 8 (which includes fig. 8A-8C) illustrates an exemplary process for providing/fabricating an integrated device package including a magnetic core inductor with guard rings embedded in a package substrate.

Fig. 9 illustrates an exemplary flow diagram of a method for providing/fabricating an integrated device package including a magnetic core inductor with guard rings embedded in a package substrate.

Fig. 10 illustrates a plan view (e.g., top view) of a coupled inductor.

Fig. 11 illustrates a plan view (e.g., top view) of a magnetic core, a coupled inductor, and a guard ring.

Fig. 12 illustrates a plan view (e.g., top view) of a set of magnetic cores, a set of inductors, and a set of guard rings configured to operate as a transformer.

Fig. 13 illustrates an example of a semi-additive patterning (SAP) process.

Fig. 14 illustrates an example of a damascene process.

Fig. 15 illustrates various electronic devices that may integrate the integrated device packages, semiconductor devices, dies, integrated circuits, and/or PCBs described herein.

Detailed Description

In the following description, specific details are given to provide a thorough understanding of various aspects of the disclosure. However, it will be understood by those of ordinary skill in the art that these aspects may be practiced without these specific details. For example, circuits may be shown in block diagrams in order not to obscure the aspects in unnecessary detail. In other instances, well-known circuits, structures and techniques may not be shown in detail in order not to obscure aspects of the disclosure.

The present disclosure describes an integrated device package including a die and a package substrate. The die is coupled to (e.g., mounted on) the package substrate. The package substrate includes at least one dielectric layer (e.g., a core layer, a prepreg layer), a magnetic core in the dielectric layer, a first protective ring, and a first inductor including a plurality of first interconnects. The first inductor is disposed in the package substrate to at least partially surround the magnetic core, wherein at least one interconnect of the plurality of first interconnects is part of a first guard ring. In some implementations, the first guard ring is a discrete guard ring (e.g., a non-contiguous guard ring). In some implementations, the first inductor is a solenoid inductor. In some implementations, the package substrate includes a second plurality of interconnects configured to operate as a second inductor. In some implementations, the first inductor and the second inductor are configured to operate as coupled inductors. In some implementations, the first inductor and the second inductor are configured to operate as a transformer. In some implementations, a magnetic core includes a carrier, a first magnetic layer, and a second magnetic layer.

Exemplary Integrated device Package including magnetic core inductor Embedded in Package substrate

Fig. 2 illustrates an example of an integrated device package including a magnetic core inductor with guard ring(s) embedded in a package substrate. Specifically, fig. 2 illustrates an example of an integrated device package 200 that includes a substrate 202, a die 204, a magnetic core 206, an inductor 208, an encapsulation layer 210, a first guard ring 280, and a second guard ring 282. The integrated device package 200 is mounted on a Printed Circuit Board (PCB) 250. Die 204 may be an Integrated Circuit (IC) that includes several transistors and/or other electronic components. Die 204 may be a logic die and/or a memory die.

The substrate 202 may be a package substrate and/or an interposer. The die 204 is coupled (e.g., mounted) to the substrate 202. More specifically, the die 204 is coupled to the substrate 202 through a first plurality of solder balls 240. In some implementations, the die 204 may be coupled to the substrate 202 differently.

The substrate 202 includes a first dielectric layer 220, a second dielectric layer 222, a first solder resist layer 224, a second solder resist layer 226, and a number of interconnects 227. The first dielectric layer 220 may be a core layer. In some implementations, the first dielectric layer 220 may be a prepreg layer. The second dielectric layer 222 may be one or more dielectric layers (e.g., one or more prepreg layers). The interconnect 227 may include traces, pads, and/or vias formed in the first dielectric layer 220 and/or the second dielectric layer 222. A first solder resist layer 224 is formed on a first surface (e.g., bottom surface, surface facing PCB 250) of substrate 202. A second solder resist layer 226 is formed on a second surface (e.g., a top surface, a surface facing the die 204) of the substrate 202.

As shown in fig. 2, the magnetic core 206 is embedded in the substrate 202. More specifically, the magnetic core 206 is located in a cavity of a first dielectric layer 220 (e.g., a core layer). The cavity of the first dielectric layer 220 is filled with a second dielectric layer 222 (e.g., a prepreg layer). Thus, in the example of fig. 2, the magnetic core 206 is surrounded by the second dielectric layer 222.

The magnetic core 206 includes a carrier 260, a first magnetic layer 262, and a second magnetic layer 264. The first magnetic layer 262 is formed in a first surface (e.g., a bottom surface) of the carrier 260, and the second magnetic layer 264 is formed on a second surface (e.g., a top surface) of the carrier 260. In some implementations, the first magnetic layer 262 and the second magnetic layer 264 are magnetic films. The carrier 260 may be a substrate configured to provide a base for the first magnetic layer 262 and the second magnetic layer 264. In some implementations, the magnetic core 206 may be made entirely of magnetic materials and/or magnetic layers. The magnetic layer 206 is at least partially surrounded by an inductor 208.

Inductor 208 is at least partially embedded in substrate 202. The inductor 208 is formed in the substrate 202 such that the inductor 208 at least partially surrounds the magnetic core 206. In some implementations, the magnetic core 206 helps increase the inductance of the inductor 208 (e.g., by approximately 2 or more times), and helps provide an inductor with a high quality (Q) factor and low resistance. Examples of magnetic cores in inductors are described and illustrated further below in at least fig. 5-6.

In some implementations, the inductor 208 is a solenoid inductor. The inductor 208 includes one or more windings, a first terminal, and a second terminal. The one or more windings and terminals of inductor 208 may be defined by interconnects in substrate 202. In some implementations, the substrate 202 may include more than one inductor (e.g., first inductor, second inductor). The two or more inductors may be configured to operate as coupled inductors or transformers. Examples of more than one inductor in a substrate are further described and illustrated below in at least fig. 10-12.

As shown in fig. 2, the inductor 208 (e.g., a first inductor) includes a first interconnect 230, a second interconnect 231, a third interconnect 232, a fourth interconnect 233, a fifth interconnect 234, a sixth interconnect 235, a seventh interconnect 236, an eighth interconnect 271, a ninth interconnect 272, a tenth interconnect 273, an eleventh interconnect 274, a twelfth interconnect 275, and a thirteenth interconnect 276. In some implementations, the first interconnect 230, the second interconnect 231, the third interconnect 232, the fourth interconnect 233, the fifth interconnect 234, the sixth interconnect 235, the seventh interconnect 236, the eighth interconnect 271, the ninth interconnect 272, the tenth interconnect 273, the eleventh interconnect 274, the twelfth interconnect 275, and the thirteenth interconnect 276 are part of a plurality of first interconnects that define the inductor 208.

An interconnect is an element or component of a device (e.g., an integrated device package, a die) and/or a substrate (e.g., a package substrate, a printed circuit board, an interposer) that may allow or facilitate electrical connection between two points, elements, and/or components. In some implementations, the interconnect can include traces, vias, pads, pillars, redistribution metal layers, and/or Under Bump Metallization (UBM) layers. In some implementations, an interconnect is a conductive material (e.g., metal, copper) that can provide an electrical path for a signal (e.g., data signal, ground signal, power signal). The interconnect may include more than one element/component. A set of interconnects may include one or more interconnects.

Interconnects 230, 236, and 276 may be traces. Interconnects 231, 233, 235, 271, 273, and 275 may be vias. Interconnects 232, 234, 272, and 274 may be pads. In some implementations, the interconnects 230, 236, and 271, 276 may define one or more windings of the inductor 208. The winding of the inductor is further described and explained below in at least fig. 3 and 5-6.

In some implementations, some of the interconnects defining the inductor 208 may also define one or more guard rings (e.g., metal rings) surrounding the cavity in the first dielectric layer 220 (e.g., the core layer). In some implementations, the metal on the first metal layer in the package substrate defines the first guard ring 280. For example, first guard ring 280 may include interconnect 234 and interconnect 274. In some implementations, the metal on the second metal layer in the package substrate defines a second guard ring 282. For example, the second guard ring 282 may include the interconnect 232 and the interconnect 272. As such, in some implementations, the interconnect 232, the interconnect 234, the interconnect 272, and the interconnect 274 may define at least portions of the inductor 208 and at least portions of guard rings (e.g., the first guard ring 280, the second guard ring 282).

The guard ring(s) are used to ensure that a properly sized cavity is formed in the first dielectric layer 220. As described above, the cavity is where the magnetic core 206 is placed. The cavity is then filled with a second dielectric layer 222 (e.g., a prepreg layer). A laser is used to create a cavity in the first dielectric layer 220. Due to the gaussian nature of the laser, a guard ring is formed on the first dielectric layer 220 to ensure accurate cutting or removal of the first dielectric layer 220. Without the free-standing guard ring(s) (which is more laser-resistant than the first dielectric layer 220), unintended portions of the first dielectric layer 220 may be removed, resulting in an oversized cavity and/or a strange shape. A free-standing guard ring is a ring that is not in contact (e.g., does not make electrical contact) with the inductor. However, the presence of the free-standing guard ring(s) may affect the overall performance of the inductor 208. First, the presence of guard ring(s) may provide shielding effects and eddy currents that reduce the overall inductance and Q factor of inductor 208. Second, since the guard ring(s) occupy space that could otherwise be used by a larger core, the guard ring(s) may limit the size of the core 206 located within the windings of the inductor 208. A smaller sized magnetic core 206 will provide a smaller inductive boost than a larger sized magnetic core 206.

To reduce and/or eliminate the above negative effects and properties of the free-standing guard ring(s), the guard ring is integrated onto the inductor 208. That is, some or all of the metal (e.g., interconnect) defining the guard ring(s) are formed such that they are in contact (e.g., physical contact, electrical contact) with the interconnect defining the inductor 208. Thus, some interconnects in the substrate 202 act as both guard rings and inductors. A guard ring integrated into an inductor may be referred to as an integrated inductor guard ring. Such a design reduces, minimizes, and/or eliminates eddy current, shielding effects, which increases inductance and Q factor. In addition, this design provides more space to place the larger magnetic core 206 in the winding of the inductor 208. Examples of guard rings integrated with inductors are further described and illustrated below in at least fig. 5-6.

The encapsulation layer 210 at least partially encapsulates the die 204. The encapsulation layer 210 may include at least one of molding and/or epoxy filling. In some implementations, the encapsulation layer 210 may be a lithographically patternable layer. The lithographically patternable layer/material is a photo-etchable material. That is, the lithographically patternable layer/material is made of a material that is capable of being etched and/or removed (e.g., by a photolithographic process) via exposure of the material to a light source (e.g., Ultraviolet (UV) light) through a mask (e.g., a photomask).

As described above, fig. 2 further illustrates that the integrated device package 200 is coupled (e.g., mounted) on a Printed Circuit Board (PCB)250 by a second plurality of solder balls 252. More specifically, the substrate 202 of the integrated device package 200 is coupled to the PCB 250 by a second plurality of solder balls 252. In some implementations, the integrated device package 200 may be coupled to the PCB 250 differently.

Fig. 3 illustrates a plan view (e.g., top view) of an inductor 300. The inductor 300 may be at least partially embedded in a substrate (e.g., a package substrate). In some implementations, the inductor 300 may correspond to the inductor 208 of fig. 2. The inductor 300 may be a solenoid inductor.

The inductor 300 includes a first interconnect 301, a second interconnect 302, a third interconnect 303, a fourth interconnect 304, a fifth interconnect 305, a sixth interconnect 306, a seventh interconnect 307, an eighth interconnect 308, and a ninth interconnect 309. The first interconnect 301 (e.g., a trace), the third interconnect 303, the fifth interconnect 305, the seventh interconnect 307, and the ninth interconnect 309 are formed on a first metal layer of a substrate (e.g., the substrate 202). For example, the third interconnect 303 may correspond to the interconnect 230 of fig. 2. Second interconnect 302 (e.g., a trace), fourth interconnect 304, sixth interconnect 306, and eighth interconnect 308 are formed in a second metal layer of a substrate (e.g., substrate 202). For example, the second interconnect 302 may correspond to the interconnect 236 of fig. 2.

Inductor 300 further includes a plurality of interconnects 311, a plurality of interconnects 313, a plurality of interconnects 315, a plurality of interconnects 317, a plurality of interconnects 319, a plurality of interconnects 321, a plurality of interconnects 323, a plurality of interconnects 325, a plurality of interconnects 327, and a plurality of interconnects 329. The plurality of interconnects may include one or more interconnects. For example, the plurality of interconnects may include one or more pads and/or one or more vias. In some implementations, the above plurality of interconnects 311, 313, 315, 317, 319, 321, 323, 325, 327, and/or 329 pass vertically through a substrate (e.g., substrate 202). For example, the plurality of interconnects 313 may collectively represent the interconnects 231 and 235 of FIG. 2. In another example, the plurality of interconnects 323 may collectively represent the interconnects 271-275 of fig. 2.

As shown in fig. 3, a plurality of interconnects 311 are coupled (e.g., electrically coupled) to interconnect 301. Interconnect 301 is coupled (e.g., electrically coupled) to a plurality of interconnects 321. A plurality of interconnects 321 is coupled to interconnect 302. Interconnect 302 is coupled to a plurality of interconnects 313. A plurality of interconnects 313 are coupled to interconnect 303. Interconnect 303 is coupled to a plurality of interconnects 323. A plurality of interconnects 323 are coupled to interconnect 304. Interconnect 304 is coupled to a plurality of interconnects 315. A plurality of interconnects 315 are coupled to interconnect 305. Interconnect 305 is coupled to a plurality of interconnects 325. A plurality of interconnects 325 are coupled to interconnect 306. Interconnect 306 is coupled to a plurality of interconnects 317. A plurality of interconnects 317 are coupled to interconnect 307. Interconnect 307 is coupled to a plurality of interconnects 327. A plurality of interconnects 327 are coupled to interconnect 308. Interconnect 308 is coupled to a plurality of interconnects 319. A plurality of interconnects 319 are coupled to interconnect 309. Interconnect 309 is coupled to a plurality of interconnects 329.

Inductor 300 includes one or more windings. Different implementations of inductor 300 may include different numbers of windings. In some implementations, the winding of inductor 300 is defined by a first interconnect 301, a second interconnect 302, a third interconnect 303, a fourth interconnect 304, a fifth interconnect 305, a sixth interconnect 306, a seventh interconnect 307, an eighth interconnect 308, a ninth interconnect 309, a plurality of interconnects 311, a plurality of interconnects 313, a plurality of interconnects 315, a plurality of interconnects 317, a plurality of interconnects 319, a plurality of interconnects 321, a plurality of interconnects 323, a plurality of interconnects 325, a plurality of interconnects 327, and a plurality of interconnects 329. For example, a first winding of inductor 300 may be defined by interconnect 302, plurality of interconnects 313, interconnect 303, and plurality of interconnects 323. However, different implementations may define the winding of inductor 300 differently.

Fig. 3 also illustrates interconnect 330 and interconnect 332. Interconnect 330 may represent a first terminal of inductor 300. Interconnect 330 is coupled to a plurality of interconnects 311. Interconnect 332 may represent a second terminal of inductor 300. Interconnect 332 is coupled to a plurality of interconnects 329. The plurality of interconnects 311 and 329 may be optional. In some implementations, interconnect 330 is directly coupled to interconnect 301. In some implementations, interconnect 332 is directly coupled to interconnect 309.

Fig. 4 illustrates a tilted assembly view of the magnetic core 206, the first guard ring 480, and the second guard ring 482. The magnetic core 206, the first guard ring 480, and the second guard ring 482 are embedded in a substrate (e.g., substrate 202). For clarity, the substrate and dielectric layers (e.g., core layer, prepreg layer) are not shown in fig. 4.

The first guard ring 480 is a metal layer formed on a first surface (e.g., a top surface) of a first dielectric layer (e.g., a core layer) of the substrate. The second guard ring 482 is a metal layer formed on a second surface (e.g., bottom surface) of the first dielectric layer of the substrate. First guard ring 480 and/or second guard ring 482 form a perimeter or periphery of a cavity in the first dielectric layer. As an example, the first guard ring 480 may be defined by a first metal layer in the package substrate (e.g., the interconnects 234 and 274 of fig. 2). The first guard ring 480 may correspond to the first guard ring 280. Similarly, the second guard ring 482 may be defined by a second metal layer in the package substrate (e.g., interconnect 232 and interconnect 272 of fig. 2), as an example. The second guard ring 482 may correspond to the second guard ring 282. Different implementations may have different designs for the guard rings. For example, the guard ring may be annular, rectangular, or any other shape. The guard rings may be located on different layers and/or levels of the package substrate. For example, the first guard ring 480 may be located on a first metal layer of the package substrate and the second guard ring 482 may be located on a second metal layer of the package substrate. Returning to fig. 2, in some implementations, the first metal layer may be on the same metal layer as interconnect 274, and the second metal layer may be on the same metal layer as interconnect 272. In some implementations, the one or more guard rings may be discrete guard rings (e.g., non-contiguous guard rings) defined by several metal layers (e.g., several interconnects). An example of a discrete guard ring is further described in fig. 6.

The magnetic core 206 is located in a cavity of the dielectric layer, which cavity is defined by the first guard ring 480 and/or the second guard ring 482. In some implementations, the magnetic core 206 can be at least partially surrounded by the first protective ring 480 and/or the second protective ring 482.

Fig. 5 illustrates the inductor 300 of fig. 3 integrated with the magnetic core 206 and the first protective ring 408 of fig. 4. The inductor 300, the magnetic core 206, and the first protective ring 480 may be implemented in a substrate (e.g., the substrate 202). However, for clarity, the substrate (including the dielectric layers (e.g., core layer, prepreg layer)) is not shown. As shown in fig. 5, the inductor 300 is integrated with the magnetic core 206 such that the magnetic core 206 is at least partially within the windings of the inductor 300. In addition, the first guard ring 480 is integrated into the winding of the inductor 300 such that the first guard ring 480 becomes part of the winding of the inductor 300 (e.g., contacts the winding of the inductor 300). A second guard ring 482 (which is not shown in fig. 5) may also be integrated in the winding of the inductor 300. The second guard ring 482 is located on a different metal layer of the substrate.

Such a design reduces and/or eliminates eddy currents, improving shielding effects, which increases inductance and Q factor. In addition, this design provides more space to place a larger magnetic core in the windings of inductor 300.

Different implementations may provide cores, guard rings, and inductors having different dimensions. In some implementations, the magnetic core 206 has a size of at least about 760 micrometers (μm) by 770 micrometers (μm). In some implementations, the edge-to-edge distance (e.g., spacing) between the magnetic core 206 and the guard ring 480 is about 50 micrometers (μm) or less. In some implementations, the edge-to-edge distance (e.g., spacing) between the magnetic core 206 and the windings of the capacitor 300 is about 50 micrometers (μm) or less. In some implementations, an edge-to-edge distance (e.g., spacing) between the windings of inductor 300 and guard ring 480 is about 25 micrometers (μm) or less.

Fig. 5 shows one guard ring, but some implementations may include more than one guard ring, as described in fig. 2 and 4. For example, the guard ring 480 may be located on a first layer (e.g., a first metal layer) of the package substrate, and another guard ring (e.g., guard ring 482) may be located on a second layer (e.g., a second metal layer) of the package substrate. In some implementations, the guard ring can be patterned and/or segmented. Thus, the guard ring is a discrete guard ring defined by non-contiguous segments and/or non-contiguous portions, rather than an adjoining ring.

Fig. 6 illustrates an example of a discrete guard ring. In particular, fig. 6 illustrates a discrete guard ring 680 integrated with the magnetic core 206 and the inductor 300. The inductor 300, the magnetic core 206, and the discrete guard ring 680 may be implemented in a substrate (e.g., the substrate 202). However, for clarity, the substrate (including the dielectric layers (e.g., core layer, prepreg layer)) is not shown. The configuration of fig. 6 is similar to the configuration of fig. 5, except that the discrete guard rings 680 are non-contiguous.

Only one discrete guard ring (e.g., a non-contiguous guard ring) is shown, but some implementations may include more than one discrete guard ring. For example, a discrete guard ring 680 may be located on a first layer (e.g., a first metal layer) of the package substrate and another guard ring may be located on a second layer (e.g., a second metal layer) of the package substrate. Additionally, some implementations may use a combination of contiguous and discrete guard rings (e.g., non-contiguous guard rings).

The discrete guard ring 680 includes a number of guard ring portions 680 a-n. Portions of the guard ring 680 may be coupled (e.g., electrically coupled) to portions of the windings of the inductor 300. Thus, portions of the guard ring 680 may be part of the inductor 300. For example, guard ring portion 680e is part of a plurality of interconnects 321. In another example, the guard ring portion 680f can be the interconnect 274 of fig. 2. Thus, some portions of the guard ring 680 may be part of the inductor 300 while other portions of the guard ring 680 are not part of the inductor 300. For example, the guard ring portion 680a does not directly physically contact the inductor 300.

The use of discrete guard rings may provide better eddy current reduction, improved shielding effect, which increases inductance and Q factor, compared to adjoining guard rings. Fig. 6 illustrates merely one example of how a discrete guard ring may be segmented. Different implementations may segment the guard ring differently into different sizes and shapes.

Fig. 6 illustrates one example of a cross-sectional view of an inductor that may be embedded in a substrate. Different implementations may embed the inductor in different designs and/or configurations. Fig. 7 illustrates a close-up view of a substrate 702 including a magnetic core 206, guard rings, and an inductor 708. Substrate 702 is similar to substrate 202 of fig. 2 except that inductor 708 has a different design than inductor 208 of fig. 2. As will be described below, the inductor 708 includes an interconnect formed on a wall of the cavity that includes the magnetic core 206.

As shown in fig. 7, the inductor 708 includes a first interconnect 230, a second interconnect 231, a third interconnect 232, a fourth interconnect 733, a fifth interconnect 234, a sixth interconnect 235, a seventh interconnect 236, an eighth interconnect 271, a ninth interconnect 272, a tenth interconnect 773, an eleventh interconnect 274, a twelfth interconnect 275, and a thirteenth interconnect 276. Thus, in this example, inductor 708 includes different interconnects 733 and 773. Interconnect 733 is coupled to interconnect 232 and interconnect 234. Interconnect 773 is coupled to interconnect 272 and interconnect 274. Interconnect 733 and interconnect 773 are defined within a cavity of first dielectric layer 220. The interconnect 733 and the interconnect 773 are formed on the side of the first dielectric layer 220 (e.g., the core layer). The interconnect 733 and the interconnect 773 are covered with a second dielectric layer 222 (e.g., a prepreg layer). In some implementations, the edge-to-edge distance (e.g., spacing) between the magnetic core 206 and the interconnect 733 is about 50 micrometers (μm) or less. In some implementations, the edge-to-edge distance (e.g., spacing) between the magnetic core 206 and the interconnect 773 is about 50 micrometers (μm) or less.

In some implementations, some of the interconnects defining the inductor 708 also define one or more guard rings (e.g., metal rings) surrounding the cavity in the first dielectric layer 220 (e.g., the core layer). In some implementations, first guard ring 280 is defined by interconnect 234 and interconnect 274. In some implementations, the second guard ring 282 is defined by the interconnect 232 and the interconnect 272. As such, the interconnect 232, the interconnect 234, the interconnect 272, and the interconnect 274 may define at least some portions of the inductor 208 and at least some portions of the guard rings (e.g., the first guard ring 280, the second guard ring 282). The guard rings 280 and/or 282 of fig. 7 may correspond to the guard ring 480 or the guard ring 680.

Exemplary Processes for manufacturing Integrated device packages including magnetic core inductors Embedded in Package substrates

In some implementations, providing/fabricating an integrated device package including a magnetic core inductor with guard rings embedded in a package substrate includes several processes. Fig. 8 (which includes fig. 8A-8C) illustrates an exemplary process for providing/fabricating an integrated device package including a magnetic core inductor with guard rings embedded in a package substrate. In some implementations, the processes of fig. 8A-8C may be used to provide/fabricate the integrated device package 200 of fig. 2 and/or other integrated device packages described in this disclosure.

It should be noted that the process of fig. 8A-8C may combine one or more stages to simplify and/or clarify the process for providing/fabricating an integrated device package including a magnetic core inductor with guard rings embedded in a package substrate. In some implementations, the order of the processes may be changed or modified.

As shown in fig. 8A, stage 1 illustrates the state after providing dielectric layer 800. Dielectric layer 800 may be a core layer. In some implementations, the dielectric layer 800 is provided by a vendor. In some implementations, the dielectric layer 800 is fabricated (e.g., formed).

Stage 2 illustrates the state after the first cavity 801 and the second cavity 803 are formed in the dielectric layer 800. Different implementations may form first cavity 801 and second cavity 803 differently. In some implementations, the cavities may be formed using a laser process.

Stage 3 illustrates the state after forming a first metal layer 802 and a second metal layer 804 on dielectric layer 800. The formation and patterning of the first and second metal layers 802 and 804 may form interconnects 802a, 802b, 804a, 804b, 806a, and 806 b. The interconnects 802a-b may define a first guard ring (e.g., a discrete guard ring) on the first surface of the dielectric layer 800. Interconnects 804a-b may define a second guard ring (e.g., a discrete guard ring) on the second surface of dielectric layer 800. An interconnect 806a (e.g., a via) may couple the interconnect 802a and the interconnect 804 a. An interconnect 806b (e.g., a via) may couple the interconnect 802b and the interconnect 804 b. Interconnects 806a-b may be formed from first metal layer 802, second metal layer 804, or a combination of first metal layer 802 and second metal layer 804. Interconnects 802a-b, 804a-b, and 806a-b may define portions of an inductor. Different implementations may use different processes to form the first metal layer 802 and the second metal layer 804. These metal layers may be patterned using a photolithography process (e.g., a photolithography process). Various examples of photolithography processes are depicted in fig. 13-14. Stage 3 involves patterning the first dielectric layer, including forming an integrated inductor guard ring (e.g., a discrete guard ring). The patterning method may include a modified semi-additive or semi-additive patterning process (SAP).

Stage 4 illustrates the state after a cavity 807 is formed in the dielectric layer 800. In some implementations, a laser is used to form (e.g., remove) portions of the dielectric layer 800. The portions of dielectric layer 800 removed by the laser may be defined within the area of the guard ring(s), as defined by interconnects 802a-b and interconnects 804 a-b.

Stage 5 illustrates the state after coupling the dielectric layer 800 including interconnects 802a-b, 804a-b, 806a, and 806b to the carrier 810.

Stage 6 illustrates the state after placing the magnetic core 206 in the cavity 807 of the dielectric layer 800 (e.g., core layer). The magnetic core 206 may be any of the magnetic cores described in this disclosure. The magnetic core 206 is disposed on a carrier 810.

As shown in fig. 8B, stage 7 illustrates a state after forming a second dielectric layer 814 on the first surface of the dielectric layer 800, the cavity 807, and the magnetic core 206. The second dielectric layer 814 may be a prepreg layer.

Stage 8 illustrates the state after decoupling (e.g., separating) carrier 810 from dielectric layer 800.

Stage 9 illustrates the state after forming a third dielectric layer 816 on the second side of the dielectric layer 800. In some implementations, the third dielectric layer 816 and the second dielectric layer 814 are the same dielectric layer.

Stage 10 illustrates the state after forming a cavity 817 in the second dielectric layer 814 and a cavity 819 in the third dielectric layer 816. The cavity may be formed using a photolithography process. Stage 10 involves via cavity formation and patterning of the second and third dielectric layers. The patterning method may include a modified semi-additive or semi-additive patterning process (SAP).

Stage 11 illustrates a state after forming interconnects 820 (e.g., vias) and 821 (e.g., traces) in/on dielectric layer 814 and interconnects 822 (e.g., vias) and 823 (e.g., traces) in/on dielectric layer 816. Interconnect 820 is coupled to interconnect 821 and interconnect 802 b. Interconnect 822 is coupled to interconnect 823 and interconnect 804 b. Interconnects 823, 822, 804b, 806b, 802b, 820, and 821 may define a portion of an inductor (e.g., a winding).

Stage 12 illustrates the state after forming a first solder resist layer 824 on the dielectric layer 814 and a second solder resist layer 826 on the dielectric layer 816. Stage 12 illustrates a substrate 830 including a dielectric layer 800, a magnetic core 206, a dielectric layer 814, a dielectric layer 816, a number of interconnects (e.g., interconnect 820), a first solder resist 824, and a second solder resist 826. The substrate 830 may be a package substrate.

As shown in fig. 8C, stage 13 illustrates a state after coupling (e.g., mounting) the die 840 to the substrate 830 through the plurality of solder balls 842. The die 840 may be variously coupled to the substrate 830.

Stage 14 illustrates the state after forming an encapsulation layer 850 on the substrate 830 and the die 840. In some implementations, the encapsulation layer 850 is one of molded and/or epoxy filled.

Stage 15 illustrates the state after coupling the plurality of solder balls 860 to the substrate 830. In some implementations, stage 15 illustrates an integrated device package 870 including a substrate 830, a magnetic core 206, an inductor, a guard ring, a die 840, and a package layer 850. In some implementations, the inductor is a solenoid inductor. In some implementations, the integrated device package 870 is similar to the integrated device package 200 of fig. 2.

Exemplary methods for fabricating an integrated device package including a magnetic core inductor embedded in a package substrate

Fig. 9 illustrates an exemplary flow diagram of a method 900 for providing/fabricating an integrated device package including a magnetic core inductor with guard rings embedded in a package substrate. In some implementations, the method of fig. 9 may be used to provide/manufacture the integrated device package of fig. 9 and/or other integrated device packages in the present disclosure.

It should be noted that the flow diagram of fig. 9 may combine one or more processes to simplify and/or clarify the method for providing an integrated device package. In some implementations, the order of the processes may be changed or modified.

The method provides (905) a substrate. In some implementations, the substrate is provided by a vendor. In some implementations, the substrate is fabricated (e.g., formed). The substrate may be a package substrate. The substrate includes a dielectric layer (e.g., a core layer) and a metal layer on the dielectric layer.

The method forms (910) at least one guard ring (e.g., guard rings 480, 482) in/on the substrate. Different implementations may form different guard rings. The guard ring may be a contiguous guard ring or a discrete guard ring (e.g., a non-contiguous guard ring). The guard ring may be formed (e.g., by a photolithographic process) from a metal layer on a dielectric layer of the substrate.

The method forms (915) a cavity in a dielectric layer (e.g., a core layer) of a substrate. The cavity may be formed in a region or portion of the dielectric layer surrounded or defined by the guard ring.

The method places (920) a magnetic core in a cavity of a dielectric layer of a substrate. One example of a magnetic core is the magnetic core 206 depicted in fig. 2. Stage 6 of fig. 8A illustrates an example of placing the magnetic core 206 in the cavity of the substrate.

The method forms (925) an inductor in a substrate such that the inductor (e.g., inductor 300) is formed at least partially around a magnetic core. An inductor is formed in a substrate such that at least portions of a guard ring are integrated into the inductor (e.g., into a winding of the inductor, where the guard ring is in contact with the inductor). The inductor may be a solenoid inductor. Stage 10-12 of fig. 8B illustrates an example of forming an inductor in a substrate.

The method couples (930) a die (e.g., die 204) to a substrate that includes a magnetic core, a guard ring, and an inductor. The die may be coupled to the substrate by a plurality of solder balls. Some implementations may couple the die to the substrate differently. Stage 13 of fig. 8C illustrates an example of a die coupled to a substrate.

The method forms (935) an encapsulation layer (e.g., encapsulation layer 210) over the substrate and die. The encapsulation layer may be molded and/or epoxy filled. Stage 14 of fig. 8C illustrates an example of forming an encapsulation layer on the substrate and the die. Once the package is formed, the method may couple a plurality of solder balls to the substrate. The plurality of solder balls may be used to couple the substrate to a Printed Circuit Board (PCB).

Exemplary Integrated device Package including several magnetic core inductors Embedded in a Package substrate

Fig. 10 illustrates a plan view (e.g., top view) of a coupled inductor 1000. Coupled inductor 1000 includes a first inductor 1001 and a second inductor 1002. Coupled inductor 1000 may be at least partially embedded in a substrate (e.g., a package substrate) in a similar manner as described above in fig. 2. The first inductor 1001 is interleaved with the second inductor 1002. That is, the windings of the first inductor 1001 are interleaved with the windings of the second inductor 1002.

The first inductor 1001 includes a first interconnect 1010, a second interconnect 1011, a third interconnect 1012, a fourth interconnect 1013, a fifth interconnect 1014, and a sixth interconnect 1015. The first interconnect 1010 (e.g., a trace), the third interconnect 1112, and the fifth interconnect 1114 are formed on a first metal layer of a substrate (e.g., the substrate 202). The second interconnect 1011, the fourth interconnect 1013, and the sixth interconnect 1015 are formed in a second metal layer of a substrate (e.g., the substrate 202).

First inductor 1001 further includes a plurality of interconnects 1020, a plurality of interconnects 1021, a plurality of interconnects 1022, a plurality of interconnects 1023, a plurality of interconnects 1024, a plurality of interconnects 1025, and a plurality of interconnects 1026. The plurality of interconnects may include one or more interconnects. For example, the plurality of interconnects may include one or more pads and/or one or more vias. In some implementations, the above plurality of interconnects 1020-1026 pass vertically through a substrate (e.g., substrate 202). For example, plurality of interconnects 1021 may collectively represent interconnects 231 and 235 of FIG. 2.

As shown in fig. 10, a plurality of interconnects 1020 are coupled (e.g., electrically coupled) to interconnect 1010. Interconnect 1010 is coupled (e.g., electrically coupled) to a plurality of interconnects 1021. A plurality of interconnects 1021 is coupled to interconnect 1011. Interconnect 1011 is coupled to a plurality of interconnects 1022. A plurality of interconnects 1022 are coupled to interconnect 1012. Interconnect 1012 is coupled to a plurality of interconnects 1023. A plurality of interconnects 1023 are coupled to interconnect 1013. Interconnect 1013 is coupled to multiple interconnects 1024. A plurality of interconnects 1024 are coupled to interconnect 1014. Interconnect 1014 is coupled to a plurality of interconnects 1025. A plurality of interconnects 1025 are coupled to the interconnect 1015. Interconnect 1015 is coupled to a plurality of interconnects 1026.

The first inductor 1001 includes an interconnect 1003 and an interconnect 1005. Interconnect 1003 may be a first terminal of first inductor 1001. Interconnect 1005 may be the second terminal of first inductor 1001. Interconnect 1003 is coupled to a plurality of interconnects 1020. Interconnect 1005 is coupled to a plurality of interconnects 1026. The multiple interconnects 1020 and 1026 may be optional. In some implementations, interconnect 1003 is directly coupled to interconnect 1010. In some implementations, interconnect 1005 is directly coupled to interconnect 1015.

The second inductor 1002 includes a first interconnect 1051, a second interconnect 1052, a third interconnect 1053, a fourth interconnect 1054, a fifth interconnect 1055, and a sixth interconnect 1056. The first interconnect 1051 (e.g., trace), the third interconnect 1053, and the fifth interconnect 1055 are formed on a second metal layer of a substrate (e.g., substrate 202). The second interconnect 1052, the fourth interconnect 1054, and the sixth interconnect 1056 are formed in a first metal layer of a substrate (e.g., substrate 202).

Second inductor 1002 further includes a plurality of interconnects 1060, a plurality of interconnects 1061, a plurality of interconnects 1062, a plurality of interconnects 1063, a plurality of interconnects 1064, a plurality of interconnects 1065, and a plurality of interconnects 1066. The plurality of interconnects may include one or more interconnects. For example, the plurality of interconnects may include one or more pads and/or one or more vias. In some implementations, the above plurality of interconnects 1060-. For example, the plurality of interconnects 1061 may collectively represent the interconnects 231-235 of FIG. 2.

As shown in fig. 10, a plurality of interconnects 1060 are coupled (e.g., electrically coupled) to interconnect 1051. Interconnect 1051 is coupled (e.g., electrically coupled) to a plurality of interconnects 1061. A plurality of interconnects 1061 are coupled to interconnect 1052. Interconnect 1052 is coupled to a plurality of interconnects 1062. A plurality of interconnects 1062 are coupled to interconnect 1053. Interconnect 1053 is coupled to a plurality of interconnects 1063. A plurality of interconnects 1063 are coupled to interconnect 1054. Interconnect 1054 is coupled to a plurality of interconnects 1064. A plurality of interconnects 1064 are coupled to interconnect 1055. Interconnect 1055 is coupled to a plurality of interconnects 1065. A plurality of interconnects 1065 are coupled to interconnect 1056. Interconnect 1056 is coupled to a plurality of interconnects 1066.

The second inductor 1002 includes an interconnect 1004 and an interconnect 1006. Interconnect 1004 may be a first terminal of second inductor 1002. The interconnect 1006 may be a second terminal of the second inductor 1002. The interconnect 1004 is coupled to a plurality of interconnects 1060. Interconnect 1006 is coupled to a plurality of interconnects 1066. The plurality of interconnects 1060 and 1066 may be optional. In some implementations, interconnect 1004 is directly coupled to interconnect 1051. In some implementations, interconnect 1006 is directly coupled to interconnect 1056.

Fig. 11 illustrates the coupling inductor 1000 of fig. 10 integrated with a core 1106 and a guard ring 1180. Guard ring 1180 is a discrete guard ring. Guard ring 1180 includes a number of guard ring portions 1180 a-p. As described above, the coupled inductor 1000 includes the first inductor 1001 and the second inductor 1002. Coupled inductor 1000, core 1106, and guard ring 1180 may be implemented in a substrate (e.g., substrate 202). However, for clarity, the substrate (including the dielectric layers (e.g., core layer, prepreg layer)) is not shown.

As shown in fig. 11, coupled inductor 1100 is integrated with magnetic core 1106 such that magnetic core 1106 is at least partially within the windings of inductor 1100. Additionally, guard ring 1180 is integrated into the winding of coupled inductor 1100 such that guard ring 1180 becomes part of the winding of coupled inductor 1100 (e.g., contacts the winding of coupled inductor 1100). Portions of guard ring 1180 may be coupled (e.g., electrically coupled) to portions of the windings of coupled inductor 1000. As such, portions of the guard ring 1180 may be part of the first inductor 1001 and/or the second inductor 1002. For example, the guard ring portion 1180d is part of the plurality of interconnects 1061. It should be noted that different implementations may segment the guard ring 1180 differently into different sizes and shapes.

Only one discrete guard ring is shown, but some implementations may include more than one guard ring. For example, the guard ring 1180 (e.g., a discrete guard ring) may be located on a first layer (e.g., a first metal layer) of the package substrate, and another guard ring may be located on a second layer (e.g., a second metal layer) of the package substrate.

Fig. 12 illustrates a plan view (e.g., top view) of two inductors configured to operate as transformers. In particular, fig. 12 illustrates a first inductor 1200, a first magnetic core 1206, a first guard ring 1280, a second inductor 1210, a second magnetic core 1216, and a second guard ring 1290. In some implementations, the first inductor 1200, the first magnetic core 1206, the first guard ring 1280, the second inductor 1210, the second magnetic core 1216, and the second guard ring 1290 are configured to operate as a transformer.

The first inductor 1200, the first core 1206, the first guard ring 1280 may be similar to the inductor 300, the core 206, and the guard ring 480 described above in fig. 3-6, respectively. Similarly, second inductor 1210, second magnetic core 1216, and second guard ring 1290 may be similar to inductor 300, magnetic core 206, and guard ring 480, respectively, described above in fig. 3-6.

The first inductor 1200, the first magnetic core 1206, the first guard ring 1280, the second inductor 1210, the second magnetic core 1216, and the second guard ring 1290 may be implemented in a substrate (e.g., substrate 202) in a similar manner as described above in fig. 2.

Fig. 12 illustrates the cores in their own respective cavities in the substrate. However, in some implementations, one cavity may include two or more magnetic cores. In some implementations, one guard ring can surround two or more magnetic cores. Additionally, in some implementations, one or more of the protection rings may be discrete protection rings (e.g., non-contiguous protection rings).

Fig. 12 illustrates guard rings (e.g., a first guard ring 1280, a second guard ring 1290) on a first metal layer of the package substrate. In some implementations, other guard rings may be located on a different metal layer (e.g., a second metal layer) of the package substrate.

Exemplary semi-additive patterning (SAP) Process

Various interconnects (e.g., traces, vias, pads) are described in this disclosure. These interconnects may be formed in the substrate, the encapsulation layer, and/or the integrated device package. In some implementations, the interconnects may include one or more metal layers. For example, in some implementations, the interconnects may include a first metal seed layer and a second metal layer. Different plating processes may be used to provide (e.g., form) these metal layers. The following are detailed examples of interconnects (e.g., traces, vias, pads) having seed layers and how these interconnects can be formed using different plating processes. The following processes may be used to form, for example, interconnects 230 and 236.

Different implementations may use different processes to form and/or fabricate metal layers (e.g., interconnects, redistribution layers, underbump metallization layers). In some implementations, these processes include a semi-additive patterning (SAP) process and a damascene process. These various processes are described further below.

Fig. 13 illustrates a process for forming interconnects using a semi-additive patterning (SAP) process to provide and/or form interconnects in one or more dielectric layers and/or encapsulation layers. As shown in fig. 13, stage 1 illustrates the state of the integrated device (e.g., substrate) after providing (e.g., forming) the dielectric layer 1302. In some implementations, stage 1 illustrates that the dielectric layer 1302 includes a first metal layer 1304. In some implementations, the first metal layer 1304 is a seed layer. In some implementations, the first metal layer 1304 may be provided (e.g., formed) on the dielectric layer 1302 after the dielectric layer 1302 is provided (e.g., received or formed). Stage 1 illustrates providing (e.g., forming) a first metal layer 1304 on a first surface of a dielectric layer 1302. In some implementations, the first metal layer 1304 is provided by using a deposition process (e.g., PVD, CVD, plating process).

Stage 2 illustrates the state of the integrated device after a photoresist layer 1306 (e.g., a photo-developed resist layer) is selectively provided (e.g., formed) on the first metal layer 1304. In some implementations, selectively providing the photoresist layer 1306 includes providing the photoresist layer 1306 over the first metal layer 1304 and selectively removing portions of the photoresist layer 1306 by developing (e.g., using a developing process). Stage 2 illustrates providing a photoresist layer 1306 such that a cavity 1308 is formed.

Stage 3 illustrates the state of the integrated device after forming a second metal layer 1310 in cavity 1308. In some implementations, a second metal layer 1310 is formed over the exposed portions of the first metal layer 1304. In some implementations, the second metal layer 1310 is provided by using a deposition process (e.g., a plating process).

Stage 4 illustrates the state of the integrated device after the photoresist layer 1306 is removed. Different implementations may use different processes to remove the photoresist layer 1306.

Stage 5 illustrates the state of the integrated device after selectively removing portions of the first metal layer 1304. In some implementations, one or more portions of the first metal layer 1304 not covered by the second metal layer 1310 are removed. As shown in stage 5, the remaining first metal layer 1304 and second metal layer 1310 may form and/or define interconnects 1312 (e.g., traces, vias, pads) in the integrated device and/or the substrate. In some implementations, the first metal layer 1304 is removed such that the dimensions (e.g., length, width) of the first metal layer 1304 below the second metal layer 1310 are substantially the same as or less than the dimensions (e.g., length, width) of the second metal layer 1310, which may result in undercutting, as shown in stage 5 of fig. 13. In some implementations, the above process may be iterated several times to provide and/or form several interconnects in one or more dielectric layers of an integrated device and/or substrate.

Exemplary Damascene Process

Fig. 14 illustrates a process for forming interconnects using a damascene process to provide and/or form interconnects in a dielectric layer and/or an encapsulation layer. As shown in fig. 14, stage 1 illustrates the state of the integrated device after providing (e.g., forming) a dielectric layer 1402. In some implementations, the dielectric layer 1402 is an inorganic layer (e.g., an inorganic film).

Stage 2 illustrates the state of the integrated device after the cavities 1404 are formed in the dielectric layer 1402. Different implementations may use different processes to provide the cavities 1404 in the dielectric layer 1402.

Phase 3 illustrates the state of the integrated device after providing the first metal layer 1406 on the dielectric layer 1402. As shown in stage 3, a first metal layer 1406 is provided on a first surface of the dielectric layer 1402. A first metal layer 1406 is provided on the dielectric layer 1402 such that the first metal layer 1406 occupies the outline of the dielectric layer 1402, including the outline of the cavity 1404. In some implementations, the first metal layer 1406 is a seed layer. In some implementations, the first metal layer 1406 is provided by using a deposition process (e.g., Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), or plating process).

Stage 4 illustrates the state of the integrated device after forming a second metal layer 1408 in the cavity 1404 and on the surface of the dielectric layer 1402. In some implementations, a second metal layer 1408 is formed over the exposed portions of first metal layer 1406. In some implementations, the second metal layer 1408 is provided by using a deposition process (e.g., a plating process).

Stage 5 illustrates the state of the integrated device after removing portions of second metal layer 1408 and portions of first metal layer 1406. Different implementations may use different processes to remove the second metal layer 1408 and the first metal layer 1406. In some implementations, a Chemical Mechanical Polishing (CMP) process is used to remove portions of second metal layer 1408 and portions of first metal layer 1406. As shown in stage 5, the remaining first metal layer 1406 and second metal layer 1408 can form and/or define an interconnect 1412 (e.g., trace, via, pad) in the integrated device and/or substrate. As shown in stage 5, interconnect 1412 is formed in such a way that first metal layer 1406 is formed on the base portion and side portion(s) of second metal layer 1410. In some implementations, the cavity 1404 may include a combination of trenches and/or holes in the two-level dielectric so that vias and interconnects (e.g., metal traces) may be formed in a single deposition process. In some implementations, the above process may be iterated several times to provide and/or form several interconnects in one or more dielectric layers of an integrated device and/or substrate.

Exemplary electronic device

Fig. 15 illustrates various electronic devices that may be integrated with any of the aforementioned integrated devices, semiconductor devices, integrated circuits, dies, interposers, packages, or package on package (pops). For example, the mobile phone device 1502, laptop computer device 1504, and fixed location terminal device 1506 can comprise an integrated device 1500 as described herein. Integrated device 1500 may be, for example, any of the integrated circuits, dies, integrated devices, integrated device packages, integrated circuit devices, device packages, integrated device packages, package-on-package devices described herein. The devices 1502, 1504, 1506 illustrated in fig. 15 are merely exemplary. Other electronic devices may also feature integrated device 1500, such electronic devices including, but not limited to, a population of devices (e.g., electronic devices) including mobile devices, hand-held Personal Communication Systems (PCS) units, portable data units such as personal digital assistants, Global Positioning System (GPS) enabled devices, navigation devices, set top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, communication devices, smart phones, tablet computers, wearable devices, servers, routers, electronic devices implemented in a motor vehicle (e.g., an autonomous vehicle), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

One or more of the components, features, and/or functions illustrated in fig. 2, 3, 4, 5, 6,7, 8A-8C, 9, 10, 11, 12, 13, 14, and/or 15 may be rearranged and/or combined into a single component, feature, or function or implemented in several components or functions. Additional elements, components, and/or functionality may also be added without departing from this disclosure. It should also be noted that fig. 2, 3, 4, 5, 6,7, 8A-8C, 9, 10, 11, 12, 13, 14, and/or 15 and their respective descriptions in this disclosure are not limited to dies and/or ICs. In some implementations, fig. 2, 3, 4, 5, 6,7, 8A-8C, 9, 10, 11, 12, 13, 14, and/or 15 and their respective descriptions may be used to fabricate, create, provide, and/or produce an integrated device. In some implementations, a device may include a die, a die package, an integrated device, an integrated apparatus, an integrated device package, a wafer, a semiconductor device, a package-on-package structure, and/or an interposer.

The word "exemplary" is used herein to mean "serving as an example, instance, or illustration. Any implementation or aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the discussed feature, advantage or mode of operation. The term "coupled" is used herein to refer to a direct or indirect coupling between two objects. For example, if object a physically contacts object B, and object B contacts object C, objects a and C may still be considered to be coupled to each other even though they are not in direct physical contact with each other.

It is also noted that the embodiments may be described as a process which is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe the operations as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations may be rearranged. A process terminates when its operations are completed.

Various features of the present disclosure described herein may be implemented in different systems without departing from the disclosure. It should be noted that the above aspects of the present disclosure are merely examples and should not be construed as limiting the present disclosure. The description of the various aspects of the disclosure is intended to be illustrative, and not to limit the scope of the claims appended hereto. As such, the teachings of the present invention are readily applicable to other types of apparatuses and many alternatives, modifications, and variations will be apparent to those skilled in the art.

Claims (30)

1. An integrated device package comprising:

a die; and

a package substrate coupled to the die, the package substrate comprising:

at least one dielectric layer;

a magnetic core in the at least one dielectric layer;

a first guard ring; and

a first inductor comprising a plurality of first interconnects, the first inductor located in the package substrate to at least partially surround the magnetic core,

wherein the first guard ring includes at least one interconnect of the plurality of first interconnects of the first inductor.

2. The integrated device package of claim 1, wherein the first protective ring comprises a non-contiguous protective ring.

3. The integrated device package of claim 1, wherein the first protective ring comprises a contiguous protective ring.

4. The integrated device package of claim 1, wherein the package substrate further comprises a second guard ring comprising at least one second interconnect of the plurality of first interconnects of the first inductor.

5. The integrated device package of claim 4, wherein the first protective ring is located on a first metal layer of the package substrate and the second protective ring is located on a second metal layer of the package substrate.

6. The integrated device package of claim 4, wherein the first protective ring comprises a first contiguous protective ring or a first non-contiguous protective ring, and the second protective ring comprises a second contiguous protective ring or a second non-contiguous protective ring.

7. The integrated device package of claim 1, wherein the package substrate further comprises a second inductor comprising a plurality of second interconnects.

8. The integrated device package of claim 7, wherein the first inductor and the second inductor are configured to operate as coupled inductors.

9. The integrated device package of claim 7, wherein the first inductor and the second inductor are configured to operate as a transformer.

10. The integrated device package of claim 7, wherein the second inductor is located in the package substrate to at least partially surround the magnetic core, wherein the first protective ring comprises at least one interconnect of the plurality of second interconnects of the second inductor.

11. The integrated device package of claim 1, wherein the at least one interconnect of the plurality of first interconnects that is part of the first guard ring is configured to reduce eddy currents and provide improved shielding for the first inductor.

12. The integrated device package of claim 1, wherein the first inductor comprises a solenoid inductor.

13. The integrated device package of claim 1, wherein the first protective ring at least partially surrounds the magnetic core.

14. The integrated device package of claim 1, wherein a spacing between the magnetic core and the first inductor is about 50 microns (μ ι η) or less.

15. The integrated device package of claim 1, wherein a spacing between the magnetic core and the first protective ring is about 50 microns (μ ι η) or less.

16. The integrated device package of claim 1, wherein the magnetic core comprises a carrier, a first magnetic layer, and a second magnetic layer.

17. The integrated device package of claim 1, wherein the plurality of first interconnects comprise traces, vias, and/or pads.

18. The integrated device package of claim 1, wherein the integrated device package is incorporated into a device selected from the group consisting of: music players, video players, entertainment units, navigation devices, communications devices, mobile phones, smart phones, personal digital assistants, fixed location terminals, tablet computers, wearable devices, laptop computers, servers, and devices in automobiles, and further including the devices.

19. A method for fabricating an integrated device package, comprising:

forming a package substrate, wherein forming the package substrate comprises:

forming at least one dielectric layer;

providing a magnetic core in the at least one dielectric layer;

forming a first metal layer to define a first guard ring in the package substrate; and

forming a plurality of first interconnects to define a first inductor in the package substrate, wherein forming the plurality of first interconnects comprises:

forming the plurality of first interconnects in the package substrate such that the plurality of first interconnects at least partially surround the magnetic core, an

Forming an interconnect of the plurality of first interconnects using at least a portion of the first metal layer to define the first inductor; and

coupling the package substrate to a die.

20. The method of claim 19, wherein forming the first metal layer to define the first protective ring in the package substrate comprises forming the first metal layer to define a non-contiguous protective ring in the package substrate.

21. The method of claim 19, wherein forming the first metal layer to define the first protective ring in the package substrate comprises forming the first metal layer to define a contiguous protective ring in the package substrate.

22. The method of claim 19, wherein forming the package substrate further comprises forming a second metal layer to define a second guard ring in the package substrate such that the second guard ring includes at least one second interconnect in the plurality of first interconnects.

23. The method of claim 22, wherein forming the first metal layer to define the first guard ring comprises forming a plurality of second interconnects, and wherein forming the second metal layer to define the second guard ring comprises forming a plurality of third interconnects.

24. The method of claim 19, wherein forming a package substrate further comprises forming a plurality of second interconnects to define a second inductor in the package substrate, wherein forming the plurality of second interconnects comprises:

forming the plurality of second interconnects in the package substrate such that the plurality of second interconnects at least partially surround the magnetic core; and

forming at least one interconnect of the plurality of second interconnects using at least a second portion of the first metal layer to define the second inductor.

25. The method of claim 19, wherein the first inductor comprises a solenoid inductor.

26. The method of claim 19, wherein forming the at least one dielectric layer comprises:

forming a first dielectric layer, wherein the first dielectric layer is a core layer; and

forming a second dielectric layer.

27. The method of claim 19, wherein a spacing between the magnetic core and the first inductor is about 50 microns (μ ι η) or less.

28. The method of claim 19, wherein a spacing between the magnetic core and the first protective ring is about 50 microns (μ ι η) or less.

29. The method of claim 19, wherein providing the magnetic core in the dielectric layer comprises providing a carrier, a first magnetic layer, and a second magnetic layer.

30. The method of claim 19, wherein the integrated device package is incorporated into a device selected from the group consisting of: music players, video players, entertainment units, navigation devices, communications devices, mobile phones, smart phones, personal digital assistants, fixed location terminals, tablet computers, wearable devices, laptop computers, servers, and devices in automobiles, and further including the devices.