JP2007166238A - Cmos sensor with shutter function per pixel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that a sensor for performing processing using a high-luminance correction signal has difficulty in processing per pixel and a sensor having an initial setting switch has a complicated pixel circuit, because suppression in logarithmic compression of saturation causes deteriorated visibility in a dark part when an object has a very bright part and very dark part. <P>SOLUTION: Each of pixels constituting a CMOS sensor is composed of a photodiode PD1 and transistors Tr1-Tr7. The Tr1s of all the pixels are turned on, thereby simultaneously resetting the PD1s of all the pixels. When the PD1 starts photoelectric conversion immediately after that, Tr4 and Tr5 are turned on based on a logic product of a vertical selection signal VSEL to be generated at a timing corresponding to an incident optical quantity of a corresponding pixel of a previous frame and a horizontal selection signal HSEL, and electric charges stored in the PD1 are transferred to a storage A via the Tr5. An exposure time from a time immediately after reset of the PD 1 to a time of transfer of the electric charges is set to be short when the incident optical quantity of the pixel is large and is set to be long when the optical quantity is small. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a CMOS sensor with a pixel-by-pixel shutter function, and more particularly to a CMOS sensor in which a shutter function is added to each of a plurality of pixels in an imaging unit.

  In the conventional CMOS sensor, the charge accumulation time obtained by photoelectrically converting incident light from a subject with a photodiode of each pixel is constant, but a rolling shutter type in which the shutter timing is slightly shifted, and a shutter for each pixel. A global shutter type whose time cannot be changed is mainly known (for example, see Non-Patent Document 1).

  FIG. 10 shows a configuration diagram of an example of a conventional CMOS sensor. As shown in the figure, the conventional CMOS sensor includes a plurality of pixels 1 arranged in a two-dimensional matrix, and a vertical selection circuit 2 that outputs a vertical selection signal for selecting the plurality of pixels 1 in units of rows. And a horizontal selection circuit 3 for outputting a horizontal selection signal for selecting a plurality of pixels 1 in units of columns and outputting a signal from the selected pixel 1 to the outside of the sensor.

  In addition, as shown in FIG. 11, each pixel 1 is a source that reads out a voltage obtained by photoelectric conversion from reset transistors Tr1 and PD1 for resetting photodiodes PD1 and PD1 that photoelectrically convert incident light from a subject. In many cases, the configuration includes a transistor Tr2 constituting a follower and a transistor Tr3 for selecting and outputting the source output signal of the transistor Tr2 in units of vertical rows to the outside. When the pixel 1 has the circuit configuration shown in FIG. 11, it has a shutter type called a rolling shutter, so that all the photodiodes cannot be reset at one time, and the shutter time (exposure time) is changed for each pixel. I can't.

  Further, in a conventional CMOS sensor, for a very bright subject, an external shutter is adjusted or an aperture is adjusted to suppress a collapse of a picture due to saturation of a photodiode of each pixel. In addition, when a subject has a very bright part and a dark part, if the bright part is not saturated, a phenomenon that the dark part cannot be seen due to the blackout often occurs.

  For this reason, conventionally, an image pickup apparatus that suppresses saturation by logarithmically compressing the sensitivity of a photodiode (see, for example, Patent Document 1), or a picture with a changed exposure time is read twice and used as a high-intensity correction signal. An imaging device that increases the dynamic range is known (for example, see Patent Document 2). Further, the average value of the incident light amount detected by each pixel circuit and the incident light amount detected by the pixel circuit adjacent to the pixel circuit is calculated, and the light receiving sensitivity range is changed based on the average value to change the incident light amount. A solid-state imaging device that can be set to an optimum light receiving sensitivity range according to the amount of incident light by detecting the above is also known in the art (see, for example, Patent Document 3).

Kazuya Yonemoto, “Basics and Applications of CCD / CMOS Image Sensors” CQ Publisher 2003 JP 2000-196961 A JP-A-11-331709 JP 2001-203941 A

  However, the logarithmic compression in the photodiode performed by the conventional imaging device described in Patent Document 1 does not saturate a very bright subject, but all pixels are in a white-out state and are visually recognized in a dark part. There is a problem that the nature is bad. Further, in the conventional imaging device described in Patent Document 2, when a signal is extracted by changing the shutter time, it is difficult to perform processing using a high luminance correction signal for each pixel.

  Furthermore, the conventional imaging device described in Patent Document 3 has an initial setting switch for detecting the saturation of the photodiode for each pixel circuit and resetting the photodiode, so that the pixel circuit becomes complicated, and the small chip size. However, there are problems such as difficulty in increasing the number of pixels.

  The present invention has been made in view of the above points. A shutter function is added for each pixel, the video signal of the previous frame is digitally processed, the saturation state of the photodiode is determined from the signal, and in the next frame. An object of the present invention is to provide a CMOS sensor with a pixel-by-pixel shutter function having a wide dynamic range by changing the exposure time of (i.e., changing the shutter time of the CMOS image sensor).

In order to achieve the above object, according to a first aspect of the present invention, there is provided a CMOS sensor in which a plurality of pixels are regularly arranged in an imaging unit.
One of the drain terminal and the source terminal is connected to the photoelectric conversion element and the first reset signal is applied to the gate terminal to reset the photoelectric conversion element that photoelectrically converts incident light and accumulates charges. And a first transistor for signal amplification, wherein one of a drain terminal and a source terminal is connected to a power supply terminal, and a pixel signal corresponding to the charge applied to the gate terminal is output from the other of the drain terminal and the source terminal. 2 and the pixel signal output from the second transistor when selected by the selection signal applied to each pixel through the selection signal line to the gate terminal, the output signal line from one of the source terminal and the drain terminal One of a source terminal and a drain terminal at a connection point between the third transistor for selection to be output to and the photoelectric conversion element and the first transistor The connected fourth transistor for charge transfer and the gate terminal are connected to the first signal line, one of the drain terminal and the source terminal is connected to the gate terminal of the fourth transistor, and the other terminal is the first terminal. A fifth transistor connected to the second signal line for controlling the gate potential of the fourth transistor, a gate terminal connected to the third signal line, and one of the drain terminal and the source terminal connected to the fourth transistor A sixth transistor for transfer connected to the other of the source terminal and the drain terminal, the other terminal connected to the gate terminal of the second transistor, and one of the drain terminal and the source terminal connected to the second transistor and the second transistor 6 is connected to the connection point with the transistor 6, the other terminal is connected to the power supply terminal, and the second reset signal is applied to the gate terminal. It is more configuration and seventh transistor,
A reset unit that simultaneously applies the first reset signal to the gate terminals of the first transistors of all the pixels to simultaneously reset the photoelectric conversion elements of all the pixels, and a charge generated by photoelectric conversion of the photoelectric conversion elements after the reset by the reset unit During the accumulation operation, the fourth and fifth transistors of the pixel selected by the logical product of the signals of the first and second signal lines are turned on, and the charge of the photoelectric conversion element is passed through the fourth transistor. First transfer means for transferring to the connection point of the fourth and sixth transistors, and after the charge transfer by the first transfer means, the sixth transistor is turned on by the signal of the third signal line, The charge accumulated at the connection point of the fourth and sixth transistors is transferred to the storage part at the common connection point of the sixth and seventh transistors, and all pixel readings are transferred to the storage part. During this period, the second transfer means for holding the charge and the timing positions at which the fourth and fifth transistors are turned on by the first transfer means are determined according to the amount of light incident on the photoelectric conversion element of the pixel. And a pixel-specific exposure time variable unit that varies the exposure time from the start of charge accumulation after resetting the photoelectric conversion element to the time of charge transfer by the first transfer unit.

  In this invention, the timing position at which the fourth and fifth transistors are turned on by the first transfer means is changed according to the amount of light incident on the photoelectric conversion element of the pixel, thereby resetting the photoelectric conversion element. The exposure time from the subsequent charge accumulation start time to the charge transfer time by the first transfer means can be varied.

In order to achieve the above object, according to a second aspect of the present invention, there is provided a CMOS sensor in which a plurality of pixels are regularly arranged in an imaging unit.
A photoelectric conversion element that photoelectrically converts incident light to accumulate charges, a first transistor in which one of a drain terminal and a source terminal is connected to the photoelectric conversion element, and a drain terminal and a source in order to reset the photoelectric conversion element One of the terminals is connected to the power supply terminal, a second transistor for signal amplification that outputs a pixel signal corresponding to the charge applied to the gate terminal from the other of the drain terminal and the source terminal, and a selection signal line to the gate terminal A third transistor for selection that outputs a pixel signal output from the second transistor to the output signal line from one of the source terminal and the drain terminal when selected by a selection signal applied to each pixel via The gate terminal is connected to the first signal line, one of the drain terminal and the source terminal is connected to the gate terminal of the first transistor, and the other A fourth transistor whose terminal is connected to the second signal line and controls the gate potential of the first transistor, a gate terminal is connected to the third signal line, and one of the drain terminal and the source terminal is the first transistor A fifth transistor for transfer in which the other terminal is connected to the gate terminal of the second transistor and one of the drain terminal and the source terminal is connected to the connection point between the transistor and the photoelectric conversion element. A sixth transistor for reset connected to a connection point between the transistor and the fifth transistor, the other terminal connected to the power supply terminal, and a reset signal applied to the gate terminal;
The first and fourth transistors of the pixel selected by the logical product of the signals of the first and second signal lines are turned on, the photoelectric conversion element is reset once, and then the first and second signal lines again. Each of the first and fourth transistors of the pixel selected by the logical product of the above signals is turned on to reset the photoelectric conversion element for the second time, and after the second reset by the reset means, 5 transistors are turned on by the signal of the third signal line, and the charges accumulated in the photoelectric conversion elements are accumulated in the accumulation portion at the common connection point of the second, fifth and sixth transistors all at once. The charge transfer means for transferring and holding the charge in the storage section, and the second reset time position of the photoelectric conversion element by the reset means in accordance with the amount of incident light on the photoelectric conversion element of the pixel As described above, by generating and outputting signals to be sent to the first and second signal lines, the time from the start of charge accumulation after the second reset of the photoelectric conversion element to the time of charge transfer by the charge transfer means And a pixel-specific exposure time variable means for varying the exposure time.

  In the present invention, signals to be sent to the first and second signal lines are set so that the reset time position of the photoelectric conversion element for the second time by the reset means is set according to the amount of light incident on the photoelectric conversion element of the pixel. By generating and outputting, the exposure time from the charge accumulation start time after the second reset of the photoelectric conversion element performed for each pixel to the charge transfer time performed simultaneously for all the pixels by the charge transfer means according to the incident light amount Variable.

  Here, the pixel-specific exposure time variable means compares the signal level for each pixel with a plurality of threshold values, determines the incident light amount of the pixel, calculates the exposure time for each pixel, and calculates the calculation result. An arithmetic means that holds as a set value, a horizontal selection signal that is output to one of the first and second signal lines for each pixel, and a vertical selection signal that is output to the other, based on the setting value calculated and held by the arithmetic means And a horizontal / vertical selection signal generating means for generating.

  According to the present invention, the following effects can be obtained.

  (1) Since the exposure time for each pixel can be varied according to the amount of incident light, saturation of the photoelectric conversion element can be suppressed for any subject, visibility in dark areas can be improved, and a wide dynamic range can be realized. .

  (2) Since the exposure time is determined based on the video signal level of the previous frame, it is possible to generate a screen with uniform brightness from a bright place to a dark place on the subject.

  Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a block diagram of an embodiment of a CMOS sensor with a pixel-by-pixel shutter function according to the present invention. As shown in the figure, the present embodiment includes a plurality of pixels 5 arranged in a two-dimensional matrix, a vertical shutter selection circuit 6 for changing the shutter time of the plurality of pixels 5 in the vertical direction for each pixel, Based on the output signal of the vertical shutter selection circuit 6, a vertical selection circuit 7 that outputs a vertical selection signal for selecting a plurality of pixels 5 in units of rows, and a known correlation with the signal read from the pixels 5 A CDS circuit 8 that performs double sampling (CDS) processing to suppress fixed pattern noise, and a horizontal selection circuit 9 that outputs a horizontal selection signal for selecting a plurality of pixels 5 for each column. And a horizontal shutter selection circuit 10 for changing the shutter time of the plurality of pixels 5 in the horizontal direction for each pixel.

  The pixel 5, the vertical selection circuit 7, the horizontal selection circuit 9, and the CDS circuit 8 of the present embodiment have the same functions as the conventional one, but the pixel 5 is different from the conventional pixel 1 shown in FIG. Since the time can be changed for each pixel, the number of elements and the circuit configuration are different as will be described later. In addition, a vertical shutter selection circuit 6 and a horizontal shutter selection circuit 10 are newly added to control the pixel 5.

  The present embodiment is characterized in that the shutter time is changed according to the amount of incident light for each pixel by using the vertical shutter selection circuit 6 and the horizontal shutter selection circuit 10. This shutter time corresponds to the exposure period of the photodiode of each pixel 5, and when the incident light quantity is so large that the saturation level is reached, the exposure period is made shorter than the standard value to saturate the photodiode in the pixel. In addition, when the amount of incident light is very small, by setting the exposure period longer than the standard value, a wide dynamic range can be realized in any subject. In this embodiment, since the exposure time is determined based on the video signal level of the previous frame, it is possible to generate a screen with uniform brightness from a bright place to a dark place.

  Next, a more specific example 1 of the embodiment of the present invention will be described with reference to FIGS. FIG. 2 is a circuit diagram of one pixel of the first embodiment of the CMOS sensor with a pixel-by-pixel shutter function according to the present invention, and FIG. 3 is a block diagram of the first embodiment of the CMOS sensor with a pixel-by-pixel shutter function according to the present invention. 2, the same components as those in FIG. 11 are denoted by the same reference numerals.

  In FIG. 2, a pixel 5 includes a photodiode PD1 that photoelectrically converts incident light from a subject, a transistor Tr1 that resets the photodiode PD1, a transistor Tr2 that constitutes a read source follower, and a plurality of pixels. In addition to the transistor Tr3 for selecting a unit, transistors constituting a circuit for controlling the voltage applied to the gate of the transistor Tr5 and the storage transistor A due to the parasitic capacitance thereafter, the transfer transistors Tr5 and Tr6 Tr4, a signal line HSEL connected to the gate of the transistor Tr4, a signal line VSEL connected to the drain of the Tr4, and a reset transistor Tr7 are added. Here, all the transistors Tr1 to Tr7 are N-channel MOS field effect transistors (FETs).

  The anode of the photodiode PD1 is grounded, and the source of the reset transistor Tr1 and the drain of the transfer transistor Tr5 are connected to the cathode. The source of the transistor Tr5 is connected to the source of the transfer transistor Tr6 via the storage section A, and the drain of the Tr6 is connected to the gate of the transistor Tr2 constituting the source follower for read amplification and the drain of the reset transistor Tr7, respectively. Has been. The parasitic capacitance at the common connection point of these transistors Tr6, Tr7, Tr2 constitutes the storage part B.

  The source of the transistor Tr2 is connected to the drain of the transistor Tr3, and the output signal Sout is output from the source of Tr3 to the outside. The power supply voltage Vdd is applied to the drains of the transistors Tr1 and Tr2 and the source of Tr7, and the gate of the transistor Tr6 is connected to the signal line TG2.

  The signal lines HSEL, VSEL, TG2, etc. are connected to predetermined circuit portions of the CMOS sensor of the first embodiment shown in FIG. That is, in FIG. 3, the pixel 5a corresponds to the pixel 5 in FIG. 1, and the vertical selection shift register and the gate 11 correspond to the vertical selection circuit 7 in FIG. 1, from which the signal TG2, RST and ROWS1 are output respectively. Further, the shutter VSEL decoder 12 in FIG. 3 corresponds to the vertical shutter selection circuit 6 in FIG.

  In FIG. 3, the shutter HSEL decoder 13 corresponds to the horizontal shutter selection circuit 10 of FIG. 1, and the signal line HSEL is connected to the pixel 5a for each column. Further, the horizontal selection shift register and the gate 14 in FIG. 3 correspond to the horizontal selection circuit 9 in FIG. The shutter HSEL decoder 13 and the horizontal selection shift register and gate 14 are signals indicating the reset position (where the value decoded from the set value input from the outside matches the value shifted from the shift register). The operation to output is performed. Further, the CDS circuit 8 operates for each column by the signals output from the horizontal selection shift register and the gate 14. Further, the read signal Sout from each pixel 5 a is input to the CDS circuit 8. The signal PDRST1 is supplied to all the pixels 5a simultaneously.

  Next, the operation of the pixel 5 having the configuration shown in FIG. 2 (pixel 5a shown in FIG. 3) will be described with reference to the timing chart shown in FIG. First, when the signal PDRST1 shown in FIG. 4A applied to the gates of the transistors Tr1 of all the pixels 5 becomes high level at time t1, the transistor Tr1 is turned on, and the cathode potential of the photodiode PD1 is fixed. The reset operation to set the voltage V1 is performed for all the pixels at the same time. Here, the fixed voltage V1 at the time of reset is expressed by the following equation.

V1 = Vdd−Von_tr1 (1)
Vdd: drain voltage of Tr1
Von_tr1: On-voltage of Tr1 Next, when the signal PDRST1 becomes low level at time t2, the transistor Tr1 is turned off, and accumulation of charges obtained by photoelectrically converting incident light by the photodiode PD1 starts. The cathode potential changes from V1 to V2. Here, even if the potential of the signal line HSEL connected to one pixel 5 becomes high level at time t3 as shown in FIG. 4C, the signal line as shown in FIG. Since the potential of VSEL is at a low level, the transistor Tr5 is not turned on at this time.

  After that, the potential of the signal line VSEL connected to a certain pixel 5 becomes high level at time t4 as shown in FIG. 4B, and in this state, the signal line VSEL is connected to the one pixel at time t5. When the potential of the signal line HSEL is again set to the high level, the transistors Tr4 and Tr5 in FIG. 2 are turned on, and the charge at the cathode potential V2 of the photodiode PD1 at that time is the drain and source of the transistor Tr5. And the potential of the storage part A due to the parasitic capacitance at the connection part of the transistors Tr5 and Tr6 becomes V3 due to the transferred charge.

  The timing at which this charge is transferred determines the shutter time. Here, the shutter time of the pixel 5, that is, the exposure time T1 is expressed by the following equation.

T1 = t5-t2 (2)
The gate voltage of the transistor Tr5 that controls this transfer is generated from the transistor Tr4 and the signal lines VSEL and HSEL.

  Subsequently, in order to make the exposure time (shutter time) independent of the readout time, after turning off the transistor Tr5, the signal TG2 applied to the gate of the transistor Tr6 is set to high level, and the transistor Tr6 is turned on. Thus, the charge at the voltage V3 stored in the storage part A is transferred to the storage part B through the source and drain of the transistor Tr6, and the charge is held in the storage part B until all pixels are read out.

  The signal readout of all pixels is the same as that of the conventional CMOS sensor, and the signal accumulated in the accumulation unit B is further read out by the pixel 5 via the gate and source of the transistor Tr2 constituting the source follower. The signal is output as an output signal Sout through the drain and source of the switching transistor Tr3 which is turned on by the signal ROWS1 which is sometimes at a high level. Further, after the signal Sout is read, the reset transistor Tr7 is turned on by a reset signal RST applied to the gate thereof, thereby resetting the charge accumulated in the accumulation unit B.

  Here, the present embodiment is characterized in that the exposure time (shutter time) T1 is variably controlled for each pixel in accordance with the amount of incident light. Therefore, the signal line VSEL is connected to the shutter VSEL decoder 12 in FIG. The timing of the output signal and the timing of the signal output to the signal line HSEL with respect to the shutter HSEL decoder 13 are variably controlled according to the amount of incident light.

  FIG. 5 is a configuration diagram for controlling the shutter time of the CMOS sensor by an external circuit. In the figure, a CMOS sensor 21 is the CMOS sensor of the first embodiment, and a video signal output as an output signal of the CMOS sensor 21 from the CDS circuit 8 of FIG. 3 is quantized by an AD converter (ADC) 22, for example. After being converted into a digital signal of 12 bits, the signal is supplied to the frame memory / digital signal processing circuit 23, subjected to predetermined signal processing, and then supplied to the pixel-specific shutter time calculation / setting value holding circuit 24. The

  The pixel-by-pixel shutter time calculation / setting value holding circuit 24 has a central processing unit (CPU), and compares the input digital video signal with, for example, a signal level for each pixel and a plurality of threshold values. The incident light quantity of the pixel is determined, the shutter time (exposure time) is calculated for each pixel, and the calculation result is held as a set value.

  The parallel data output interface 25 converts each pixel into data to be output to the signal lines VSEL and HSEL based on the pixel-specific setting value input from the pixel-by-pixel shutter time calculation / setting value holding circuit 24, and The 8-bit parallel data is set in the shutter VSEL decoder 12 and the shutter HSEL decoder 13 shown in FIG. The calculation of the shutter time and the data setting described above need to be performed at high speed and processed within the vertical blank period.

  As a result, when the incident light quantity is very large such that it reaches the saturation level or saturation level of the photodiode output, the shutter time (exposure time) in the next exposure is shortened, the signal level is very low, and the incident light quantity is low. When it is very small, the shutter time (exposure time) in the next exposure is lengthened. However, if the shutter time (exposure time) is significantly changed, the original subject image may be changed. Therefore, it is necessary to change the shutter time to such an extent that it can be practically used. In order to vary the shutter time (exposure time), the transfer timing of the accumulated charge of the pixel is varied.

  FIG. 6 shows a configuration diagram of a control circuit for controlling the shutter time of the CMOS sensor by an internal circuit in the CMOS sensor. As shown in the figure, this control circuit is provided in each of the shutter VSEL decoder 12 and the shutter HSEL decoder 13 shown in FIG. In FIG. 6, the parallel input / shift register / latch unit 27 includes a 4- to 8-bit parallel HSEL selection setting value (in the case of the shutter HSEL decoder 13) or a VSEL selection setting value (shutter use) input from the outside. (In the case of the VSEL decoder 12), it is latched while shifting.

  The decoder 28 compares the HSEL selection setting value of each line input from the parallel input / shift register / latch unit 27 with the horizontal selection address input from the internal circuit (shutter HSEL decoder). 13) or whether the VSEL selection setting value of each line matches the vertical selection address input from the internal circuit (in the case of the shutter VSEL decoder 12), and the decoding is performed when both match. Then, the HSEL signal and VSEL signal of each line are generated and output to the signal lines HSEL and VSEL.

  According to the first embodiment, since the shutter time is determined by digital processing, the relationship between the level of the optical signal and the saturation can be freely determined. Further, since the saturation level can be detected after noise suppression by the CDS circuit 8, saturation suppression can be performed on the actual output signal.

  Next, a more specific example 2 of the embodiment of the present invention will be described with reference to FIGS. FIG. 7 is a circuit diagram of one pixel of the first embodiment of the CMOS sensor with a pixel-by-pixel shutter function according to the present invention, and FIG. 8 is a block diagram of the first embodiment of the CMOS sensor with a pixel-by-pixel shutter function according to the present invention. In FIG. 7, the same components as those in FIGS. 2 and 11 are denoted by the same reference numerals.

  In FIG. 7, a pixel 5 includes a photodiode PD1 that photoelectrically converts incident light from a subject, a transistor Tr1 that resets the photodiode PD1, a transistor Tr2 that constitutes a read source follower, and a plurality of pixels. In addition to the transistor Tr3 for selecting in units, the transfer transistor Tr6, the subsequent storage unit C due to parasitic capacitance, the transistor Tr8, the signal line HSEL connected to the gate of the transistor Tr8, and the drain of the Tr8 And a reset transistor Tr7 are added. Here, all the transistors Tr1 to Tr3 and Tr6 to Tr8 are N-channel MOS field effect transistors (FETs).

  The source of the reset transistor Tr1 and the source of the transfer transistor Tr6 are connected to the cathode of the photodiode PD1. The drain of the transistor Tr6 is connected to the gate of the transistor Tr2 constituting the source follower for reading and the drain of the reset transistor Tr7. The parasitic capacitance at the common connection point of these transistors Tr6, Tr7, Tr2 constitutes the storage section C. The source of the transistor Tr8 is connected to the gate of the transistor Tr1.

  The source of the transistor Tr2 is connected to the drain of the transistor Tr3, and the output signal Sout is output from the source of Tr3 to the outside. A power supply voltage Vdd is applied to the drains of the transistors Tr1 and Tr2 and the source of Tr7, and the gate of the transistor Tr6 is connected to the signal line TG.

  The signal lines HSEL, VSEL, TG, etc. are connected to predetermined circuit portions of the CMOS sensor of the second embodiment shown in FIG. 8, the pixel 5b corresponds to the pixel 5 in FIG. 1, and the vertical selection shift register and the gate 15 correspond to the vertical shutter selection circuit 6 in FIG. 1. From this, the signal TG is sent to the pixel 5b for each row. , RST, and ROWS1 are output. The shutter VSEL decoder 16 in FIG. 8 corresponds to the vertical selection circuit 7 in FIG. 1 and is connected to the pixels 5b for each row by a signal line VSEL.

  In FIG. 8, the shutter HSEL decoder 17 corresponds to the horizontal selection circuit 9 of FIG. 1, and the signal line HSEL is connected to the pixel 5b for each column. Further, the horizontal selection shift register and the gate 18 in FIG. 8 correspond to the horizontal shutter selection circuit 10 in FIG. The shutter HSEL decoder 17 and the horizontal selection shift register and gate 18 are signals indicating the reset position (where the value decoded from the set value input from the outside matches the value shifted by the shift register). The operation to output is performed. Further, the CDS circuit 8 is operated for each column by a signal output from the horizontal selection shift register and the gate 18. Further, the read signal Sout from each pixel 5 b is input to the CDS circuit 8.

  Next, the operation of the pixel 5 having the configuration shown in FIG. 7 (pixel 5b shown in FIG. 8) will be described with reference to the timing chart shown in FIG. First, when the signal on the signal line VSEL shown in FIG. 9A becomes high level at time t11 and the signal on the signal line HSEL shown in FIG. 9B becomes high level, the transistor Tr8 is turned on. As a result, the transistor Tr1 is also turned on, and the power supply voltage Vdd is applied to the cathode of the photodiode PD1 through the transistor Tr1 to be reset. The fixed voltage V4 at the time of reset is expressed by the following equation.

V4 = HSEL−Vt_tr8−Vt_tr1 (3)
HSEL: Tr8 gate voltage of the signal line HSEL
Vt_tr1: threshold voltage of Tr1
Vt_tr8: Threshold voltage of Tr8 Thereafter, charges due to photoelectric conversion of incident light are accumulated by the photodiode PD1, and the cathode potential of PD1 falls from V4. At time t12, the signal on the signal line VSEL shown in FIG. 9A again becomes a high level, and one row including the pixel 5 (5b) is selected, and the transistor Tr8 of the pixel 5 (5b) is selected. When the signal of the signal line HSEL applied to the gate becomes high level and this pixel 5 (5b) is selected, the transistors Tr8 and Tr1 are turned on, and the charge accumulated in the photodiode PD1 until just before that point is turned on. Is discarded and the second reset is performed on PD1. The reset potential at this time is V4 expressed by the above equation (3).

  As shown in FIG. 9C at time t13 immediately after the reset, when the signal on the signal line HSEL changes from the high level to the low level, the transistors Tr8 and Tr1 are turned off, and the photodiode PD1 transmits the incident light. Charges due to photoelectric conversion are accumulated again, and the potential of the cathode of PD1 falls from V4 toward V5. Then, as shown in FIG. 9D, when the signal on the signal line TG applied to the gate of the transistor Tr6 becomes high level at time t14, the transistor Tr6 is turned on, and is stored in the photodiode PD1 at that time. The charge generated by the photoelectric conversion is transferred to the storage portion C via the source and drain of the transistor Tr6. Note that the charge transfer of PD1 performed at time t14 is performed all at once.

  The timing at which the charges are transferred determines the shutter time. Here, the shutter time of the pixel 5, that is, the exposure time T2 is expressed by the following equation.

T2 = t14-t13 (4)
In the second embodiment, the transfer timing is the same for all the pixels, and the photodiode PD1 is reset for each pixel in order to control the exposure time T2. The gate voltage of the transistor Tr1 that controls this reset is generated from the signals of the transistor Tr8 and the signal lines VSEL and HSEL.

  After the charge is transferred to the storage unit C, it is held until all pixels are read. The pixel signal readout is the same as in the conventional CMOS sensor, and the signal accumulated in the accumulation unit C is output from the sensor as an output signal Sout through the transistor Tr2 constituting the source follower and the switching transistor Tr3 selected for each column. Is output. Further, after the signal is read, the charge accumulated in the accumulating portion C is reset by the resetting transistor Tr7. RST in FIG. 7 is a signal for turning on the reset transistor Tr7.

  Thus, according to the present embodiment, the first reset of the photodiode PD1 is performed by the logical product of the signals of the signal lines VSEL and HSEL. Next, the second reset of the photodiode PD1 is performed by the logical product of the signals of the signal lines VSEL and HSEL, and the accumulation of the charge of the photodiode PD1 actually transferred from there is started. Thereafter, the transfer transistors Tr6 in all the pixels are turned on at the same timing by the signal of the signal line TG, the charges accumulated in the PD1 are transferred to the accumulation unit C, and the exposure ends.

  The time T2 from the second reset time point to the transfer time point expressed by the equation (4) is the exposure time. This is the shutter time. This time T2 is varied for each pixel and according to the brightness of the subject, and is controlled so as not to be saturated by the photodiode PD1. Thereby, according to the present embodiment, a global shutter type CMOS sensor with a wide dynamic range can be realized, and can be applied to, for example, a security-related monitoring camera.

  In the case of this embodiment, as in the first embodiment, when the control circuit for controlling the shutter time of the CMOS sensor is an external circuit, the configuration shown in the block diagram of FIG. 6 is a configuration shown in the block diagram. Further, according to the second embodiment, since the shutter time is determined by digital processing, the relationship between the optical signal level and the saturation can be freely determined. Further, since the saturation level can be detected after noise suppression by the CDS circuit 8, saturation suppression can be performed on the actual output signal.

  Note that the present invention is not limited to the above-described embodiments and examples. For example, the drains and sources of the transistors Tr1 to Tr8 may be connected in reverse to the examples. Tr8 may be configured by a P-channel MOS field effect transistor by reversing the positive and negative (magnitude relationship) between the power source and the embodiment.

It is a block diagram of one embodiment of a CMOS sensor with a shutter function for each pixel of the present invention. It is a circuit diagram of one pixel of Example 1 of the CMOS sensor with a shutter function for each pixel of the present invention. It is a block diagram of Example 1 of the CMOS sensor with a shutter function for each pixel of the present invention. 3 is a timing chart for explaining the operation of FIG. 2. It is a block diagram of an example of the external control circuit which controls the shutter time of the CMOS sensor of this invention. It is a block diagram of an example of the control circuit inside a sensor which controls the shutter time of the CMOS sensor of this invention. It is a circuit diagram of one pixel of Example 2 of the CMOS sensor with a shutter function for each pixel of the present invention. It is a block diagram of Example 2 of the CMOS sensor with a shutter function for each pixel of the present invention. 8 is a timing chart for explaining the operation of FIG. It is a block diagram of an example of the conventional CMOS sensor. It is a circuit diagram of an example of one pixel of FIG.

Explanation of symbols

5, 5a, 5b Pixel 6 Vertical shutter selection circuit
7 Vertical selection circuit 8 CDS circuit 9 Horizontal selection circuit 10 Horizontal shutter selection circuit 11, 15 Vertical selection shift register and gate 12, 16 Shutter VSEL decoder 13, 17 Shutter HSEL decoder 14, 18 Horizontal selection shift register and gate 21 CMOS sensor 22 AD converter (ADC) of the present invention
23 Frame Memory / Digital Signal Processing Circuit 24 Pixel-Specific Shutter Time Calculation / Set Value Holding Circuit 25 Parallel Data Output / Interface 27 Parallel Input / Shift Register / Latch Unit 28 Decoder

Claims (3)

In a CMOS sensor in which a plurality of pixels are regularly arranged in the imaging unit,
Each of the pixels
A photoelectric conversion element that photoelectrically converts incident light and accumulates charges;
In order to reset the photoelectric conversion element, a first transistor in which one of a drain terminal and a source terminal is connected to the photoelectric conversion element, and a first reset signal is applied to a gate terminal;
A second transistor for signal amplification in which one of the drain terminal and the source terminal is connected to the power supply terminal, and a pixel signal corresponding to the charge applied to the gate terminal is output from the other of the drain terminal and the source terminal;
A selection of outputting a pixel signal output from the second transistor from one of the source terminal and the drain terminal to the output signal line when selected by a selection signal applied to each pixel via the selection signal line to the gate terminal. A third transistor for
A fourth transistor for charge transfer in which one of a source terminal and a drain terminal is connected to a connection point between the photoelectric conversion element and the first transistor;
The gate terminal is connected to the first signal line, one of the drain terminal and the source terminal is connected to the gate terminal of the fourth transistor, and the other terminal is connected to the second signal line. A fifth transistor for controlling the gate potential of the transistor;
The gate terminal is connected to the third signal line, one of the drain terminal and the source terminal is connected to the other of the source terminal and the drain terminal of the fourth transistor, and the other terminal is the gate terminal of the second transistor. A sixth transistor for transfer connected to
One of a drain terminal and a source terminal is connected to a connection point between the second transistor and the sixth transistor, the other terminal is connected to a power supply terminal, and a second reset signal is applied to the gate terminal. A seventh transistor for resetting,
Reset means for simultaneously applying the first reset signal to the gate terminals of the first transistors of all pixels to simultaneously reset the photoelectric conversion elements of all pixels;
During the charge accumulation operation by photoelectric conversion of the photoelectric conversion element after reset by the reset means, the fourth and fifth transistors of the pixel selected by the logical product of the signals of the first and second signal lines are respectively set. A first transfer means for turning on and transferring the charge of the photoelectric conversion element to the connection point of the fourth and sixth transistors via the fourth transistor;
After the charge transfer by the first transfer means, the sixth transistor is turned on by the signal of the third signal line, and in the storage portion at the common connection point of the second, sixth, and seventh transistors, A second transfer means for transferring the charge accumulated at the connection point of the fourth and sixth transistors and holding the charge in the accumulation portion for the entire pixel readout period;
The photoelectric conversion element is reset by changing the timing positions at which the fourth and fifth transistors are turned on by the first transfer unit according to the amount of light incident on the photoelectric conversion element of the pixel. A CMOS sensor with a pixel-by-pixel shutter function, comprising: a pixel-by-pixel exposure time varying unit that varies an exposure time from a subsequent charge accumulation start point to a charge transfer point by the first transfer unit. In a CMOS sensor in which a plurality of pixels are regularly arranged in the imaging unit,
Each of the pixels
A photoelectric conversion element that photoelectrically converts incident light and accumulates charges;
In order to reset the photoelectric conversion element, a first transistor in which one of a drain terminal and a source terminal is connected to the photoelectric conversion element;
A second transistor for signal amplification in which one of the drain terminal and the source terminal is connected to the power supply terminal, and a pixel signal corresponding to the charge applied to the gate terminal is output from the other of the drain terminal and the source terminal;
A selection of outputting a pixel signal output from the second transistor from one of the source terminal and the drain terminal to the output signal line when selected by a selection signal applied to each pixel via the selection signal line to the gate terminal. A third transistor for
The gate terminal is connected to the first signal line, one of the drain terminal and the source terminal is connected to the gate terminal of the first transistor, and the other terminal is connected to the second signal line. A fourth transistor for controlling the gate potential of the transistor;
A gate terminal is connected to a third signal line, one of a drain terminal and a source terminal is connected to a connection point between the first transistor and the photoelectric conversion element, and the other terminal is a gate of the second transistor. A fifth transistor for transfer connected to the terminal;
One of the drain terminal and the source terminal is connected to a connection point between the second transistor and the fifth transistor, the other terminal is connected to the power supply terminal, and a reset signal is applied to the gate terminal. A sixth transistor,
Each of the first and fourth transistors of the pixel selected by the logical product of the signals of the first and second signal lines is turned on, the photoelectric conversion element is reset once, and then the first and second transistors again. Reset means for turning on the first and fourth transistors of the pixel selected by the logical product of the signals of the two signal lines and resetting the photoelectric conversion element for the second time;
After the second reset by the reset means, the fifth transistors of all the pixels are turned on by the signal of the third signal line, and the common connection point of the second, fifth, and sixth transistors is set. A charge transfer means for transferring the charges accumulated in the photoelectric conversion element to all the pixels at the same time, and holding the charges in the accumulation unit;
A signal to be sent to the first and second signal lines so that a reset time position of the photoelectric conversion element for the second time by the reset means is set according to the amount of light incident on the photoelectric conversion element of the pixel. A pixel-specific exposure time variable unit that varies an exposure time from a charge accumulation start time after a second reset of the photoelectric conversion element to a charge transfer time by the charge transfer means by generating and outputting the photoelectric conversion element. A CMOS sensor with a pixel-specific shutter function. The exposure time varying means for each pixel is
Comparing a signal level for each pixel and a plurality of threshold values, determining an incident light amount of the pixel, calculating an exposure time for each pixel, and holding the calculation result as a set value;
Horizontal / vertical selection for generating a horizontal selection signal output to one of the first and second signal lines and a vertical selection signal output to the other for each pixel based on the set value calculated and held by the calculation means 3. A CMOS sensor with a pixel-by-pixel shutter function according to claim 1, further comprising a signal generation unit.

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