JP2009092787A - Display device, display device driving method, and electronic apparatus - Google Patents

Abstract

A precharge period can be shortened in the case of adopting a precharge operation for supplying a precharge signal PSIG of a voltage Vpb to a data line as a countermeasure against vertical crosstalk.
Prior to supply of a video signal VSIG to a data line, a precharge signal PSIG of a voltage Vpb for countermeasures against vertical crosstalk is supplied to the data line, and then the potential of the data line is changed to a signal of the video signal VSIG. In a liquid crystal display device that adopts a configuration in which the precharge operation is completed by returning to the halftone potentials Vpgh and Vpgl in the vicinity of the potential, the low side to which the precharge signal PSIG of the voltage Vpb is written as the video signal VSIG lower than the common potential VVC Only the field period is supplied to the data line.
[Selection] Figure 2

Description

  The present invention relates to a display device, a display device driving method, and an electronic apparatus.

  In a display device in which pixels are arranged in a matrix, for example, a liquid crystal display device, in general, the specific resistance (substance specific to a substance) of the liquid crystal is deteriorated by continuously applying a DC voltage having the same polarity to the liquid crystal. In order to prevent this, an AC driving method is employed in which the polarity of the video signal is inverted at a certain period with reference to the common potential (signal center).

  In the case of an active matrix type liquid crystal display device that adopts a field inversion driving method in which the polarity of a video signal is inverted with a period of 1F (1F is one field period) among AC driving methods, the leakage current of a pixel transistor that is a pixel switching element There is a problem that the display quality is deteriorated due to the vertical crosstalk generated due to this.

  Due to the characteristics of the pixel transistor, the leakage current increases when the pixel holds a potential higher than the potential of the data line. Further, the leakage current of the pixel transistor varies depending on the image to be displayed.

  For example, as shown in FIG. 10, when a black window (black region) 201 is displayed with a gray background, for example, even if pixels in the same gray region are displayed, The amount of leakage of the pixel transistors is different between the pixels A1 and A2 connected to the data line A of the background region 202 located at the pixel B1 and the pixels B1 and B2 connected to the data line B wired to the black region 201. .

  As a result, the applied voltage to the liquid crystal is different between the pixels A1 and A2 of the background region 202 positioned on the left and right of the black region 201 and the pixels B1 and B2 of the gray regions 203 and 204 positioned above and below the black region 201. The gray brightness of the gray areas 203 and 204 positioned above and below the black area 201 is different from the original gray of the background area 202, and this brightness difference is visually recognized as vertical crosstalk. Become.

  In addition, the gray region 203 above the black region 201 is visually recognized as vertical crosstalk that is darker than the original gray of the background region 202, and the vertical gray region 204 below the black region 201 is brighter than the original gray of the background region 202. Visible as crosstalk. The reason is as follows.

  When a video signal is written with a positive polarity (or negative polarity) in a certain field with respect to a pixel and a video signal is written with a negative polarity (or positive polarity) in the next field, At the stage of writing, the polarity of the writing row and the polarity of the gray region 203 above the black region 201 where writing is completed have the same negative polarity (or positive polarity), whereas the black region 202 to be written from now on. The polarity of the gray region 204 below is kept positive (or negative) in the previous field.

  As described above, the polarity of the potential held by the pixel with respect to the potential to be written in the black region 201 is different between the gray region 203 above the black region 201 and the gray region 204 below. Since there is a difference in the leak amount of the pixel transistor between the gray area 203 and the lower gray area 204, the gray area 203 above the black area 201 is displayed darker than the original gray, and the gray area below the black area 201 is displayed. In 204, the image is displayed brighter than the original gray.

  In order to eliminate this vertical crosstalk problem, in the conventional technique, a low voltage precharge signal that increases the leakage current of the pixel transistor is supplied to the data lines during the horizontal blanking period. The pixel leak amount is made uniform so that the pixel potential is prevented from becoming non-uniform depending on the video to be displayed (see, for example, Patent Document 1).

  Specifically, as shown in the timing waveform diagram of FIG. 11, the precharge signal PSIG having a low voltage Vpb that increases the leakage current of the pixel transistor is written to the data line at the generation timing of the precharge control pulse PCG. ing. FIG. 12 shows the potentials of the data lines A and B and the potentials of the pixels A1, A2, B1, and B2 in FIG. In FIG. 11 and FIG. 12, for the sake of simplicity, three pixel rows are shown, and a timing relationship of a 3H period (H is a horizontal period) corresponding to the three rows is shown.

  The voltage Vpb of the precharge signal PSIG is near the maximum value Vvbl of the low-side video signal VSIG lower than the common potential VVC, preferably lower than the maximum value Vvbl. The precharge signal PSIG of the voltage Vpb is a period for writing a High-side video signal VSIG higher than the common potential VVC (High-side field period), and a period for writing the Low-side video signal VSIG lower than the common potential VVC (Low-side field period). ) Both are supplied to the data line.

  Here, if the potential of the data line is kept at the potential Vpb that causes the pixel transistor to leak, the potential difference from the potential of the video signal VSIG to be written to the data line is large, so the video signal VSIG is supplied to the data line. As a result, the burden on the circuit system is increased, and insufficient charge / discharge of the data line occurs. As a result, the holding potential may be non-uniform for each data line. This becomes streak-like noise and causes image quality defects.

  In order to avoid the image quality defect due to the leakage of the pixel transistor, in the above conventional technique, as is apparent from the timing waveform diagram of FIG. 11, after the precharge signal PSIG of the voltage Vpb is supplied to the data line, the data The precharge operation is completed by returning the line potential to the halftone potentials Vpgh and Vpgl in the vicinity of the signal potential of the video signal VSIG.

JP 2006-259224 A

  However, in the above prior art, after supplying the precharge signal PSIG of the voltage Vpb to the data line, the potential of the data line is returned to the halftone potentials Vpgh and Vpgl in the vicinity of the signal potential of the video signal VSIG. Since the potential difference between the voltage Vpb and the potential Vpgh is as large as about 8 V, for example, it takes time to charge the data line when the potential of the data line is returned from Vpb to Vpgh.

  On the other hand, with the recent trend toward higher resolution and higher refresh rate, the horizontal blanking period tends to be shorter, and the time allotted to the precharge period for performing the precharge operation is becoming shorter and shorter. is there. Therefore, shortening of the precharge period is desired.

  Therefore, the present invention performs a precharge operation for supplying to the data line a precharge signal PSIG having a voltage Vpb lower than the maximum value Vvgl of the low-side video signal VSIG lower than the common potential VVC as a countermeasure against vertical crosstalk. An object of the present invention is to provide a display device, a display device driving method, and an electronic apparatus that can shorten the precharge period in the case of adopting the configuration to be performed.

  In order to achieve the above object, the present invention includes a pixel array unit in which pixels are arranged in a matrix, and data lines are wired for each column in the matrix pixel arrangement, and the pixels are arranged through the data lines. In the display device in which the polarity of the video signal to be written to is inverted in a field cycle with reference to the common potential, in the first field in which the video signal higher than the common potential is written prior to the supply of the video signal to the data line In the second field in which the first precharge signal of the halftone potential is supplied to the data line and the video signal lower than the common potential is written, the first potential of the potential near the maximum value of the video signal lower than the common potential is set. The second precharge signal and then the first precharge signal are sequentially supplied to the data line.

  In a field inversion drive type display device having a precharge function and an electronic device having the display device, a pixel transistor which is a switching element of a pixel holds a potential higher than the potential of a data line due to its characteristics. Since the leakage current becomes large when the image signal is in the first field in which the video signal higher than the common potential is written in the precharge operation for supplying the precharge signal prior to the supply of the video signal to the data line, By supplying only the first precharge signal to the data line, the potential of the second precharge signal (potential in the vicinity of the maximum value of the video signal lower than the common potential) in the data line is increased to a halftone potential. Since there is no potential change, the time required for charging the data line can be shortened.

  According to the present invention, in the first field in which a video signal higher than the common potential is written, since the high potential change in the data line is eliminated, the time required for charging the data line can be shortened, so the precharge operation is performed. The precharge period can be shortened and the burden on the circuit system for supplying the video signal to the data line can be reduced.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[System configuration]
FIG. 1 is a system configuration diagram showing a display device according to an embodiment of the present invention. Here, a case where the present invention is applied to a liquid crystal display device, particularly an active matrix liquid crystal display device of a field inversion driving method will be described as an example.

  Here, the liquid crystal display device has a panel structure in which two substrates (not shown), at least one of which is transparent, are arranged to face each other, and a liquid crystal material is sealed between the two substrates to form a liquid crystal layer. It has become.

  As shown in FIG. 1, a field inversion drive type active matrix liquid crystal display device 10 according to the present embodiment includes a pixel array unit 30 in which pixels 20 are two-dimensionally arranged in a matrix, a vertical drive circuit 40, a horizontal The system configuration includes a drive circuit 50 and a precharge circuit 60.

  In the liquid crystal display device 10, gate lines (scanning lines) 31-1, 31-2,. Lines 32-1, 32-2,... Are wired. .. And the data lines 32-1, 32-2,... Are arranged at the intersections of the gate lines 31-1, 31-2,.

  Actually, hundreds of thousands to millions of pixels 20 are arranged, but here, for the sake of simplicity, the pixel arrangement is a total of nine pixels arranged in three rows and three columns.

(Pixel configuration)
The pixel 20 has a configuration including a pixel transistor 21, for example, a thin film transistor (TFT), a liquid crystal capacitor 22, and a storage capacitor 23. The pixel transistor 21 has a gate electrode connected to the gate lines 31-1, 31-2, and 31-3, and a source electrode connected to the data lines 32-1, 32-2, and 32-3.

  The liquid crystal capacitor 22 means a capacitive component of a liquid crystal material generated between a pixel electrode and a counter electrode formed opposite thereto, and the pixel electrode is connected to the drain electrode of the pixel transistor 21. A common potential VVC of DC voltage is applied to the counter electrode of the liquid crystal capacitor 22 in common to all pixels. The storage capacitor 23 has one electrode connected to the pixel electrode of the liquid crystal capacitor 22 and the other electrode connected to the counter electrode of the liquid crystal capacitor 22.

  In the pixel 20 configured as described above, the pixel transistor 21 is turned on in units of rows by the vertical scanning by the vertical driving circuit 40, and is supplied from the horizontal driving circuit 50 through the data lines 32-1, 32-2, and 32-3. The signal VSIG is taken into the pixel 30. The signal voltage of the captured video signal VSIG is applied to the liquid crystal capacitor 22 and held in the holding capacitor 23. The storage capacitor 23 holds the potential for a period until the pixel transistor 21 of the same pixel is turned on next time.

(Vertical drive circuit)
The vertical drive circuit 40 includes, for example, a shift register or an output circuit having the number of stages corresponding to the number of rows of the pixel array unit 30 (three rows in this example), and sequentially outputs scanning pulses from each output end. One end of each of the gate lines 31-1, 31-2, 31-3 is connected to each output terminal of the vertical drive circuit 40.

  The vertical drive circuit 40 sequentially scans each pixel 20 of the pixel array unit 30 row by row through the gate lines 31-1, 31-2, 31-3 by sequentially outputting scan pulses from the respective output terminals. While selecting.

  Then, the vertical drive circuit 40 turns on the pixel transistor 21 by the scan pulse, thereby selecting the video signal VSIG supplied from the horizontal drive circuit 50 through the data lines 32-1, 32-2, and 32-3. Is written in each pixel 20.

(Horizontal drive circuit)
The horizontal drive circuit 50 includes, for example, shift registers 51 and analog switches (hereinafter referred to as “horizontal switches”) HSW1 to HSW3 having the number of stages corresponding to the number of columns of the pixel array unit 30 (three columns in this example). It has a configuration.

  The shift register 51 sequentially outputs switch control pulses (sample hold pulses) SHP1 to SHP3 from each shift stage (unit circuit of the shift register 51). The horizontal switches HSW1 to HSW3 are driven by switch control pulses SHP1 to SHP3 sequentially output from the shift register 51, whereby the video signal supply line 52 is supplied to each pixel 20 in the row selected by the vertical drive circuit 40. The video signal VSIG supplied through the line is output, for example, dot-sequentially during one horizontal period through the data lines 32-1, 32-2, and 32-3 for each line (one row) or for each of a plurality of lines.

  The horizontal switches HSW1 to HSW3 are configured by CMOS transmission gates in which an N channel MOS transistor and a P channel MOS transistor are connected in parallel. The switch elements of the horizontal switches HSW1 to HSW3 are not limited to the CMOS transmission gate, and can be configured using a single transistor.

(Precharge circuit)
The precharge circuit 60 includes analog switches (hereinafter, referred to as “precharge switches”) PSW1 to PSW3 provided corresponding to the data lines 32-1, 32-2, and 32-3, and a horizontal drive circuit. 50, prior to supplying (writing) the video signal VSIG to the data lines 32-1, 32-2, and 32-3, the precharge control pulse PCG in a period other than the video signal VSIG writing period, for example, in the horizontal blanking period. The precharge signal PSIG of a predetermined level is supplied (written) to the data lines 32-1, 32-2, and 32-3 by the control by the above.

  The precharge operation by the precharge circuit 60 is performed for the following purpose. That is, as described above, the data lines 32-1, 32-2, and 32 are used to eliminate the problem of vertical crosstalk caused by the leakage of the pixel transistor 21 and to reduce the load on the horizontal drive circuit 50. A precharge operation is performed in order to avoid streak-like image quality defects caused by charge / discharge shortage of -3.

  Corresponding to these two purposes, the precharge signal PSIG selectively takes two values (voltages). Specifically, the precharge signal PSIG includes a voltage Vpb in the vicinity of the maximum value Vvbl of the video signal VSIG that is lower than the common potential VVC for countermeasures against vertical crosstalk, preferably a voltage Vpb that is lower than the maximum value Vvbl, and a horizontal drive circuit. The halftone potentials Vpgh and Vpgl in the vicinity of the signal potential of the video signal VSIG for reducing the burden of 50 and for preventing streak-like image quality defects are selectively taken.

[Characteristics of this embodiment]
In the field inversion driving type active matrix liquid crystal display device 10 having the precharge function with the above configuration, the pixel transistor 21 has a characteristic that the pixel 20 is driven by the potential of the data lines 32-1, 32-2, and 32-3. It is known that the leakage current increases when a higher potential is held in the pixel capacitor 23 and when the potential difference between the drain and source of the pixel transistor 21 is larger.

  Therefore, the horizontal driving circuit 50 has a higher potential than the common potential VVC as compared to the low-side field period in which the video signal VSIG lower than the common potential VVC is written to the data lines 32-1, 32-2, and 32-3. In the High-side field period in which the video signal VSIG is written, the potential difference between the drain and the source of the pixel transistor 21 is smaller. Therefore, the leakage amount in the High-side field period is much smaller than the leakage amount in the Low-side field period. I understand that. The present invention was made paying attention to this point.

  That is, according to the present invention, prior to the supply of the video signal VSIG from the horizontal drive circuit 50 to the data lines 32-1, 32-2, and 32-3, the precharge signal PSIG of the voltage Vpb for countermeasures against vertical crosstalk is provided. Is supplied to the data lines 32-1, 32-2, and 32-3, and then the potentials of the data lines 32-1, 32-2, and 32-3 are changed to halftone potentials Vpgh and Vpgl in the vicinity of the signal potential of the video signal VSIG. In the liquid crystal display device 10 having a configuration in which the precharge operation is completed by returning to the data line 32-1, the precharge signal PSIG having the voltage Vpb is applied to the data lines 32-1 only during the low-side field period in which the video signal VSIG lower than the common potential VVC is written. It is characterized by being supplied to 32-2 and 32-3.

  In the liquid crystal display device 10 according to the present embodiment, data is supplied from the precharge circuit 60 provided separately from the horizontal drive circuit 50 that supplies the video signal VSIG to the data lines 32-1, 32-2, and 32-3. Although the precharge signal PSIG is supplied to the lines 32-1, 32-2, and 32-3, the precharge signal PSIG is supplied to the data lines 32-1, 32-2, and 32-3. The form is not limited to this.

  For example, a precharge analog switch is provided on the horizontal drive circuit 50 side, and the precharge signal PSIG is selectively supplied via the precharge analog switch prior to the supply of the video signal VSIG by the horizontal drive circuit 50. The configuration in which the precharge signal PSIG is superimposed on the video signal VSIG, for example in the horizontal blanking period, and the precharge signal PSIG is selectively supplied via the horizontal switches HSW1 to HSW3 is also included in the data lines 32-1, It is also possible to adopt a form of supplying the precharge signal PSIG to 32-2 and 32-3.

(Precharge operation according to this embodiment)
FIG. 2 is a timing waveform diagram showing a timing relationship between the video signal VSIG, the precharge signal PSIG, the precharge control pulse PCG, and the switch control pulses SHP1 to SHP3 in the liquid crystal display device 10 according to the present embodiment.

  As is clear from the timing waveform diagram of FIG. 2, a High-side field in which a High-side video signal VSIG higher than the common potential VVC is written to the data lines 32-1, 32-2, and 32-3 as the precharge signal PSIG. In the period, only the halftone potential Vpgh is given, and in the Low side field period in which the Low side video signal VSIG lower than the common potential VVC is written, the voltage Vpb and the halftone potential Vpgl for countermeasures against vertical crosstalk are given in a 1H cycle. It is done.

  Switching from the halftone potential Vpgh to the voltage Vpb and switching from the halftone potential Vpgl to the halftone potential Vpgh when the field is switched are performed in the vertical blanking period.

  In the horizontal blanking period, the precharge control pulse PCG becomes logic positive (logic “1”), so that the precharge switches PSW1 to PSW3 are turned on, and the precharge signal PSIG is supplied to the data lines 32-1, 32-2 and 32-3.

  At this time, in the high-side field period, only the halftone potential Vpgh is supplied to the data lines 32-1, 32-2, and 32-3 all together. Thereafter, in the horizontal drive circuit 50, the logical positive switch control pulses SHP1, SHP2, and SHP3 are sequentially output from the shift register 51 in the horizontal effective period, so that the horizontal switches HSW1, HSW2, and HSW3 are sequentially turned on, and the common. A video signal VSIG higher than the potential VVC is supplied to the data lines 32-1, 32-2, and 32-3.

  On the other hand, in the low-side field period, the precharge switches PSW1 to PSW3 are turned on, so that the voltage Vpb for the countermeasure against vertical crosstalk is first, and then the halftone potential Vpgl is the data lines 32-1 and 32-2. , 32-3. Thereafter, in the horizontal drive circuit 50, the horizontal switches HSW1, HSW2, and HSW3 are sequentially turned on during the horizontal effective period, and the video signal VSIG lower than the common potential VVC is supplied to the data lines 32-1, 32-2, and 32-3. Supply.

(When precharge operation is not performed)
Here, prior to the description of the effects of the present embodiment, a case where the precharge operation is not performed will be described.

  FIG. 3 is a waveform diagram showing the potentials of the data lines A and B and the potentials of the pixels A1, A2, B1, and B2 in FIG. 10 when the precharge operation is not performed.

  When the pixel potentials of the pixel A1 and the pixel B1 and the pixel A2 and the pixel B2 are compared, there is a difference in the period in which the leak current of the pixel transistor painted in gray increases. Since the magnitude of the leak current differs between the potentials of the data lines A and B, the leak amount is expressed by the color density (the darker the leak current, the greater the leak current).

  The data line B displaying the black window pattern reaches a lower potential, and the amount of pixel leakage increases. As a result, an image quality defect such as vertical crosstalk as shown in FIG. 10 occurs.

  As described above, a precharge technique is used in order to eliminate the problem of vertical crosstalk caused by leakage of the pixel transistor 21. FIG. 12 shows the potentials of the data lines A and B in FIG. 10 and the potentials of the pixels A1, A2, B1, and B2 in the case of the prior art using this precharge technique (Patent Document 1).

(Operational effect of this embodiment)
FIG. 4 is a waveform diagram showing the potentials of the data lines A and B and the potentials of the pixels A1, A2, B1, and B2 in FIG. 10 when the precharge operation according to the present embodiment is performed.

  As is apparent from the waveform diagram of FIG. 4, only in the low-side field period in which the video signal VSIG lower than the common potential VVC is written, the precharge signal PSIG of the voltage Vpb for countermeasures against vertical crosstalk is applied to the data lines 32-1, The pixel A1 and the pixel B1 are supplied to the 32-2 and 32-3 in the low-side field period in which the leak amount of the pixel transistor 21 is larger than the high-side field period in which the video signal VSIG higher than the common potential VVC is written. In the meantime, since the leak amount between the pixel A2 and the pixel B2 is made uniform, the occurrence of vertical crosstalk can be suppressed.

  When the potential higher than that of the data lines 32-1, 32-2, and 32-3 in which the leakage of the pixel transistor 21 is significant is maintained in the High-side field period, as described above, the data line 32-1. , 32-2 and 32-3, since the video signal VSIG higher than the common potential VVC is written, the potential difference between the drain and source of the pixel transistor 21 is small, and the leakage amount is smaller than the leakage amount in the low-side field period. Therefore, there is no problem in image quality even if the precharge signal PSIG having the voltage Vpb for the countermeasure against vertical crosstalk is not supplied to the data lines 32-1, 32-2, 32-3.

  On the contrary, in the high-side field period, the precharge signal PSIG of the voltage Vpb for the countermeasure against the vertical crosstalk is not supplied to the data lines 32-1, 32-2, 32-3, so that the data lines 32-1, The precharge operation is performed because the large potential change of about 8 V, for example, Vpb → Vpgh in 32-2 and 32-3 is eliminated, and the time required for charging the data lines 32-1, 32-2, and 32-3 can be shortened. Can be shortened.

  In addition, as the potential change of the data lines 32-1, 32-2, and 32-3, the potential change of about 3V, for example, Vpb → Vpgl in the low-side field period may be sufficient, so the precharge for writing the precharge signal PSIG is required. The burden on the circuit 60 can be reduced.

In particular, the liquid crystal display device 10 according to the present embodiment employs a batch precharge method in which all the data lines 32-1, 32-2, and 32-3 are precharged in a batch. In the precharge method, the load on the nF order is large and the burden on the precharge circuit 60 is large. However, since the change from the voltage Vpb having a large potential difference to the halftone potential Vpgh is eliminated, the charge time can be shortened.
In addition, it can contribute to reduction of power consumption of the drive system.

  Since the precharge period can be shortened, the precharge operation can be executed even if the horizontal blanking period is shortened, which helps to realize high resolution and high refresh rate. Further, as the screen becomes larger, the wiring capacity increases, which is a solution to the problem of requiring a longer precharge period.

[Modification]
In the above embodiment, the case where the batch precharge method in which all data lines are precharged is adopted and the precharge signal PSIG is written in the horizontal blanking period has been described as an example. The present invention is not limited to application to the method, and application to a dot sequential precharge method in which data lines are precharged in order is also possible. In the case of the dot sequential precharge method, the precharge signal PSIG may be written in a period other than the period of writing the video signal VSIG to the data line.

  In the above embodiment, the case where the horizontal driving circuit 50 uses the dot sequential driving method in which the video signal VSIG is sequentially written from the first column to each pixel 20 of the selected row by the vertical driving circuit 40 will be described as an example. However, the present invention is not limited to application to the horizontal driving circuit 50 of the dot sequential driving method, but a horizontal driving circuit of the line sequential driving method for writing the video signal VSIG to all the pixels 20 of the selected row all together. The invention can also be applied to a horizontal driving circuit of a selector driving method (time division driving method).

  Here, the selector driving method refers to, for example, a plurality of data lines on the liquid crystal panel in units (sets) for one output of a driver IC (not shown) that supplies the video signal VSIG from the outside of the liquid crystal panel. The plurality of data lines are sequentially selected by an analog switch in a time-sharing manner, while the video signals output in time series for each output of the driver IC with respect to the selected data line are time-sharing. This is a method of driving each data line by distributing and supplying.

  In the above embodiment, the case where the present invention is applied to a liquid crystal display device has been described as an example. However, the present invention is not limited to the application to a liquid crystal display device, and an image such as an organic EL (Electro Luminescence) display device can be used. The present invention can be applied to all display devices by using a precharge technique for writing a precharge signal PSIG of a predetermined level prior to writing the signal VSIG to the data line.

[Application example]
As an example, the display device according to the present invention described above is applied to various electronic devices shown in FIGS. 5 to 9, for example, electronic devices such as digital cameras, notebook personal computers, mobile terminal devices such as mobile phones, and video cameras. The input video signal or the video signal generated in the electronic device can be applied to a display device of an electronic device in any field that displays an image or a video.

  As described above, by using the display device according to the present invention as a display device for electronic devices in all fields, the display device according to the present invention can shorten the precharge period, as is apparent from the description of the embodiment described above. In various electronic devices, it is possible to realize a high resolution and high refresh rate of a video display unit using the display device.

  Note that the display device according to the present invention includes a module-shaped one having a sealed configuration. For example, a display module is provided in which a sealing part (not shown) is provided so as to surround the pixel array part 30, and this sealing part is attached to an opposing part such as transparent glass with an adhesive. The transparent facing portion may be provided with a color filter, a protective film, and the like, and further the above-described light shielding film. Note that the display module may be provided with a circuit unit for inputting / outputting signals from the outside to the pixel array unit, an FPC (flexible printed circuit), and the like.

  Specific examples of electronic devices to which the present invention is applied will be described below.

  FIG. 5 is a perspective view showing an appearance of a television set to which the present invention is applied. The television television set according to this application example includes a video display screen unit 101 including a front panel 102, a filter glass 103, and the like, and is created by using the display device according to the present invention as the video display screen unit 101. .

  6A and 6B are perspective views showing an external appearance of a digital camera to which the present invention is applied. FIG. 6A is a perspective view seen from the front side, and FIG. 6B is a perspective view seen from the back side. The digital camera according to this application example includes a light emitting unit 111 for flash, a display unit 112, a menu switch 113, a shutter button 114, and the like, and is manufactured by using the display device according to the present invention as the display unit 112.

  FIG. 7 is a perspective view showing an external appearance of a notebook personal computer to which the present invention is applied. A notebook personal computer according to this application example includes a main body 121 including a keyboard 122 that is operated when characters and the like are input, a display unit 123 that displays an image, and the like, and the display device according to the present invention is used as the display unit 123. It is produced by this.

  FIG. 8 is a perspective view showing the appearance of a video camera to which the present invention is applied. The video camera according to this application example includes a main body 131, a lens 132 for shooting an object on a side facing forward, a start / stop switch 133 at the time of shooting, a display unit 134, and the like. It is manufactured by using a display device.

  FIG. 9 is an external view showing a mobile terminal device to which the present invention is applied, for example, a mobile phone, in which (A) is a front view in an open state, (B) is a side view thereof, and (C) is closed. (D) is a left side view, (E) is a right side view, (F) is a top view, and (G) is a bottom view. The mobile phone according to this application example includes an upper housing 141, a lower housing 142, a connecting portion (here, a hinge portion) 143, a display 144, a sub display 145, a picture light 146, a camera 147, and the like. Alternatively, the sub-display 145 is manufactured by using the display device according to the present invention.

1 is a system configuration diagram showing an active matrix type liquid crystal display device of a field inversion driving method according to an embodiment of the present invention. FIG. 5 is a timing waveform diagram showing a timing relationship among a video signal VSIG, a precharge signal PSIG, a precharge control pulse PCG, and switch control pulses SHP1 to SHP3 in the liquid crystal display device according to the present embodiment. FIG. 11 is a waveform diagram showing the potentials of the data lines A and B in FIG. 10 and the potentials of the pixels A1, A2, B1, and B2 when the precharge operation is not performed. FIG. 11 is a waveform diagram showing each potential of the data lines A and B of FIG. 10 and each potential of the pixels A1, A2, B1, and B2 when the precharge operation according to the present embodiment is performed. It is a perspective view which shows the external appearance of the television set to which this invention is applied. It is a perspective view which shows the external appearance of the digital camera to which this invention is applied, (A) is the perspective view seen from the front side, (B) is the perspective view seen from the back side. 1 is a perspective view illustrating an appearance of a notebook personal computer to which the present invention is applied. It is a perspective view which shows the external appearance of the video camera to which this invention is applied. BRIEF DESCRIPTION OF THE DRAWINGS It is an external view which shows the mobile telephone to which this invention is applied, (A) is the front view in the open state, (B) is the side view, (C) is the front view in the closed state, (D) Is a left side view, (E) is a right side view, (F) is a top view, and (G) is a bottom view. It is explanatory drawing of vertical crosstalk. FIG. 7 is a timing waveform diagram showing a timing relationship among a video signal VSIG, a precharge signal PSIG, a precharge control pulse PCG, and switch control pulses SHP1 to SHP3 in the prior art. FIG. 11 is a waveform diagram showing the potentials of the data lines A and B of FIG. 10 and the potentials of the pixels A1, A2, B1, and B2 when the precharge operation according to the conventional technique is performed.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Liquid crystal display device, 20 ... Pixel, 21 ... Pixel transistor, 22 ... Liquid crystal capacity, 23 ... Retention capacity, 30 ... Pixel array part, 31-1, 31-2, 31-3 ... Gate line, 32-1, 32-2, 32-3 ... Data line, 40 ... Vertical drive circuit, 50 ... Horizontal drive circuit, 51 ... Shift register, 52 ... Video signal supply line, 60 ... Precharge circuit, HSW1, HSW2, HSW3 ... Horizontal switch, PSW1, PSW2, PSW3 ... Precharge switch

Claims (5)

Pixels are arranged in a matrix, and a pixel array unit is provided in which data lines are wired for each column with respect to the matrix pixel arrangement. The polarity of the video signal written to the pixels through the data lines is based on a common potential. A display device that reverses with a field period,
Prior to supplying the video signal to the data line, in a first field in which a video signal higher than the common potential is written, a first precharge signal having a halftone potential is supplied to the data line, In a second field in which a lower video signal is written, a second precharge signal having a potential in the vicinity of the maximum value of the video signal lower than the common potential is supplied, and then the first precharge signal is sequentially supplied to the data line. A display device. The display device according to claim 1, wherein the first and second precharge signals are supplied to the data line during a horizontal blanking period prior to the supply of the video signal to the data line. The display device according to claim 1, wherein the second precharge signal is lower than a maximum value of a video signal lower than the common potential. Pixels are arranged in a matrix, and a pixel array portion in which data lines are wired for each column with respect to the matrix-like pixel arrangement, and the polarity of a video signal written to the pixels through the data lines is based on a common potential. And a display device driving method that reverses in a field cycle,
Prior to supplying the video signal to the data line, in a first field in which a video signal higher than the common potential is written, a first precharge signal having a halftone potential is supplied to the data line, In a second field in which a lower video signal is written, a second precharge signal having a potential in the vicinity of the maximum value of the video signal lower than the common potential is supplied to the data line in order. A method for driving a display device. Pixels are arranged in a matrix, and a pixel array unit is provided in which data lines are wired for each column with respect to the matrix pixel arrangement. The polarity of the video signal written to the pixels through the data lines is based on a common potential. And having a display device that reverses in the field period,
Prior to supplying the video signal to the data line, in a first field in which a video signal higher than the common potential is written, a first precharge signal having a halftone potential is supplied to the data line, In a second field in which a lower video signal is written, a second precharge signal having a potential in the vicinity of the maximum value of the video signal lower than the common potential is supplied, and then the first precharge signal is sequentially supplied to the data line. Electronic equipment characterized by

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