JP2012208635A - Constant voltage circuit and amplifier circuit - Google Patents

Abstract

Provided are a constant voltage circuit and an amplifier circuit that can prevent oscillation even when connected to an amplifier having a transistor having a large gate capacitance.
A constant voltage circuit includes a differential amplifying unit having a first input terminal to which a predetermined voltage is applied and a second input terminal connected to an output terminal, the source being The source-grounded amplifier 42 includes a transistor T46 that is grounded, has a drain connected to the output terminal 46, and a gate to which the output of the differential amplifier 41 is applied. A resistor 47 and a capacitor 48 are connected in series between the gate and drain of the transistor T46. The voltage Vg output from the constant voltage circuit 40 is supplied from the bias terminal 26b of the amplifier 20 to the transistors T3 and T4 via the bias feeding inductors 25a and 25b.
[Selection] Figure 11

Description

  The present invention relates to a constant voltage circuit and an amplifier circuit.

  An amplifier used in a wireless device such as a cellular phone is required to reduce adjacent channel leakage distortion as much as possible.

  One of the causes for increasing the adjacent channel leakage distortion of the amplifier is a variation in bias voltage. Usually, a constant voltage circuit that outputs a constant voltage is used as the bias circuit. In this case, if the bias terminal of the amplifier has a high impedance, the bias voltage is affected by the envelope and fluctuates when a data modulation signal is input to the amplifier. This increases the distortion of the amplifier.

  In order to reduce the distortion of the amplifier, a large-capacity pass capacitor is usually connected to the bias terminal of the amplifier.

JP 2002-108467 A JP 2008-42625 A

  An object of the present invention is to provide a constant voltage circuit and an amplifier circuit that can prevent oscillation even when connected to an amplifier having a transistor having a large gate capacitance.

  According to one aspect of the disclosed technology, a differential amplifier including a first input terminal to which a predetermined voltage is applied, and a second input terminal connected to the output terminal, a source is grounded, A source-grounded amplifier including a transistor having a drain connected to the output terminal and a gate to which an output of the differential amplifying unit is provided; a resistor and a capacitor connected in series between the gate and the drain of the transistor; A constant voltage circuit is provided.

  According to another aspect of the disclosed technology, a constant voltage circuit that outputs a predetermined voltage from an output terminal, and an amplifier that includes a bias terminal connected to the output terminal, the amplifier includes: A first transistor connected to the differential input terminal, a second transistor connected to the second differential input terminal, and a first transistor connected between the bias terminal and the first transistor. And a second bias power supply unit connected between the bias terminal and the second transistor, wherein the constant voltage circuit has a first input terminal to which a predetermined voltage is applied. And a second input terminal connected to the output terminal, a source is grounded, a drain is connected to the output terminal, and an output of the differential amplifier is given to a gate. A so-called third transistor A scan grounded amplifier, the amplifier circuit is provided with a resistor and a capacitor connected in series between the gate and the drain of the third transistor.

  According to the constant voltage circuit according to the above aspect, oscillation can be prevented even when connected to an amplifier having a transistor having a large gate capacitance.

FIG. 1 is a diagram illustrating an amplifier and a waveform of a signal input to the amplifier. FIG. 2 is a diagram schematically showing the frequency spectrum of the output of the amplifier. FIG. 3 is a diagram illustrating an amplifier in which a pass capacitor is connected to the bias terminal. FIG. 4 is a diagram schematically showing the frequency spectrum of the output of the amplifier. FIG. 5 is a circuit diagram showing an example of the differential amplifier. FIG. 6 is a circuit diagram illustrating an example of a bias circuit. FIG. 7 is a circuit diagram showing an example in which the bias circuit of FIG. 6 is used in the differential amplifier of FIG. FIG. 8A is a diagram simulating the input waveform of the bias circuit of FIG. 7, and FIG. 8B is a diagram simulating the output waveform of the bias circuit. FIG. 9 is an equivalent circuit diagram for explaining the mechanism of oscillation of the bias circuit. FIG. 10 is a diagram illustrating a result of examining the frequency dependence characteristics of the pass phase and loop gain of the bias circuit by simulation. FIG. 11 is a circuit diagram of a constant voltage circuit according to the embodiment and an amplifier circuit using the constant voltage circuit as a bias circuit. FIG. 12 is a diagram illustrating a result obtained by simulating the frequency dependence characteristics of the passing phase and the loop gain of the constant voltage circuit (bias circuit) according to the embodiment. FIG. 13A is a diagram simulating the input waveform of the constant voltage circuit (bias circuit) of the embodiment, and FIG. 13B is a diagram simulating the output waveform of the constant voltage circuit. FIG. 14 is a diagram illustrating a result of simulating distortion characteristics of the amplifier circuit according to the embodiment. FIG. 15 is a diagram illustrating an equivalent circuit of the λ / 4 short stub.

  Hereinafter, before describing the embodiment, a preliminary matter for facilitating understanding of the embodiment will be described.

  FIG. 1 is a diagram showing an amplifier and a waveform of a signal input to the amplifier, and FIG. 2 is a diagram schematically showing a frequency spectrum of the output of the amplifier. Here, as shown in FIG. 1, it is assumed that a data modulation signal, that is, a signal in which a data signal having a frequency in the order of MHz is superimposed on a carrier wave having a frequency in the order of GHz is input to the input terminal 11 of the amplifier 10. Further, it is assumed that bias voltages Vd and Vg are supplied to the bias terminals 13 and 14 of the amplifier 10.

  As shown in FIG. 1, when the data modulation signal is input to the input terminal 11 of the amplifier 10, the bias voltages Vd and Vg vary with the frequency of the envelope of the data modulation signal. As a result, adjacent channel leakage distortion appears at the output terminal 12 of the amplifier 10 before and after the signal band as shown in FIG. In particular, the third-order intermodulation distortion (IM3) appearing on the higher frequency side than the signal band is large, and this third-order intermodulation distortion becomes a problem.

  FIG. 3 shows an amplifier in which a pass capacitor is connected to the bias terminal, and FIG. 4 is a diagram schematically showing the frequency spectrum of the output of the amplifier. If the large-capacity pass capacitors 15a and 15b are connected to the bias terminals 13 and 14 of the amplifier 10 as shown in FIG. 3, the fluctuations in the bias voltages Vd and Vg can be reduced to a negligible level. Leakage distortion can be suppressed.

  FIG. 5 is a circuit diagram showing an example of the differential amplifier. The differential amplifier 20 includes a first-stage amplifier circuit 21, a second-stage amplifier circuit 22, matching circuits 23a and 23b, and bias feeding inductors (or λ / 4 short stubs: the same applies hereinafter) 24a and 24b. , 25a, 25b.

  The first stage amplifier circuit 21 has n-type MOS transistors T1, T2. The gate of the transistor T1 is connected to the differential input terminal 27a, and the gate of the transistor T2 is connected to the differential input terminal 27b. The sources of the transistors T1 and T2 are both grounded, the drain of the transistor T1 is connected to the matching circuit 23a, and the drain of the transistor T2 is connected to the matching circuit 23b. A bias voltage Vd is supplied from the bias terminal 26a to the drains of the transistors T1 and T2 via the inductors 24a and 24b.

  The second-stage amplifier circuit 22 includes n-type MOS transistors T3 and T4. The gate of the transistor T3 is connected to the matching circuit 23a, and the gate of the transistor T4 is connected to the matching circuit 23b. A bias voltage Vg is supplied to the gates of the transistors T3 and T4 from the bias terminal 26b via the inductors 25a and 25b. Further, the sources of the transistors T3 and T4 are grounded, the drain of the transistor T3 is connected to the differential output terminal 28a, and the drain of the transistor T4 is connected to the differential output terminal 28b.

  In such a differential amplifier 20, the carrier wave of the data modulation signal input to the differential input terminal 27a is in reverse phase to the carrier wave of the data modulation signal input to the differential input terminal 27b. For this reason, with respect to the carrier wave, the midpoint A of the inductors 24a and 24b and the midpoint B of the inductors 25a and 25b become virtual grounds and are stabilized.

  However, since the envelopes of the signals input to the differential input terminals 27a and 27b are in phase, the voltages at the midpoint A of the inductors 24a and 24b and the midpoint B of the inductors 25a and 25b vary with the envelope frequency.

  If a large-capacity pass capacitor 29 is connected between the terminals 26a and 26b and the ground, as indicated by the alternate long and short dash line in FIG. 5, the fluctuations in the bias voltages Vd and Vg can be reduced to a negligible level. . However, since the envelope frequency is generally as low as MHz, a large-capacity pass capacitor of μF order is required to stabilize the bias voltages Vd and Vg. It is difficult to integrate such a large-capacity pass capacitor in a semiconductor chip.

  A voltage follower circuit using a current mirror is known as a low impedance bias circuit (constant voltage circuit) that can be integrated in a semiconductor chip. FIG. 6 is a circuit diagram showing an example of this type of bias circuit.

  The bias circuit 30 includes a differential amplifier 31 and a common source amplifier 32. The differential amplifier 31 includes p-type MOS transistors T11 and T12 and n-type MOS transistors T14 and T15, and the common-source amplifier 32 includes a p-type MOS transistor T13, an n-type MOS transistor T16, and a current source 34. .

  The sources of the p-type MOS transistors T11 and T12 of the differential amplifier 31 are both connected to a terminal 33 to which the voltage Vdd is supplied, and the sources of the n-type MOS transistors T14 and T15 are both grounded. The drain of the transistor T11, the drain of the transistor T14, the gate of the transistor T14, and the gate of the transistor T15 are electrically connected to each other through the connection point N1. Further, the drain of the transistor T12 and the drain of the transistor T15 are both connected to the connection point N2 that is the output terminal of the differential amplifier 31.

  The gate of the transistor T12 serving as the first input terminal of the differential amplifier 31 is connected to the terminal 34 to which the voltage Vin is supplied, and the gate of the transistor T11 serving as the second input terminal of the differential amplifier 31 is It is connected to the connection point N3.

The source of the p-type MOS transistor T13 of the common source amplifier 32 is connected to the terminal 33 to which the voltage Vdd is supplied, and the source of the n-type MOS transistor T16 is grounded. The drains of these transistors T13 and T16 are connected to the connection point N3 and the output terminal 36. Further, the gate of the transistor T13 is connected to the current source 35, and the gate of the transistor T16 is connected to the connection point N2. In such a bias circuit 30, the voltage Vin supplied to the terminal 34 and the output terminal 36 are The output voltage Vout is the same voltage. When the bias circuit 30 is viewed from the output terminal 36, the output impedance is low. For example, when the current value is 0.1 mA, it is about 50Ω.

  FIG. 7 is a circuit diagram showing an example in which the bias circuit of FIG. 6 is used in the differential amplifier of FIG. 7, the same components as those in FIGS. 5 and 6 are denoted by the same reference numerals. In FIG. 7, only the bias circuit (output voltage Vg) connected to the bias terminal 26b is shown, but a similar bias circuit (output voltage Vd) is also connected to the bias terminal 26a.

  As shown in FIG. 7, the voltage Vg output from the output terminal 36 of the bias circuit 30 is supplied to the gates of the transistors T 3 and T 4 via the bias power supply inductors 25 a and 25 b in the differential amplifier 20. At this time, the load of the bias circuit 30 is the inductors 25a and 25b and the gate input capacitance Cgs of the transistors T3 and T4.

  In a high-output differential amplifier, a transistor having a large gate width is used. Therefore, the gate capacitance Cgs of the transistor becomes large (for example, 1 pF or more). In the low-power amplifier and other functional circuits, since the transistor size is small, the gate capacitance Cgs is small, and the gate capacitance Cgs hardly affects the operation of the bias circuit.

  8A is a diagram simulating the input waveform of the bias circuit 30 in FIG. 7, and FIG. 8B is a diagram simulating the output waveform of the bias circuit 30 in the same manner. Here, the waveform of a signal output from the output terminal 36 of the bias circuit 30 when a step signal changing from 0 V to 0.4 V is applied to the terminal 34 of the bias circuit 30 is simulated.

  As can be seen from FIGS. 8A and 8B, when the gate capacitance Cgs of the transistors T3 and T4 in the amplifier 20 is large, from the moment when the voltage Vin supplied to the terminal 34 of the bias circuit 30 rises to 0.4V. The bias circuit 30 oscillates.

  FIG. 9 is an equivalent circuit diagram for explaining the oscillation mechanism of the bias circuit 30. As shown in FIG. 9, the bias circuit 30 can be considered as a two-stage inverter circuit in which a part of the output signal is fed back to the input terminal. Further, the gate capacitance Cgs of the transistor can be considered as a load connected between the output terminal of the inverter circuit and the ground.

  In the feedback type amplifier circuit represented as the equivalent circuit diagram of FIG. 9, the oscillation condition is determined by the loop gain and the passing phase. That is, if the phase difference (passing phase) of the output signal with respect to the input signal is approximately 180 degrees and the loop gain is 1 or more, the feedback amplifier circuit oscillates.

  In FIG. 10, the horizontal axis represents frequency, the vertical axis represents pass phase (right vertical axis) and loop gain (left vertical axis), and the frequency dependence characteristics of the pass phase and loop gain of the bias circuit are simulated and investigated. The results are shown. In FIG. 10, the alternate long and short dash line indicates the simulation result when there is no load, and the solid line indicates when a capacitor corresponding to the gate capacitance Cgs of the transistor is connected between the output terminal and the ground as shown in FIG. The simulation results are shown.

  In this case, as can be seen from FIG. 10, the loop gain is 1 or more regardless of the presence or absence of the load in the range where the frequency is 120 MHz or less.

  On the other hand, as can be seen from FIG. 10, when there is no load, the passing phase is about 100 degrees or less at a frequency (120 MHz or less) at which the loop gain is 1 or more. Therefore, it can be seen that the bias circuit does not oscillate when there is no load.

  However, when a capacitor is connected as a load, the phase change with increasing frequency is large, and the value of the passing phase is close to 180 degrees even when the loop gain is 1 or more. For this reason, when a capacitor is connected as a load, the bias circuit oscillates as shown in FIG.

  When the bias circuit oscillates, a bias voltage cannot be stably supplied to the amplifier. Therefore, not only the distortion of the amplifier cannot be reduced, but also the oscillation signal of the bias circuit is amplified and an unnecessary wave is output.

  In the following embodiments, a constant voltage circuit capable of preventing oscillation even when connected to an amplifier having a transistor having a large gate capacitance Cgs will be described.

(Embodiment)
FIG. 11 is a circuit diagram of a constant voltage circuit according to the embodiment and an amplifier circuit using the constant voltage circuit as a bias circuit.

  The constant voltage circuit 40 according to the present embodiment includes a differential amplifying unit 41 and a common source amplifying unit 42. The differential amplifier 41 includes p-type MOS transistors T41 and T42 and n-type MOS transistors T44 and T45. The common-source amplifier 42 includes a p-type MOS transistor T43, an n-type MOS transistor T46, It has a current source 45, a resistor 47, and a capacitor 48.

  The sources of the p-type MOS transistors T41 and T42 of the differential amplifier 41 are both connected to the terminal 43 to which the voltage Vdd is supplied, and the sources of the n-type MOS transistors T44 and T45 are both grounded. Further, the drain of the transistor T41, the drain of the transistor T44, the gate of the transistor T44, and the gate of the transistor T45 are electrically connected to each other through the connection point N1. Furthermore, the drain of the transistor T42 and the drain of the transistor T45 are both connected to the connection point N2 that is the output terminal of the differential amplifier 41.

  The gate of the transistor T42 serving as the first input terminal of the differential amplifier 41 is connected to the terminal 44 to which the voltage Vin is supplied, and the gate of the transistor T41 serving as the second input terminal of the differential amplifier 41 is It is connected to the connection point N3.

  The source of the p-type MOS transistor T43 of the common-source amplifier 42 is connected to the terminal 43 to which the voltage Vdd is supplied, and the source of the n-type MOS transistor T46 is grounded. The drains of these transistors T43 and T46 are connected to the connection point N3 and the output terminal 46. Further, the gate of the transistor T43 is connected to the current source 45, and the gate of the transistor T46 is connected to the connection point N2. Furthermore, a resistor 47 and a capacitor 48 are connected in series between the gate and drain of the transistor T46.

  Since the circuit configuration of the differential amplifier 20 is basically the same as that of the differential amplifier 20 of FIG. 5, the description thereof is omitted here. In FIG. 11, only the constant voltage circuit (bias circuit) whose output voltage is Vg connected to the bias terminal 26b of the differential amplifier 20 is shown, but the output voltage of the bias terminal 26a is also constant as Vd. A voltage circuit is connected. The constant voltage circuit 40 shown in FIG. 11 may be connected to only one of the bias terminals 26a and 26b of the differential amplifier 20, and a pass capacitor may be externally attached to the other bias terminal.

  In the constant voltage circuit (bias circuit) according to the present embodiment, as described above, the resistor 47 and the capacitor 48 are connected in series between the gate and the drain of the transistor T46 in the common source amplifier 42. By feeding back the output of the constant voltage circuit 40 to the gate of the transistor T46 via the RC circuit formed by the resistor 47 and the capacitor 48, the loop gain of the constant voltage circuit 40 is reduced, and the change of the passing phase is moderated. can do. The resistance value of the resistor 47 and the capacitance value of the capacitor 48 are set so that the loop gain and the passing phase do not satisfy the oscillation condition.

  In FIG. 12, the horizontal axis indicates the frequency, the vertical axis indicates the pass phase (right vertical axis) and the loop gain (left vertical axis), and the pass phase and loop of the constant voltage circuit (bias circuit) according to the present embodiment. The result of having investigated the frequency dependence characteristic of the gain by simulating is shown. In FIG. 12, the alternate long and short dash line shows the simulation result when there is no load, and the solid line shows the simulation result when a capacitor corresponding to the gate capacitance Cgs of the transistor is connected as a load between the output terminal and the ground. ing.

  As can be seen from FIG. 12, when a capacitor is connected as the load of the constant voltage circuit (bias circuit) 40, the loop gain becomes 1 or more in the region where the frequency is about 80 MHz or less. On the other hand, in the region where the frequency is 80 MHz or less, the passing phase is 100 degrees or less. Therefore, it can be seen that the constant voltage circuit 40 does not oscillate.

  FIG. 13A is a diagram simulating the input waveform of the constant voltage circuit (bias circuit) 40 of this embodiment, and FIG. 13B is a diagram simulating the output waveform of the constant voltage circuit 40. Here, the waveform of a signal output from the output terminal 46 of the constant voltage circuit 40 when a step-like signal changing from 0 V to 0.4 V is applied to the terminal 44 of the constant voltage circuit 40 is simulated.

  As can be seen from FIGS. 13A and 13B, in the constant voltage circuit 40 according to the present embodiment, when the pulsed signal Vin is input to the terminal 44, the same voltage as the input signal Vin from the output terminal 46. Is output. From this simulation result, it can be seen that the constant voltage circuit (bias circuit) 40 according to the present embodiment can supply a stable bias.

  FIG. 14 is a diagram showing a result of simulating the distortion characteristics of the amplifier circuit of FIG. 11 with the output of the amplifier circuit on the horizontal axis and the distortion strength on the vertical axis. In FIG. 14, the alternate long and short dash line shows the distortion characteristics (comparative example) when a high impedance power supply is directly connected to the bias terminal without using the bias circuit, and the solid line uses the bias circuit (constant voltage circuit) having the configuration shown in FIG. It is a distortion characteristic (Example) when doing. However, here, a two-tone signal (a signal in which a MHz-order data signal is superimposed on a GHz-order carrier wave) is input to the input terminal of the amplifier circuit, and third-order intermodulation distortion (IM3) is output from the output power of the amplifier circuit. Is plotted as a function of.

  From FIG. 14, it can be seen that the overall distortion output of the amplifier circuit of the embodiment is smaller than that of the amplifier circuit of the comparative example not using the bias circuit. In particular, when the output power is around 26 dBm, the third-order intermodulation distortion is about −28 dBm in the comparative example, whereas it is about −34 dBm in the example, and it can be seen that the distortion can be reduced by about 6 db.

  In the above-described embodiment, the case where the inductor is disposed as the bias power feeding portion between the bias terminal of the differential amplifier 20 and the gate of the transistor has been described. However, a λ / 4 short stub is disposed instead of the inductor. Also good. FIG. 15 shows an equivalent circuit of the λ / 4 short stub. As in the equivalent circuit of FIG. 15, the λ / 4 short stub can be considered as an inductor and a capacitor connected in parallel.

  The following additional notes are disclosed with respect to the above embodiments.

(Supplementary Note 1) A differential amplifier including a first input terminal to which a predetermined voltage is applied, and a second input terminal connected to the output terminal;
A source-grounded amplifier including a transistor whose source is grounded, whose drain is connected to the output terminal, and whose gate is supplied with the output of the differential amplifier;
A constant voltage circuit comprising: a resistor and a capacitor connected in series between a gate and a drain of the transistor.

  (Supplementary note 2) The constant voltage circuit according to Supplementary note 1, wherein the differential amplifier section includes a current mirror circuit.

  (Supplementary note 3) The constant voltage circuit according to Supplementary note 1 or 2, wherein the same voltage as the voltage inputted to the first input terminal of the differential amplifier is outputted from the output terminal.

(Appendix 4) a constant voltage circuit that outputs a predetermined voltage from the output terminal;
An amplifier having a bias terminal connected to the output terminal;
The amplifier includes a first transistor connected to a first differential input terminal, a second transistor connected to a second differential input terminal, and between the bias terminal and the first transistor. A first bias power supply unit connected to the first bias power supply unit, and a second bias power supply unit connected between the bias terminal and the second transistor,
The constant voltage circuit includes: a differential amplification unit including a first input terminal to which a predetermined voltage is applied; and a second input terminal connected to the output terminal;
A source-grounded amplifier including a third transistor, the source of which is grounded, the drain of which is connected to the output terminal, and the output of the differential amplifier section is supplied to the gate;
An amplifier circuit comprising a resistor and a capacitor connected in series between a gate and a drain of the third transistor.

  (Supplementary Note 5) The amplifier circuit according to Supplementary Note 4, wherein each of the first bias feeding unit and the second bias feeding unit is an inductor.

  (Supplementary note 6) The amplifier circuit according to supplementary note 4, wherein each of the first bias feeding unit and the second bias feeding unit is a λ / 4 short stub.

  DESCRIPTION OF SYMBOLS 10 ... Amplifier, 11 ... Input terminal, 12 ... Output terminal, 13, 14 ... Bias terminal, 15a, 15b ... Bus capacitor, 20 ... Differential amplifier, 21, 22 ... Amplifier circuit, 23a, 23b ... Matching circuit, 24a , 24b, 25a, 25b ... bias feeding inductors, 26a, 26b ... bias terminals, 27a, 27b ... differential input terminals, 28a, 28b ... differential output terminals, 30 ... bias circuit, 31 ... differential amplification unit, 32 Reference source amplifying unit 33, 34 Terminal 35, Current source 36 Output terminal 40 Constant voltage circuit (bias circuit) 41 Differential amplification unit 42 Source grounded amplification unit 43 44 ... Terminal, 45 ... Current source, 46 ... Output terminal, 47 ... Resistance, 48 ... Capacitor.

Claims (4)

A differential amplifier having a first input terminal to which a predetermined voltage is applied and a second input terminal connected to the output terminal;
A source-grounded amplifier including a transistor whose source is grounded, whose drain is connected to the output terminal, and whose gate is supplied with the output of the differential amplifier;
A constant voltage circuit comprising: a resistor and a capacitor connected in series between a gate and a drain of the transistor.   The constant voltage circuit according to claim 1, wherein the differential amplifier includes a current mirror circuit.   3. The constant voltage circuit according to claim 1, wherein the same voltage as the voltage input to the first input terminal of the differential amplifier is output from the output terminal. 4. A constant voltage circuit for outputting a predetermined voltage from the output terminal;
An amplifier having a bias terminal connected to the output terminal;
The amplifier includes a first transistor connected to a first differential input terminal, a second transistor connected to a second differential input terminal, and between the bias terminal and the first transistor. A first bias power supply unit connected to the first bias power supply unit, and a second bias power supply unit connected between the bias terminal and the second transistor,
The constant voltage circuit includes: a differential amplification unit including a first input terminal to which a predetermined voltage is applied; and a second input terminal connected to the output terminal;
A source-grounded amplifier including a third transistor, the source of which is grounded, the drain of which is connected to the output terminal, and the output of the differential amplifier section is supplied to the gate;
An amplifier circuit comprising a resistor and a capacitor connected in series between a gate and a drain of the third transistor.

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