JP2013073622A - Communication interface, communication method, and image forming apparatus - Google Patents

Abstract

Provided are a communication interface, a communication method, and an image forming apparatus capable of increasing the communication speed even when the capacity of a reception FIFO is limited.
A communication interface transmits received data, a FIFO write instruction signal, and a FIFO read instruction signal obtained by delaying the FIFO write signal to a reception FIFO of a different communication interface, and the received data is transmitted to a reception FIFO of a different communication interface. A reception FIFO connection circuit is provided that stores the received data in the order received and reads the received data stored in the distributed order in the order received and outputs the data to the memory.
[Selection] Figure 2

Description

  Embodiments described herein relate generally to a communication interface, a communication method, and an image forming apparatus.

  The image forming apparatus includes a parent substrate that controls the entire image forming apparatus, a child substrate connected to the parent substrate, and a child substrate connected to the child substrate. For example, each mechanism such as a paper feed mechanism, a paper discharge mechanism, and a scanner mechanism is provided. A plurality of grandchild boards to be controlled.

  The parent board and the child board, and the child board and each grandchild board are connected by a communication interface to exchange data.

  The communication interface includes a DMAC, a transmission FIFO, a reception FIFO, and a communication circuit.

  The capacity of the receiving FIFO is selected optimally according to the normal operation of the image forming apparatus.

  Here, in recent years, with the complexity of the system, maintenance for rewriting a large-capacity program under the user has become necessary.

  In a conventional image forming apparatus, received data is temporarily stored in one receiving FIFO, which is read out by the DMAC and stored in the main memory.

  Accordingly, since the capacity of the receiving FIFO is limited while the capacity of the program to be updated is large, the communication speed cannot be increased, and the updating takes time.

  In this regard, a technique has been proposed in which a downloaded program is once stored in a RAM.

  However, even in this technique, the communication speed is regulated by the capacity of the receiving FIFO.

JP-A-9-114614

  Accordingly, there is a need for a communication interface, a communication method, and an image forming apparatus that can increase the communication speed even when the capacity of the receiving FIFO is limited.

  In order to solve the above problems, an embodiment of the present invention includes a transmission communication circuit that transmits transmission data, and a transmission FIFO that temporarily stores transmission data and outputs transmission data stored in a first-in first-out manner. A reception communication circuit that receives the reception data, a reception FIFO that temporarily stores the reception data and outputs the reception data stored on a first-in first-out basis, and a transmission FIFO and a reception FIFO connected to the system bus The DMAC for controlling the operation of the received data, the received data, the FIFO write instruction signal, and the FIFO read instruction signal obtained by delaying the FIFO write signal are transmitted to the reception FIFOs of different communication I / Fs, and the received data is transmitted to the different communication I / Fs. The received data is distributed and stored in the receiving FIFO, and the received data stored in a distributed manner is read out and output to the memory. Providing a receiving FIFO connection circuit, a communication interface with a.

1 is a block diagram illustrating a configuration of an image forming apparatus. It is a figure which shows the structure of a communication interface. It is a block diagram which shows the structure of the FIFO connection circuit for reception of the 2nd communication interface with which a sub-board | substrate is equipped. It is a block diagram which shows the structure of the FIFO connection circuit for reception of the 1st 3rd communication interface with which a sub-board | substrate is equipped. It is a block diagram which shows the structure of the FIFO connection circuit for reception of the 2nd 3rd communication interface with which a sub-board | substrate is equipped.

  Hereinafter, embodiments of a communication interface, a communication method, and an image forming apparatus will be described in detail with reference to the drawings.

The communication interface according to the present embodiment includes a transmission communication circuit that transmits transmission data, a transmission FIFO that temporarily stores transmission data and outputs transmission data stored in a first-in first-out manner, and a reception circuit that receives reception data. A communication circuit, a receive FIFO that temporarily stores received data and outputs received data stored in first-in first-out, a DMAC that is connected to the system bus and controls the operation of the transmit FIFO and receive FIFO, and receive The data, the FIFO write instruction signal, and the FIFO read instruction signal obtained by delaying the FIFO write signal are transmitted to the reception FIFO of the different communication I / F, and the received data is received in the reception FIFO of the different communication I / F. Receiving FIFO that stores the received data in a distributed manner and reads the received data in the order received and outputs them to the memory Figure 1 comprising a connection circuit, a is a block diagram showing a configuration of an image forming apparatus 10 of the present embodiment. As shown in FIG. 1, the image forming apparatus 10 has a first communication interface (hereinafter referred to as an I / F) 25 that performs overall control of the image forming apparatus 10 and communicates with the child board 30. 20 and a second communication I / F 33 that communicates with the parent board 20 and a third communication I / F 37A, 37B, and 37C that communicates with a plurality of grandchild boards 40A, 40B, and 40C that control different mechanisms. The sub board 30 and grandchild boards 40A, 40B, and 40C including the fourth communication I / F 41A, 41B, or 41C that communicate with the sub board 30 are provided.

  The parent board 20 communicates with the first communication I / F 25 that communicates with the child board 30, the CPU 23 that is an arithmetic device, the memory 24 that is a storage device, and the personal computer (PC) 11 that is an external device. An I / F 22 and a system bus 21 are provided.

  The first communication I / F 25, the CPU 23, the memory 24, and the communication I / F 22 are connected via the system bus 21.

  The child board 30 includes a second communication I / F 33 that communicates with the parent board 20 and third communication I / Fs 37A, 37B that communicate with a plurality of grandchild boards 40A, 40B, and 40C that control different mechanisms. 37C, a CPU 32 that is an arithmetic device, a memory 35 that is a storage device, a print engine 36 that performs image processing, and a system bus 31.

  The second communication I / F 33, the third communication I / F 37 A, 37 B, 37 C, the CPU 32, the memory 35, and the print engine 36 are connected via the system bus 31.

  The grandchild substrate 40A controls, for example, a paper feeding mechanism that supplies a recording medium to the image forming unit. The grandchild substrate 40B controls, for example, a paper discharge mechanism that discharges a recording medium on which an image is formed. The grandchild substrate 40C controls, for example, a scanner mechanism that reads a document and supplies the read image data to the image forming unit.

  When the image forming apparatus 10 further includes a mechanism, the image forming apparatus 10 may further include a grandchild substrate that controls the mechanism. Also in this case, the additional grandchild board includes a communication I / F that communicates with the child board 30.

  The grandchild boards 40A, 40B, and 40C are fourth communication I / Fs 41A, 41B, and 41C that communicate with the child board 30, CPUs 42A, 42B, and 42C that are arithmetic devices, and memories 43A, 43B, and 43C that are storage devices. And system buses 44A, 44B, 44C.

  The fourth communication I / Fs 41A, 41B, 41C, the CPUs 42A, 42B, 42C and the memories 43A, 43B, 43C are connected via system buses 44A, 44B, 44C.

  Hereinafter, the first communication I / F 25, the second communication I / F 33, the third communication I / F 37A, 37B, 37C, and the fourth communication I / F 41A, 41B, 41C are collectively referred to as a communication I / F 41.

  FIG. 2 is a diagram illustrating a configuration of the communication interface 41. As shown in FIG. 2, the communication I / F 41 includes a transmission communication circuit 411 that transmits transmission data, a transmission FIFO 412 that temporarily stores transmission data and outputs transmission data stored in a first-in first-out manner, and a reception A reception communication circuit 415 that receives data, a reception FIFO 414 that temporarily stores the reception data and outputs the reception data stored on a first-in first-out basis, and is connected to the system bus 44 and is connected to the transmission FIFO 412 and the reception FIFO 414. A DMAC 413 for controlling the operation; and a reception FIFO connection circuit 416 for connecting the reception FIFOs 414 of different communication I / Fs.

  The reception FIFO connection circuit 416 controls whether or not to connect the reception FIFOs 414 of each board by a connection instruction signal transmitted from the CPU 23 of the parent board.

  FIG. 3 is a block diagram showing a configuration of the reception FIFO connection circuit 416A of the second communication I / F 33 provided in the slave board 30. As shown in FIG. In FIG. 3, the portion related to data transmission is omitted.

  As shown in FIG. 3, the reception FIFO connection circuit 416A receives the reception data from the reception communication circuit 415A, outputs the first selector 417A to the reception FIFO 414A, and the write instruction signal from the reception communication circuit 415A. Is input, and a delay circuit 421A that delays the write instruction signal from the reception communication circuit 415A.

  FIG. 4 is a block diagram showing a configuration of the reception FIFO connection circuit 416B of the first third communication I / F 37A provided in the slave board 30. As shown in FIG. In FIG. 4, the portion related to data transmission is omitted.

  As shown in FIG. 4, the reception FIFO coupling circuit 416B selects and switches the input signal from the reception data from the reception communication circuit 415B and the data output from the reception FIFO 414A, and outputs the selected signal to the reception FIFO 414B. 1 selector 417B, a second selector 418B that selects and switches an input signal from a write instruction signal from the reception communication circuit 415B and an output of the delay circuit 421A, and a write instruction signal from the reception communication circuit 415B A delay circuit 421B.

  FIG. 5 is a block diagram showing a configuration of a reception FIFO connection circuit 416C of the second third communication I / F 37B provided in the slave board 30. As shown in FIG. In FIG. 5, the portion related to data transmission is omitted.

  As shown in FIG. 5, the reception FIFO coupling circuit 416C selects and switches the input signal from the reception data from the reception communication circuit 415C and the data output from the reception FIFO 414B, and outputs the selected signal to the reception FIFO 414C. 1 selector 417C, a second selector 418B that selects and switches an input signal from a write instruction signal from the reception communication circuit 415C and an output of the delay circuit 421B, and a write instruction signal from the reception communication circuit 415C A delay circuit 421B.

  The operation of the communication interface according to the present embodiment will be described with reference to FIGS.

  The first selector 417A and the second selector 418A shown in FIG. 3 receive the FIFO connection instruction signal from the CPU 23 via the system bus 44.

  In this case, the first selector 417A is switched to output the received data to the reception FIFO 414A, and the second selector 418A is switched to output the write instruction signal to the FIFO to the reception FIFO 414B.

  The data signal is transmitted in the order of the reception communication circuit 415A → the first selector 417A → the reception FIFO 414A, and is output to the first selector 417B shown in FIG.

  The write instruction signal to the FIFO is output to the receiving communication circuit 415B shown in FIG. 4 via the second selector 418A → receiving FIFO 414A → DMAC 413A → system bus.

  Further, the write instruction signal to the FIFO is delayed by the delay circuit 421A and output to the second selector 418B shown in FIG.

  The read instruction signal for data once stored in the FIFO is output to the reception communication circuit 415B shown in FIG. 4 via DMAC 413A → reception FIFO 414A → DMAC 413A → system bus.

  Note that the operation of the reception FIFO connection circuit 416A is the same as that when there is a FIFO connection instruction signal even when there is no FIFO connection instruction signal.

  The first selector 417B and the second selector 418B shown in FIG. 4 receive a FIFO connection instruction signal from the CPU 23 via the system bus 44.

  In this case, the first selector 417B is switched to select the reception data output from the reception FIFO 414A shown in “B” of FIG. 4 and output it to the reception FIFO 414B, and the second selector 418B 4 is switched so as to select the FIFO write instruction signal output from the delay circuit 421A indicated by “C” and output it to the reception FIFO 414C.

  The data signal is transmitted in the order of reception FIFO 414A → first selector 417B → reception FIFO 414B, and is output to the first selector 417C shown in FIG.

  The write instruction signal to the FIFO is output to the reception communication circuit 415C shown in FIG. 5 via the delay circuit 421A → second selector 418B → reception FIFO 414B → DMAC 413B → system bus.

  The data read instruction signal once stored in the FIFO is output to the receiving communication circuit 415C shown in FIG. 5 via DMAC 413B → receiving FIFO 414B → DMAC 413B → system bus.

  Note that the operation of the reception FIFO connection circuit 416A is as follows. When there is no FIFO connection instruction signal, the first selector 417B selects the received data from the reception communication circuit 415B and the second selector 418B receives the input. The write instruction signal from the communication circuit 415B is selected.

  The first selector 417C and the second selector 418C shown in FIG. 5 receive the FIFO connection instruction signal from the CPU 23 via the system bus 44.

  In this case, the first selector 417C is switched to select the reception data output from the reception FIFO 414B indicated by “G” in FIG. 4 and output it to the reception FIFO 414C. The second selector 418C 4 is switched to select and output the write instruction signal to the FIFO output from the delay circuit 421B indicated by “F” in FIG.

  The data signal is transmitted in the order of reception FIFO 414B → first selector 417C → reception FIFO 414C, and is output to the memory 35 via the DMAC 413C shown in FIG.

  The write instruction signal to the FIFO is output from the delay circuit 421B → second selector 418C → receiving FIFO 414C.

  A data read instruction signal once stored in the FIFO is output from the DMAC 413C to the reception FIFO 414C.

  Note that the operation of the reception FIFO connection circuit 416B is as follows. When there is no FIFO connection instruction signal, the first selector 417C selects the reception data from the reception communication circuit 415C and the second selector 418C receives the input. The write instruction signal from the communication circuit 415C is selected.

  When the FIFO connection instruction signal is output from the CPU 23, the received data is stored in the reception FIFO 414A, read by the delayed read instruction signal, transmitted to the reception FIFO 414B, stored, and delayed read instruction It is read by the signal, stored in the receiving FIFO 414C, read by the delayed read instruction signal, and stored in the memory 35.

  The reception FIFO connection circuit transmits the reception data, the FIFO write instruction signal, and the FIFO read instruction signal delayed from the FIFO write signal to the reception FIFO of different communication I / Fs.

  Then, the reception FIFO connection circuit distributes and stores the received data in the reception FIFOs of the different communication I / Fs, reads out the distributed storage data in the order received, and outputs the received data to the memory.

  In the above-described embodiment, the case where the slave board 30 includes two communication I / Fs for connecting the grandchild boards has been described as an example, but the number of the communication I / Fs may be three or more.

  As described above, the communication interface of the present embodiment includes a transmission communication circuit 411 that transmits transmission data, a transmission FIFO 412 that temporarily stores transmission data and outputs transmission data stored in a first-in first-out manner, A reception communication circuit 415 that receives the reception data, a reception FIFO 414 that temporarily stores the reception data and outputs the reception data stored on a first-in first-out basis, and a transmission FIFO 412 and a reception FIFO 414 that are connected to the system bus 44. A first selector that selectively switches between input of received data from the reception FIFO 414 of the other communication I / F and input of received data from the reception communication circuit 415, and other Input of write instruction signal to FIFO from delay circuit of communication I / F and communication circuit 41 for reception A second selector for selecting and switching to the input of the write instruction signal to the FIFO from, includes a reception FIFO coupling circuit 416 for coupling the receiving FIFO414 different communication I / F, a.

  Therefore, even if the capacity of the reception FIFO is limited, there is an effect that the communication speed can be increased.

  Although several embodiments have been described, these embodiments have been presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalents thereof.

414A, 414B, 414C: Reception FIFO
417A, 417B, 417C: first selector 418A, 418B, 418C: second selector

Claims (5)

A transmission communication circuit for transmitting transmission data;
A transmission FIFO that temporarily stores transmission data and outputs the transmission data stored in first-in first-out;
A receiving communication circuit for receiving the received data;
A receiving FIFO that temporarily stores received data and outputs the received data stored in first-in first-out;
A DMAC connected to a system bus and controlling the operations of the transmission FIFO and the reception FIFO;
The reception data, the FIFO write instruction signal, and the FIFO read instruction signal obtained by delaying the FIFO write signal are transmitted to the reception FIFO of the different communication I / F, and the reception data is received for the reception of the different communication I / F. A FIFO connection circuit for receiving, which stores the received data in a FIFO in a distributed order, reads the received data stored in a distributed manner in the order received, and outputs the received data to a memory;
A communication interface comprising: The receiving FIFO coupling circuit is:
A first selector that selectively switches between input of the reception data from the reception FIFO of the different communication interface and input of the reception data from the reception communication circuit;
A second selector for selectively switching between the input of the FIFO write instruction signal from the delay circuit of the different communication interface and the input of the FIFO write instruction signal from the reception communication circuit;
The communication interface according to claim 1. The receiving FIFO connection circuit is
Sending received data, FIFO write instruction signal, and FIFO read instruction signal obtained by delaying the FIFO write signal to the reception FIFO of a different communication interface,
The received data is distributedly stored in the receiving FIFO of the different communication interfaces in the order received,
A communication method of reading out the received data stored in a distributed manner in the order received and outputting the read data to a memory. The receiving FIFO coupling circuit is:
A first selector that selectively switches between input of the reception data from the reception FIFO of the different communication interface and input of the reception data from the reception communication circuit;
A second selector for selectively switching between the input of the FIFO write instruction signal from the delay circuit of the different communication interface and the input of the FIFO write instruction signal from the reception communication circuit;
The communication method according to claim 3. An image forming unit for forming an image on a recording medium;
A paper feed mechanism for supplying the recording medium to the image forming unit;
A paper discharge mechanism for discharging the recording medium on which the image is formed by the image forming unit;
A master board having a first communication interface for performing communication;
A second communication interface that communicates with the parent substrate, and a child substrate that includes a third communication interface that communicates with a plurality of grandchild substrates that control different mechanisms;
A grandchild board comprising a fourth communication interface for communicating with the child board;
Provided on the daughter board,
A transmission communication circuit for transmitting transmission data;
A transmission FIFO that temporarily stores transmission data and outputs the transmission data stored in first-in first-out;
A receiving communication circuit for receiving the received data;
A receiving FIFO that temporarily stores received data and outputs the received data stored in first-in first-out;
A DMAC connected to a system bus and controlling the operations of the transmission FIFO and the reception FIFO;
The reception data, the FIFO write instruction signal, and the FIFO read instruction signal obtained by delaying the FIFO write signal are transmitted to the reception FIFO of the different communication I / F, and the reception data is received for the reception of the different communication I / F. A communication interface comprising: a FIFO coupling circuit for reception that stores the received data in a FIFO in a distributed order, reads the received data stored in a distributed manner in a received order, and outputs the received data to a memory;
An image forming apparatus comprising:

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