JP2016110400A - Arithmetic processing unit, and control method for arithmetic processing unit - Google Patents

Abstract

An arithmetic processing device and a control method for the arithmetic processing device that can further reduce power consumption by shortening the time required until the power is turned off and increasing the standby time are provided. Based on a register file holding data used for arithmetic processing and a pre-sleep instruction Sppd, the contents of the register file are saved to a non-volatile memory using empty register read access. A register save control unit 1 that executes a process of saving the contents of the register file 23 to the nonvolatile memory 33 based on a sleep instruction Spd received after the pre-sleep instruction. [Selection] Figure 3

Description

  The embodiments referred to in this specification relate to an arithmetic processing device and a control method for the arithmetic processing device.

  In the recent IoT (Internet of Things) era, for example, small electronic devices such as sensors are used in various places including smart meters. Under such circumstances, data processing such as sensing and recognition is preferably performed intermittently and with low power consumption in order to avoid frequent charging and battery replacement.

  In such a small electronic device, for example, when predetermined processing by the arithmetic processing unit (processor) is completed, the processing result (data) is stored in the nonvolatile memory (nonvolatile memory), the processor is turned off, and the standby is performed. (Standby: sleep) state is performed. In other words, normally-off technology for reducing power consumption by turning off the power of the processor is becoming important in battery-driven small electronic devices.

  By the way, conventionally, various types of arithmetic processing devices that can reduce power consumption have been proposed.

Japanese Patent Laid-Open No. 06-259163 JP 09-034599 A

  As described above, for example, in order to reduce the power consumption of the processor, a technique for reducing the power consumption is known in which the power is turned off during sleep (standby). Here, at the time of sleep, for example, information in the processor such as the contents of a register file (register) is saved in the nonvolatile memory.

  However, since the writing speed of the nonvolatile memory is slow, it takes a long time to turn off the power, and the standby time is shortened. Thus, when the standby time is shortened, the effect of reducing power consumption is reduced.

  In order to shorten the save time, for example, a method of increasing the bandwidth of the processor and the non-volatile memory, or a method of mounting them on the same semiconductor chip (LSI) is conceivable, but this increases the area and manufacturing cost. become. The subject of this invention is improving the low power effect by standby processing, without increasing a mounting area and manufacturing cost.

  According to one embodiment, an arithmetic processing device is provided that includes a register file that holds data used for arithmetic processing and a register save control unit.

  The register saving control unit saves the contents of the register file in a nonvolatile memory using an empty register read access based on a pre-sleep instruction, and based on a sleep instruction received after the pre-sleep instruction, A process of saving the contents of the register file in the nonvolatile memory is executed.

  The disclosed arithmetic processing device and the control method of the arithmetic processing device have an effect of further reducing power consumption by shortening the time required until the power is turned off and increasing the standby time.

FIG. 1 is a block diagram schematically illustrating an example of an arithmetic processing device. FIG. 2 is a diagram for schematically explaining a control method in an example of the arithmetic processing device. FIG. 3 is a block diagram schematically illustrating the arithmetic processing apparatus according to the present embodiment. FIG. 4 is a diagram for schematically explaining the control method of the arithmetic processing unit according to the present embodiment. FIG. 5 is a diagram (No. 1) for explaining an example of the control method of the arithmetic processing unit according to the embodiment. FIG. 6 is a diagram (No. 2) for explaining an example of the control method of the arithmetic processing unit according to the present embodiment. FIG. 7 is a diagram for explaining the effect of the control method of the arithmetic processing apparatus according to the present embodiment. FIG. 8 is a block diagram showing the main part of the first embodiment of the arithmetic processing unit. FIG. 9 is a block diagram illustrating an example of a read port selection unit in the arithmetic processing unit illustrated in FIG. FIG. 10 is a block diagram showing an example of a register read control unit in the arithmetic processing unit shown in FIG. FIG. 11 is a block diagram showing an example of the NVM store control unit in the arithmetic processing unit shown in FIG. FIG. 12 is a block diagram showing the main part of the second embodiment of the arithmetic processing unit. FIG. 13 is a flowchart for explaining an example of a save instruction insertion process in the arithmetic processing unit shown in FIG. FIG. 14 is a diagram for explaining the extension of the instruction format applied to the arithmetic processing unit shown in FIG. FIG. 15 is a block diagram showing the main part of a third embodiment of the arithmetic processing unit. FIG. 16 is a diagram for explaining an example of the save information table in the arithmetic processing unit shown in FIG. FIG. 17 is a block diagram illustrating an example of a read port selection unit in the arithmetic processing unit illustrated in FIG. FIG. 18 is a block diagram showing an example of the NVM store control unit in the arithmetic processing unit shown in FIG.

  First, before describing in detail the arithmetic processing device and the control method of the arithmetic processing device of the present embodiment, referring to FIG. 1 and FIG. 2, an example of the arithmetic processing device and the control method of the arithmetic processing device, and its problems Explain the point.

  FIG. 1 is a block diagram schematically illustrating an example of an arithmetic processing device, and illustrates an example of a VLIW processor (Very Long Instruction Word Processor) that performs pipeline processing. As will be described later, the application of the present embodiment is not limited to the VLIW processor, and it goes without saying that the present embodiment can also be applied to a scalar processor or the like.

  As shown in FIG. 1, a processor (arithmetic processing unit) 500 includes an instruction cache 21, a data cache 22, a register file (register) 23, and a nonvolatile memory controller 24. Five pipeline stages IF, ID, EX , MA, WB are executed.

  Here, IF indicates an instruction fetch stage, and the first (first) instruction held in the instruction cache 21 from the external instruction memory 31 is, for example, the first clock (of the program counter). Fetch at the first clock).

  ID indicates an instruction decode stage, and the first instruction is decoded (for example, a control signal is generated) at the second clock, and the register file 23 is referred to by a register specifier. In the second clock, the second instruction is fetched in the IF stage.

  EX indicates an instruction execution stage (EXecution), and the first instruction is executed at the third clock (for example, calculation such as numerical calculation, load / store data, or calculation of an address branch destination). . At the third clock, the third instruction is fetched in the IF stage, and the second instruction is decoded in the ID stage.

  MA indicates a memory access stage, and memory access is performed by the first instruction at the fourth clock. For example, processing such as writing data into the data cache 22 or writing data into both the data cache 22 and the external data memory 32 (write-through) is performed. At the fourth clock, the fourth instruction is fetched in the IF stage, the third instruction is decoded in the ID stage, and the second instruction is executed in the EX stage.

  WB indicates a stage for writing data back to the register (Write Back), and the result of the first instruction is written back to the register file 23 at the fifth clock. At the fifth clock, the fifth instruction is fetched in the IF stage, the fourth instruction is decoded in the ID stage, the third instruction is executed in the EX stage, and the third instruction is executed in the MA stage. Performs memory access by instruction.

  In FIG. 1, an example of five pipeline stages IF, ID, EX, MA, and WB is shown. However, this is merely an example, and different pipeline stages or different processing stages may be used. .

  In FIG. 1, reference numeral 31 is an instruction memory provided outside the processor 500, 32 is a data memory, and 33 is a non-volatile memory (non-volatile memory). The non-volatile memory (NVM) is for storing data when the power of the processor 500 is turned off and in a standby state in accordance with the non-volatile memory controller 24 in order to reduce power consumption, for example. It is memory.

  The processor 500 generally has, for example, a register file 23 that holds data being calculated, and a circuit that reads data from the register file 23 is provided with a selector having a register number of one.

  In addition, the pipeline processor 500 as shown in FIG. 1 often has a register bypass circuit for bypassing the execution result of the preceding instruction. In this case, the read port of the register file 23 is increased and the area is greatly increased. There is a tendency to increase.

  Here, for example, a flash memory or the like is used as the non-volatile memory 33. However, the writing process to the non-volatile memory 33 generally takes a longer time than the case of writing to an SRAM (Static Random Access Memory) or the like. Cost.

  Therefore, it takes a long time to save the contents of the register file 23 to the nonvolatile memory 33. For example, the standby time during which the power of the processor 500 can be turned off to reduce power is shortened, and the effect of reducing power consumption is reduced. . Although not shown, it goes without saying that what is saved in the nonvolatile memory 33 includes not only the contents of the register file 23 but also the contents (values) of various control registers, for example.

  FIG. 2 is a diagram for schematically explaining a control method in an example of the arithmetic processing device, and for explaining a data saving process at the time of power-down (sleep). In FIG. 2, the horizontal axis indicates time.

  As shown in FIG. 2, for example, when the sleep instruction (power down signal) Spd is given to the processor 500 in operation (execution) at the time Tpd, the nonvolatile memory controller 24 uses the total save period Psav. The contents of the register file 23 are saved in the nonvolatile memory 33.

  After the sleep period Pslp0 (after time Ts), when the sleep release (power-up signal) Spu is given at time Tpu, the data saved in the nonvolatile memory 33 is written back to the register file 23 in the return period Pret.

  Then, the processor 500 resumes the operation after the return period Pret. Note that the save and restore (write-back) processing of the contents of the register file 23 (control register) can be performed using, for example, a load / store instruction.

  Here, in order to write the contents of the register file 23 to the non-volatile memory 33 such as a flash memory, it takes a long time (the save period Psav) with respect to the sleep period Pslp0. The possible sleep period Pslp0 is shortened. As a result, the effect of reducing the power consumption by the sleep (power down) process for turning off the processor 500 is reduced.

  In order to shorten the save time, for example, it may be possible to increase the bandwidth of the processor 500 and the nonvolatile memory 33 or to be mounted on the same semiconductor chip. However, this increases the area and manufacturing cost. This is not preferable.

  Hereinafter, embodiments of an arithmetic processing device and a control method for the arithmetic processing device will be described in detail with reference to the accompanying drawings. FIG. 3 is a block diagram schematically illustrating an arithmetic processing apparatus according to the present embodiment, and illustrates an example of a VLIW processor that performs pipeline processing.

  The application of the present embodiment is not limited to the VLIW processor, and can be widely applied to a scalar processor (single scalar processor, superscalar processor) or the like.

  As is clear from the comparison between FIG. 3 and FIG. 1 described above, the arithmetic processing unit (processor) 600 of this embodiment is provided with the register saving control unit 1 for the processor 500 described with reference to FIG. It has become.

  Here, for example, the register saving control unit 1 receives a signal from the decode stage ID (decoder 42), gives a signal to the execution stage EX (execution unit 43), and receives a signal from the memory access stage MA (memory access unit 44). receive.

  Further, the register save control unit 1 exchanges signals between the register file (register) 23 and the nonvolatile memory controller 24, and controls data save and write back processing with the nonvolatile memory 33.

  Although not shown, it is needless to say that what is saved in the nonvolatile memory 33 includes not only the contents of the register file 23 but also the contents (values) of various control registers, for example. Details of the register save control unit 1 will be described later with reference to FIG.

  FIG. 4 is a diagram for schematically explaining the control method of the arithmetic processing unit according to the present embodiment, and is for explaining the data saving process at the time of power-down. In FIG. 4, the horizontal axis indicates time.

  As apparent from the comparison between FIG. 4 and FIG. 2 described above, in the control method of the arithmetic processing unit according to the present embodiment, the pre-sleep instruction is issued at time Tppd before the sleep instruction (power-down signal) Spd is given at time Tpd. (Prepower down signal) Sppd is given.

  Here, when the pre-sleep instruction Sppd is given, the contents of the register file 23 are saved in the nonvolatile memory 33 by using, for example, an empty register read access in the processor 600.

  As an empty register read access, for example, as will be described in detail later, for example, an instruction (NOP: No OPeration instruction) that is frequently used in the VLIW processor, for example, for the convenience of instruction scheduling can be used. .

  That is, if the pre-sleep instruction Sppd is given at the time Tppd before the sleep instruction Spd is given at the time Tpd, the saving from the register file 23 to the nonvolatile memory 33 is gradually performed during the execution of the processor 600 in the period Psav1. Done.

  Then, after the sleep instruction Spd is given at the time Tpd, for example, differential saving is performed in a period Psav2 described in detail later. This differential saving is rewritten (overwritten) by, for example, the contents (data) that could not be saved in the nonvolatile memory 33 in the period Psav1, or the operation of the processor 600 before the sleep instruction Spd was given at the time Tpd. Content.

  Here, since the differential save period Psav2 in FIG. 4 is normally sufficiently shorter than the total save period Psav in FIG. 2, according to the present embodiment, the sleep period Pslp0 in FIG. 2 is changed to the sleep period Pslp1 in FIG. Therefore, the power consumption can be reduced. The pre-sleep instruction Sppd can be given as a new command or a new external signal, for example.

  The processing after the sleep period Pslp1 is the same as that in FIG. 2. When the sleep cancellation instruction (power-up signal) Spu is given at time Tpu, the data saved in the nonvolatile memory 33 is restored in the return period Pret. Write back to the register file 23.

  Then, the processor 600 resumes the operation after the return period Pret. Note that the save and restore (write-back) processing of the contents of the register file 23 (control register) can be performed using, for example, a load / store instruction.

  Thus, according to the control method of the arithmetic processing unit according to the present embodiment, before the sleep instruction Spd is given at the time Tpd, the pre-sleep instruction Sppd is given at the time Tppd and the save process is started in advance. The sleep period Pslp1 can be lengthened. As a result, the effect of reducing power consumption can be further exhibited.

  5 and 6 are diagrams for explaining an example of the control method of the arithmetic processing unit according to the present embodiment. FIG. 5 is a diagram for explaining the saving process to the nonvolatile memory 33. 6 is for explaining the overwriting process after the saving process is performed.

  As shown in FIG. 5, when the processor (arithmetic processing unit) 600 is a VLIW processor, since a NOP instruction is usually used frequently, the contents of the register file (register) 23 are used by using the NOP instruction. It can be saved in the nonvolatile memory 33.

  In the example of FIG. 5, after the pre-sleep instruction Sppd is given, for example, the value of the register v0 is saved in the nonvolatile memory 33 using a NOP instruction (nop), and the save flag is rewritten to “1”. Further, after the NVM write time for writing the value of the register v0 to the nonvolatile memory 33, the value of the register v1 is saved to the nonvolatile memory 33 using the NOP instruction, and the save flag is rewritten to “1”.

  Note that the values of the registers v13 to v15 that have not been saved in time during the save period (Psav1) from the pre-sleep instruction Sppd to the sleep instruction Spd are saved in the nonvolatile memory 33 during the save period (Psav2) after the sleep instruction Spd. . Further, the save flags are all initialized to “0” when, for example, the pre-sleep instruction Sppd is given and the values of the registers v1 to v15 are written back (returned) from the nonvolatile memory 33.

  Further, as shown in FIG. 6, for example, the register v1 rewritten by the operation of the processor 600 between the pre-sleep instruction Sppd and the sleep instruction Spd rewrites the dirty flag (dirty) to “1”.

  That is, the value of the register v1 is saved in the non-volatile memory 33 in the period Psav1, but when the value is overwritten by the operation of the processor 600 before the sleep instruction Spd is given, the dirty flag is overwritten together with the overwriting of the register v1. Is rewritten to "1".

  Then, in the period (difference saving period) Psav2 after the sleep instruction Spd is given, by referring to the dirty flag “1”, the value of the register v1 is saved again in the nonvolatile memory 33 and rewritten (overwritten). )I do.

  Thereby, for example, the value of the register that could not be saved in the nonvolatile memory 33 in the period Psav1 and the value of the register rewritten by the operation of the processor 600 before the sleep instruction Spd is given are saved in the nonvolatile memory 33. Is possible.

  FIG. 7 is a diagram for explaining the effect of the control method of the arithmetic processing apparatus according to the present embodiment. Here, FIG. 7A shows a change in power consumption during the save process of the processor 500 shown in FIGS. 1 and 2, and FIG. 7B shows the processor of this embodiment shown in FIGS. A change in power consumption during 600 save processing is shown.

  As shown in FIG. 7B, according to the present embodiment, during the operation of the processor 600, the contents of the register file 23 are stored in the nonvolatile memory 33 by the pre-sleep instruction Sppd given before the sleep instruction Spd. Pre-evacuation (CP2 ′) is performed.

  Since the power CP2 ′ required for the advance saving is added to the power during operation (during execution) of the processor 600 during the period Psav1, it is preferable to increase the maximum power of the power source slightly correspondingly.

  Here, the electric power CP2 ′ required for the advance evacuation corresponds to a part CP2 of the electric power CP0 at the time of evacuation in FIG. Therefore, according to the present embodiment, the power CP3 obtained by subtracting the power CP1 at the time of differential saving and the power CP2 ′ required for the preliminary saving in FIG. 7 (b) from the power CP0 at the time of saving shown in FIG. 7 (a) is reduced. It becomes possible.

  For example, if the register value saved by the pre-sleep instruction Sppd is overwritten by the operating processor 600, the saving (writing) is performed again in the nonvolatile memory 33 at the time of saving the difference. Becomes smaller.

  However, for example, if 32 general registers are instructed to be saved at the end of the function and enter the standby state after returning from the function, there are few writes to the general registers at the end of the function. In most cases, saving is considered to be completed for most registers. Here, if the number of registers saved by differential saving is about 4, the time required to enter the standby state can be shortened to about 4/32 (= 1/8).

  FIG. 8 is a block diagram showing the main part of the first embodiment of the arithmetic processing unit, in which the processor (arithmetic processing unit) 600 automatically controls the saving process. That is, in the first embodiment, when an empty read port of the register file 23 is detected from the decoding result, the contents of the register (register file 23) are saved in the nonvolatile memory (nonvolatile memory) 33 using the empty port.

  As shown in FIG. 8, the register save control unit 1 includes a read port selection unit 11, a register read control unit 12, a table control unit 13, a save information table 14, an NVM store control unit 15, and a register number unit 16.

  Here, reference numeral 41 is an operation mode section, 42 is a decoder (decode stage ID), 43 is an execution section (execution stage EX), and 44 is a memory access section (memory access stage MA).

  The operation mode unit 41 is a register indicating whether the pre-save mode or the normal mode, and enters the pre-save mode when the pre-save is notified. Then, after the data of all the registers (register file 23) is saved or after returning from the sleep (standby) state, the normal mode is restored.

  The register number section 16 indicates the index of the register to be saved, is initialized when the pre-saving mode is entered, and is updated by the NVM store control section 15. The save information table 14 has a saved flag and a dirty flag for each element of the register file 23.

  Here, the initial values of the saved flag and dirty flag are “0”, and if the register is saved in the pre-save mode, the saved flag is “1”, and the register is written after saving. The dirty flag becomes “1”. Then, it is initialized to “0” after returning from sleep or when entering the pre-retraction mode.

  The decoder (ID stage) 42 includes four outputs of a register write index w-idx, a register write enable signal we, a register read index r-idx, and a register read enable signal re, and one input of a status signal status of the save information table. .

  The register write index w-idx and the enable signal we have the same number as the number of write ports of the register file 23, respectively. Similarly, on the read side, there are as many register read indexes r-idx and register read enable signals re as there are read ports in the register file 23, respectively.

  As the status signal of the save information table 14, assuming that the register save read port is 0th, the information of the save information table 14 corresponding to the 0th register read index r-idx [0] is passed as the status signal status. .

  The register file 23 reads the data data of the number of read ports from the read index r-idx and the read enable signal re. It should be noted that data bypass and interlock between pipeline stages are controlled by the register file 23.

  The effective section (EX stage) 43 is a stage that generally executes processing such as computation in the pipeline processor (600). The register saving control unit 1 passes data data used for executing the normal instruction read from the register file 23 to the effective unit 43.

  The memory access unit (MA stage) 44 is a stage that generally executes memory access processing in a pipeline processor. The register save control unit 1 receives data to be saved, an index idx, and a save enable signal enb from the memory access unit 44 using a register save instruction in a sleep mode (power down mode) in which power consumption is suppressed.

  The read port selection unit 11 searches for an empty read port from the register read enable signal re received from the decoder 42. In the pre-save mode, “1” is output to the read enable signal s-re [i] of the empty port i, and “0” is output otherwise.

  Further, “1” is output to the enable signal enb indicating that there is an empty port. If there is no empty port or the normal mode is not the pre-save mode, “0” is output to all the enable signals s-re and the signal enb.

  The register read control unit 12 passes to the register file 23 the save register number for the selected read port and the register read index number (r-idx) received from the decoder 42 for the other read ports. The same applies to the read enable signal re. Further, the register read control unit 12 selects data to be saved from the received data data and passes it to the NVM store control unit 15.

  The NVM store control unit 15 stores the data data received from the register read control unit 12 in the nonvolatile memory 33 in the advance save mode. In the normal mode, the data output from the MA stage (memory access unit 44) is stored in the nonvolatile memory 33 by the register save instruction.

  Here, when writing is performed in the advance save mode, the save information flag is set in the save information table 14 and the register number is incremented. When the final register write is completed, the operation mode is returned to the normal mode.

  The table control unit 13 receives the re-register write index w-idx and the enable signal we from the decoder 42, and sets the dirty flag (dirty) to “1” in the case of a saved register. Further, the saved flag is updated to “1” in accordance with the notification from the NVM store control unit 15.

FIG. 9 is a block diagram showing an example of the read port selection unit 11 in the arithmetic processing unit shown in FIG. As shown in FIG. 9, the read port selector 11 includes a selector 110, a plurality of inverters 111 _{0 to} 111 _n−1 , a plurality of AND gates 112 _{1 to} 112 _n−1 , 114, 115 _{0 to} 115 _n−1 , and OR gate 113 is included.

  For the read enable signal re [i], the read port selection unit 11 sets s-re [i] = 1 for the smallest i where re [i] = 0, and “0” otherwise. If i does not exist, enb = 0, and if i exists, enb = 1.

  However, when the operation mode is not the pre-save mode (pre) (normal mode: other), all output “0”. Note that the read port selection unit 11 shown in FIG. 9 is merely an example, and various modifications and changes can be made.

FIG. 10 is a block diagram showing an example of the register read control unit 12 in the arithmetic processing unit shown in FIG. As shown in FIG. 10, the register read control unit 12 includes a plurality of selectors 120 _{0 to} 120 _n−1 , a plurality of OR gates 121 _{1 to} 121 _n−1 , 123, and a plurality of AND gates 122 _{0 to} 122 _{n. Contains -1} .

  The register read control unit 12 selects a save register index (register number) based on the index s-re [i] of the i-th port selected by the read port selection unit 11, and receives the rest from the decoder 42. The read index r-idx [i] is selected.

  Further, the register read control unit 12 calculates the data data [i] (data [0] to data [n] of the register file 23 from the register index idx [i] (idx [0] to idx [n-1]) of the selection result. -1]).

Here, the read enable signal re [i] (re [0] to re [n-1]) of the register file 23 is output from the decoder 42 by the OR gates 121 _{1 to} 121 _n−1 . It is assumed that the logical sum of ~ re [n-1] and the output s-re [0] to s-re [n-1] of the read port selection unit 11 is obtained.

  Then, the register read control unit 12 extracts the data data of the i-th port from the read result and passes it to the NVM store control unit 15, and executes the register read results data [0] to data [n−1]. To pass. Note that the register read control unit 12 shown in FIG. 10 is merely an example, and it goes without saying that various modifications and changes are possible.

  FIG. 11 is a block diagram showing an example of the NVM store control unit 15 in the arithmetic processing unit shown in FIG. As illustrated in FIG. 11, the NVM store control unit 15 includes a write determination unit 151, an address calculation unit 152, an index update unit 153, and a plurality of selectors 154 to 156.

  In the pre-save mode (pre), the NVM store control unit 15 writes the data data passed from the register read control unit 12 to the address addr indicated by the register number in the nonvolatile memory 33 via the nonvolatile memory controller 24. .

  However, the save enable signal enb from the read port selector 11 is “0” (no usable read port), or the busy signal busy from the nonvolatile memory controller 24 is “1” (during writing to the nonvolatile memory 33). If so, cancel the writing process.

  In the normal mode (other), data is written to the nonvolatile memory 33 based on the data data, the register number idx, and the write enable signal enb passed from the memory access unit (MA stage) 44.

  Further, when the register value is written in the nonvolatile memory 33 in the pre-save mode (pre), the register number (idx) and the write signal (save = 1) are notified to the table control unit 13 and the saved flag is set to “ Update to 1 ”.

  The write determination unit 151 is notified of a signal enb = 0 (no usable read port) from the read port selection unit 11 or a signal busy = 1 (during writing to the nonvolatile memory 33) from the nonvolatile memory controller 24. If so, the output signal enb = 0 is output. In other cases, the output signal enb = 1 is output.

  The address calculation unit 152 calculates the address addr of the write destination nonvolatile memory 33 based on the register number idx from the register number unit 16 and outputs it to the selector 156. Here, for example, when the data size of the register is constant, it can be obtained by multiplying (actually shifting) the register number by the number of bytes. The index updating unit 153 increments the value of the register number idx from the register number unit 16 by “1”.

  First, the operation during sleep (standby, standby) will be described. When the sleep is notified, the contents of the register file 23 (control register) are basically saved in the nonvolatile memory 33 using a normal instruction. However, when saving the contents of the register file 23, it is preferable to add a function of referring to the save information table 14 and canceling the instruction when the save is completed and the dirty flag is “0”.

  Next, the operation when returning from sleep will be described. The return from sleep also returns data from the nonvolatile memory 33 to the register file 23 using a normal command. As a method for restoring (writing back) data in the nonvolatile memory 33, a special extended function is not required. Then, the register number in the register number section 16 and the data in the save information table 14 are initialized.

  FIG. 12 is a block diagram showing the main part of the second embodiment of the arithmetic processing unit, and shows what inserts a save instruction into a program (assembly program). As is clear from the comparison between FIG. 12 and FIG. 8 described above, in the second embodiment, the read port selection unit 11 in the first embodiment is omitted. In FIG. 12, it is assumed that the pre-sleep instruction Sppd (preliminary save) and the sleep instruction Spd are performed by commands.

  In the arithmetic processing unit of the second embodiment, the register save control unit 1 analyzes the program and inserts a register save instruction between the pre-save instruction (Sppd) and the sleep instruction (Spd). At this time, in consideration of the latency of the nonvolatile memory 33, register save instructions are inserted at appropriate intervals.

  FIG. 13 is a flowchart for explaining an example of a save instruction insertion process in the arithmetic processing unit shown in FIG. 12, and explains a process for inserting a register save instruction between a pre-save instruction and a sleep instruction in the assembly program. Is to do.

  Here, in the flowchart shown in FIG. 13, the input is an assembly program, and the output is also an assembly program. As a constraint condition, it is assumed that a pre-save instruction (an instruction corresponding to the pre-sleep instruction Sppd) and a sleep instruction (an instruction corresponding to the sleep instruction Spd) exist in the same basic block. Further, the basic block refers to a code portion that is executed straight in the flowchart without branching or merging.

  As shown in FIG. 13, when the insertion process of the save instruction in the assembly program is started, the lexical analysis is performed in step ST1, and then the process proceeds to step ST2 to perform intermediate expression processing of the compiler.

  Furthermore, it progresses to step ST3 and it is determined whether the unprocessed basic block exists. If it is determined in step ST3 that there is no unprocessed basic block, the process proceeds to step ST4, where assembly code is output and the process returns to the assembly program.

  On the other hand, if it is determined in step ST3 that an unprocessed basic block exists, the process proceeds to step ST5, where it is determined whether a pre-evacuation instruction exists. If it is determined in step ST5 that a pre-save instruction exists, the process proceeds to step ST6, where Inst = the instruction next to the pre-save instruction, and further, L = 0, and the process proceeds to step ST7, where Inst = sleep instruction is established. Determine whether or not.

  Here, for example, L considers the wait (wait) due to the write time (latency) of the non-volatile memory 33 in order to write (save) to the non-volatile memory 33 without waiting for the original program. Has been introduced.

  If it is determined in step ST7 that Inst = sleep instruction is not established, the process proceeds to step ST8, where it is determined whether an empty read port exists in the Inst instruction and L ≦ 0 is established.

  If it is determined in step ST5 that there is no pre-save command, and if it is determined in step ST7 that Inst = sleep command is established, the process returns to step ST3 and the above-described processing is repeated.

  If it is determined in step ST8 that an empty read port exists in the Inst instruction and L ≦ 0 is satisfied, the process proceeds to step ST9. Here, for example, in the case of a single scalar processor, the presence of an empty read port in step ST8 can be determined by whether or not the instruction uses all the read ports of the register file 23.

  Further, for example, in the case of a VLIW processor, an instruction (NOP: No OPeration) that does nothing is inserted for convenience of instruction scheduling. Therefore, the determination of the existence of an empty read port in step ST8 can be made, for example, in the case of a VLIW processor, that an empty read port exists when a NOP instruction exists.

  Then, in step ST9, a pre-save command is inserted, and the process proceeds to step ST10 as L = non-volatile memory 33 latency. Here, the insertion of the pre-save instruction in step ST9 is, for example, in the case of a single scalar processor, it is difficult to actually insert an instruction, so the instruction format is expanded, for example.

  That is, in the case of a single scalar processor, for example, a mode bit (save) indicating whether or not the register value is saved simultaneously with the execution of the instruction is added to the instruction. When a save instruction is inserted, the save mode bit is set to “1”.

  Further, for example, in the case of a VLIW processor, for example, by replacing the NOP instruction found in step ST8 with a save instruction, the advance save instruction insertion in step ST9 can be realized.

  On the other hand, if it is determined in step ST8 that there is an empty read port in the Inst instruction and at least one of L ≦ 0 is not established, the process proceeds to step ST11, and after L = L−1, the process proceeds to step ST10. . In step ST10, Inst = next instruction is set, the process returns to step ST7 and the above-described processing is repeated.

  Then, with respect to the basic block in which the pre-save instruction and the sleep instruction exist, the save instruction is inserted with an interval of the write latency to the nonvolatile memory 33 from the instruction next to the pre-save instruction to the instruction before the sleep instruction.

  14 is a diagram for explaining the extension of the instruction format applied to the arithmetic processing unit shown in FIG. 8, FIG. 14 (a) shows the instruction format before the extension, and FIG. 14 (b) shows the extension. The subsequent instruction format is shown. As is clear from a comparison between FIG. 14A and FIG. 14B, for example, a 1-mode bit (flag) sv is added to the expanded instruction format.

  If the mode bit sv is added to all instructions, the instruction space may become tight. Therefore, if there is not enough space in the instruction space, the instruction format is expanded only for a part of the instructions that have a vacant read port. It may be.

  Further, when the addition of the mode bit sv is limited to a part of the instructions, for example, when determining the empty read port in the above-described step ST8, the determination is made based on whether or not the instruction has the save mode bit.

  Next, the specification of the pre-save instruction is an instruction that does not take an operand, and the processor has a dedicated register (register for storing a register number) as in the first embodiment described with reference to FIGS. Number part) 16 is provided. The operation of the register number unit 16 is the same as that of the first embodiment.

  The data of the register file 23 indexed by the register number section 16 is read from the register file 23 and stored in the nonvolatile memory 33, and the register number is incremented.

  Here, for example, in the case of a single scalar processor, an unused port is fixed for an instruction in which the read port of the register file 23 is empty. Therefore, the save command uses a fixed free port.

  In the case of the VLIW processor, since a read port is assigned to each slot, the read port assigned to the slot into which the save instruction is inserted is used.

  FIG. 15 is a block diagram showing the main part of the third embodiment of the arithmetic processing unit, which corresponds to a mask function added to the first embodiment described above. As is apparent from the comparison between FIG. 15 and FIG. 8 described above, in the third embodiment, register information for masking (not performing pre-save) is stored in the save information table 14 of the first embodiment. For registers whose mask is “1”, pre-saving is not performed.

  That is, the mask information (mask signal, mask value m) stored in the save information table 14 is input to the read port selection unit 11 and the NVM store control unit 15 via the table control unit 13.

  Here, the mask value is set in the save information table 14 by a dedicated command (for example, set pre save mask immediate value). In the immediate value, each bit corresponds to each register. Further, when the number of registers is large and the instruction length exceeds, it can be divided into a plurality of instructions.

  FIG. 16 is a diagram for explaining an example of the save information table in the arithmetic processing unit shown in FIG. As shown in FIG. 16, in the arithmetic processing unit of the third embodiment, the save information table 14 is provided with a flag of a mask value m, for example.

  For example, the mask bit is set to “1” for the register v1 that is preferably not pre-saved. Note that the mask bit is set to “0” for the register v0 that performs the pre-save so that the above-described pre-save process is performed.

  Here, as the register (v1) in which the mask bit (m) in the save information table 14 is set to “1” and the advance save is not performed, for example, one that is frequently rewritten by the operation of the processor 600 is selected. .

  FIG. 17 is a block diagram illustrating an example of a read port selection unit in the arithmetic processing device illustrated in FIG. 15, and FIG. 18 is a block diagram illustrating an example of the NVM store control unit in the arithmetic processing device illustrated in FIG. The register saving control unit 1 will be described only with respect to the differences from the first embodiment described with reference to FIGS.

  As is clear from the comparison between FIG. 17 and FIG. 9 described above, the read port selection unit 11 in the third embodiment has an inverter 116 and an AND gate 117 added to that of the first embodiment.

The inverter 116 inverts the mask value m and supplies it to one input of the AND gate 117. The AND gate 117 performs a logical product of the output of the selector 110 given to the other input and the inverted mask value. And supplied to one input of AND gates 114, 115 _{0 to} 115 _n−1 .

  Thereby, even if the operation mode by the operation mode unit 41 is the pre-save mode, if the mask value m is “1”, the enable signal enb and the read enable signal s-re become “0”.

  As is clear from comparison between FIG. 18 and FIG. 11 described above, the NVM store control unit 15 in the third embodiment applies a mask value (mask information, mask information) to the write determination unit 151 from the table control unit 13 described above. Signal) m is input.

  In the third embodiment, the write determination unit 151 receives an enable signal enb from the read port selection unit, a busy signal from the nonvolatile memory controller 24, and a mask value m from the table control unit 13.

  The write determination unit 151 has an enable signal enb of “0” (no usable read port), a busy signal busy of “1” (busy state during writing), or a mask value m of “1” (masking). At this time, the output signal (enb) is set to “0”, otherwise it is set to “1”. However, when m = 1, in order to update the register number, a logical sum of the write determination (enb) and the mask value m signal is taken as the register number enable signal (enb).

  As described above, the registers whose mask value m is “1” are not saved in advance to the nonvolatile memory 33 even when the pre-sleep instruction Sppd is received, and are saved to the nonvolatile memory 33 after receiving the sleep instruction Spd. To start.

  In the above, it is preferable to set a register that is frequently rewritten by the operation of the processor 600 as a register to be masked (a register that does not perform pre-saving). That is, by rewriting the registers that are highly likely to be rewritten by the operation of the processor 600 from when the pre-sleep instruction Sppd is applied until when the sleep instruction Spd is applied, rewriting (overwriting) that occurs after the sleep instruction Spd is reduced. be able to.

  As a result, in the pre-save to the non-volatile memory 33 by the pre-sleep instruction Sppd, it is possible to reduce the number of rewrites by saving the register values that are unlikely to be rewritten, and as a result, further lower consumption Electricity can be expected.

  Here, the arithmetic processing apparatus of the third embodiment described with reference to FIGS. 15 to 18 applies the mask processing to the first embodiment of FIGS. Mask processing can also be applied to the second embodiment of FIG.

  In this case, for example, mask information (m) is stored in the save information table 14, and the mask value m is input to the register read control unit 12 and the NVM store control unit 15 via the table control unit 13.

  For example, for a register whose mask value m is “1”, the pre-save instruction Sppd is not saved in advance even if the pre-sleep instruction Sppd is received, and the register to the non-volatile memory 33 is received after receiving the sleep instruction Spd. Control to start evacuation.

  It should be noted that each of the above-described embodiments is merely an example, and it goes without saying that various changes and modifications can be made in the configuration and signal logic.

  Although the embodiment has been described above, all examples and conditions described herein are described for the purpose of helping understanding of the concept of the invention applied to the invention and the technology. It is not intended to limit the scope of the invention. Nor does such a description of the specification indicate an advantage or disadvantage of the invention. Although embodiments of the invention have been described in detail, it should be understood that various changes, substitutions and modifications can be made without departing from the spirit and scope of the invention.

Regarding the embodiment including the above examples, the following supplementary notes are further disclosed.
(Appendix 1)
A register file that holds the data to be used for arithmetic processing;
Based on the pre-sleep instruction, using the empty register read access, save the contents of the register file to the nonvolatile memory,
A register save control unit that executes a process of saving the contents of the register file in the nonvolatile memory based on a sleep instruction received after the pre-sleep instruction.
An arithmetic processing apparatus characterized by that.

(Appendix 2)
The register save control unit further includes:
Based on a sleep release instruction received after the sleep instruction, a process of writing back the contents saved in the nonvolatile memory to the register file is executed.
The arithmetic processing apparatus according to Supplementary Note 1, wherein:

(Appendix 3)
further,
A non-volatile memory controller for controlling the content of the register file to be saved in the non-volatile memory and writing back the content saved in the non-volatile memory to the register file;
The register save control unit performs control via the nonvolatile memory controller.
The arithmetic processing apparatus according to Supplementary Note 1 or Supplementary Note 2, wherein:

(Appendix 4)
The pre-sleep instruction is performed by an instruction or an external signal.
The arithmetic processing apparatus according to any one of Supplementary Note 1 to Supplementary Note 3, wherein

(Appendix 5)
The register save control unit
Control to save the contents of the register file that has not been saved by the save based on the pre-sleep instruction to the nonvolatile memory based on the sleep instruction;
The arithmetic processing apparatus according to any one of Supplementary Note 1 to Supplementary Note 4, wherein:

(Appendix 6)
The register save control unit
A save information table for holding save information saved in the nonvolatile memory;
A table control unit that rewrites the flag in the save information table corresponding to the location where the register file is rewritten when the register file is rewritten after the save to the nonvolatile memory; Including,
The arithmetic processing apparatus according to any one of Supplementary Note 1 to Supplementary Note 4, wherein:

(Appendix 7)
The register save control unit
Control the contents of the rewritten portion of the register file corresponding to the rewritten flag in the save information table to be saved again in the nonvolatile memory based on the sleep instruction;
The arithmetic processing apparatus according to appendix 6, wherein:

(Appendix 8)
The evacuation information table is
The pre-sleep instruction includes mask information that defines the contents of the register file that is not saved in the nonvolatile memory,
The register save control unit
Based on the sleep instruction, control to save the contents of the register file defined by the mask information in the nonvolatile memory,
The arithmetic processing apparatus according to appendix 6 or appendix 7, characterized in that.

(Appendix 9)
Saving the contents of the register file in the nonvolatile memory based on the pre-sleep instruction is performed using a NOP instruction in the arithmetic processing unit in operation.
The arithmetic processing apparatus according to any one of Supplementary Note 1 to Supplementary Note 8, wherein:

(Appendix 10)
The arithmetic processing unit includes:
Based on the sleep instruction, after saving the contents of the register file in the nonvolatile memory, until the sleep release instruction is received, the sleep mode with reduced power consumption is entered.
The arithmetic processing apparatus according to any one of Supplementary Note 1 to Supplementary Note 9, wherein:

(Appendix 11)
Based on the pre-sleep instruction, using empty register read access in the arithmetic processing unit in operation, the contents of the register file are saved in the nonvolatile memory,
Based on the sleep instruction received after the pre-sleep instruction, the content of the remaining register file that has not been saved in the nonvolatile memory is saved in the nonvolatile memory;
A control method for an arithmetic processing unit.

(Appendix 12)
further,
Based on the sleep release instruction received after the sleep instruction, the contents saved in the nonvolatile memory are written back to the register file.
The control method of the arithmetic processing unit according to appendix 11, wherein

(Appendix 13)
The contents of the register file saved in the nonvolatile memory based on the sleep instruction are:
In the save based on the pre-sleep instruction, the contents of the register file that has not been saved, or
The contents of the register file rewritten after the pre-sleep instruction.
The control method of the arithmetic processing device according to appendix 11 or appendix 12, characterized in that.

(Appendix 14)
further,
Based on the mask signal, the pre-sleep instruction defines the contents of the register file that is not saved in the nonvolatile memory,
Based on the sleep instruction, the contents of the register file defined by the mask signal are saved in the nonvolatile memory;
14. The method for controlling an arithmetic processing apparatus according to any one of supplementary note 11 to supplementary note 13, wherein the arithmetic processing apparatus is controlled.

(Appendix 15)
Saving the contents of the register file in the nonvolatile memory based on the pre-sleep instruction is performed using a NOP instruction in the arithmetic processing unit in operation.
The method for controlling an arithmetic processing apparatus according to any one of Supplementary Note 11 to Supplementary Note 14, wherein:

(Appendix 16)
The arithmetic processing unit includes:
Based on the sleep instruction, after saving the contents of the register file in the nonvolatile memory, until the sleep release instruction is received, the sleep mode with reduced power consumption is entered.
The method for controlling an arithmetic processing apparatus according to any one of Supplementary Note 11 to Supplementary Note 15, wherein:

DESCRIPTION OF SYMBOLS 1 Register save control part 11 Read port selection part 12 Register read control part 13 Table control part 14 Save information table 15 NVM store control part 16 Register number part 21 Instruction cache 22 Data cache 23 Register file (register)
24 Nonvolatile memory controller 31 Instruction memory 32 Data memory 33 Nonvolatile memory 41 Operation mode section 42 Decoder (decode stage ID, ID stage)
43 execution unit (execution stage EX, EX stage)
44 Memory Access Unit (Memory Access Stage MA, MA Stage)
500,600 arithmetic processing unit (processor)
Spd sleep instruction (power-down signal)
Sppd pre-sleep instruction (pre-power-down signal)
Spu Sleep release (power-up signal)

Claims (9)

A register file that holds the data to be used for arithmetic processing;
Based on the pre-sleep instruction, using the empty register read access, save the contents of the register file to the nonvolatile memory,
A register save control unit that executes a process of saving the contents of the register file in the nonvolatile memory based on a sleep instruction received after the pre-sleep instruction.
An arithmetic processing apparatus characterized by that. The register save control unit further includes:
Based on a sleep release instruction received after the sleep instruction, a process of writing back the contents saved in the nonvolatile memory to the register file is executed.
The arithmetic processing apparatus according to claim 1. The register save control unit
A save information table for holding save information saved in the nonvolatile memory;
A table control unit that rewrites the flag in the save information table corresponding to the location where the register file is rewritten when the register file is rewritten after the save to the nonvolatile memory; Including,
The arithmetic processing device according to claim 1 or 2, wherein The register save control unit
Control the contents of the rewritten portion of the register file corresponding to the rewritten flag in the save information table to be saved again in the nonvolatile memory based on the sleep instruction;
The arithmetic processing device according to claim 3. The evacuation information table is
The pre-sleep instruction includes mask information that defines the contents of the register file that is not saved in the nonvolatile memory,
The register save control unit
Based on the sleep instruction, control to save the contents of the register file defined by the mask information in the nonvolatile memory,
The arithmetic processing apparatus according to claim 3 or 4, wherein Based on the pre-sleep instruction, using empty register read access in the arithmetic processing unit in operation, the contents of the register file are saved in the nonvolatile memory,
Based on the sleep instruction received after the pre-sleep instruction, the content of the remaining register file that has not been saved in the nonvolatile memory is saved in the nonvolatile memory;
A control method for an arithmetic processing unit. further,
Based on the sleep release instruction received after the sleep instruction, the contents saved in the nonvolatile memory are written back to the register file.
The method of controlling an arithmetic processing unit according to claim 6. The contents of the register file saved in the nonvolatile memory based on the sleep instruction are:
In the save based on the pre-sleep instruction, the contents of the register file that has not been saved, or
The contents of the register file rewritten after the pre-sleep instruction.
The method for controlling an arithmetic processing apparatus according to claim 6 or 7, wherein: further,
Based on the mask signal, the pre-sleep instruction defines the contents of the register file that is not saved in the nonvolatile memory,
Based on the sleep instruction, the contents of the register file defined by the mask signal are saved in the nonvolatile memory;
The method for controlling an arithmetic processing apparatus according to any one of claims 6 to 8, wherein:

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