JP2500938B2 - Semiconductor device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to an improvement in the dielectric breakdown withstand capacity of a gate insulating film in an insulated gate semiconductor device such as a power MOSFET or an insulated gate bipolar transistor. is there.

[Prior Art] FIG. 3 is a sectional view showing a structure of a power MOSFET element 1a. In the figure, an N ⁻ layer 3 is formed on one main surface of the N ⁺ layer 2 by epitaxial growth to form a semiconductor vapor plate. The P region 4 is formed by the double diffusion method in which the impurities are selectively diffused from the surface of the N ⁻ layer 3 in two steps, and the impurities are selectively diffused from the surface of the P region 4 to form P region 4. Two N ⁺ regions 5 are formed in the region 4 at regular intervals. Furthermore, from the surface of the N ⁻ layer 3 to each N ⁺ region 5
An insulating layer 6 made up of a gate insulating film 6a and an interlayer insulating film 6b is formed over a part of the surface of the above, and a gate electrode 7 made of, for example, polysilicon is formed in each insulating layer 6. A source electrode 8 made of Al or the like is formed so as to be electrically connected to both the P region 4 and the N ⁺ region 5. A drain electrode 9 made of metal is formed on the back surface of the N ⁺ semiconductor substrate 2.

Next, the operation of this power MOSFET element 1a will be described. The drain electrode 9 of the power MOSFET element 1a shown in FIG.
With a constant drain voltage V _DS applied between the gate electrode 7 and the source electrode 8, the power MO between the gate electrode 7 and the source electrode 8 is increased.
When a gate voltage V _GS that is equal to or higher than the threshold voltage V _{T of the} SFET is applied, a channel is formed in a region corresponding to the gate electrode 7 and narrowed between the N ⁻ layer 3 and the N ⁺ region 5 in the P region 4. As a result, a drain current flows between the drain electrode 9 and the source electrode 8. Therefore, the drain current can be controlled by controlling the gate voltage V _GS .

In recent years, the performance of power MOSFET devices has dramatically improved, and for example, the ON resistance, which was a drawback of power MOSFET devices,
A power MOSFET device reduced to about 0.03Ω and a power WOSFET device with a drain voltage of 900 to 1000V have been put to practical use.

[Problems to be Solved by the Invention]

The power MOSFET element 1a, which is a conventional semiconductor device, is configured as described above, and is connected to the peripheral circuit in the actual use state as shown in FIG. Ie power
A power supply E and a load Z are connected in series between the source electrode 8 and the drain electrode 9 of the MOSFET element 1a, while the gate electrode 7
Is connected to the driver circuit D via a resistor Rg.

By the way, in the equivalent circuit state shown in FIG.
When the element 1a is operated at a high speed, a rush voltage A as shown by a solid line in FIG. 5 is generated between the gate electrode 7 and the source electrode 8 as well known in the art. As a result, the insulating layer 6 between the gate electrode 7 and the source electrode 8 may be broken down. In order to prevent this, it is conceivable to set the value of the resistance Rg to a large value to suppress the inrush voltage to a low level. The voltage changes as shown by the dashed line B in FIG. 5, the switching timing becomes long, and the high-speed operability of the power MOSFET element 1a is impaired.

In addition, the insulating layer 6 may be momentarily broken between the gate electrode 7 and the source electrode 8 as soon as a driving device such as a motor that is the load Z is turned off. This is because a certain amount or more of electrostatic charge is accumulated in the insulating layer 6 between the gate electrode 7 and the source electrode 8, and that amount is the dielectric breakdown withstand amount between the gate electrode 7 and the source electrode 8 (hereinafter referred to as “GS insulation”). This is because the "breakdown tolerance") is exceeded.

Therefore, in order to prevent the breakdown of the insulating layer 6 between the gate electrode 7 and the source electrode 8, it is desired to improve the GS breakdown resistance.

Here, this GS dielectric breakdown withstand capacity greatly depends particularly on the thickness of the gate insulating film 6a. Because usually the gate insulation layer
The thickness of 6a is considerably smaller than the thickness of the interlayer insulating film 6b.
This is because the a and the interlayer insulating film 6b are about 1000 Å and 10000 Å, respectively, so that in the above case, the thin gate insulating film 6a is destroyed first. Therefore, from the viewpoint of improving the GS breakdown resistance, it is preferable to increase the thickness of the gate insulating film 6a.

However, in recent years, a device capable of controlling a power MOSFET element at a low voltage has been developed, and the gate insulating film 6a has been formed to be thin accordingly, which causes a problem that the GS breakdown resistance is lowered. . Especially power MO
When manufacturing a high-value-added module product that incorporates SFET elements and other bipolar transistors in the same package, as described above, the GS breakdown resistance decreases with the thickness reduction of the gate insulating film, When a failure occurs in the power MOSFET element, not only the problem that the power MOSFET element becomes unusable but also the entire module product including this power MOSFET element becomes unusable and the yield of the module product decreases. There is a problem.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device having a large GS breakdown resistance and high reliability.

[Means for solving the problem]

According to the present invention, the first electrode and the control electrode are formed on one surface through the insulating layer, while the second electrode is formed on the other surface, and the first and second electrodes are formed by the potential applied to the control electrode.
The object is an insulated gate semiconductor device in which conduction / non-conduction between electrodes is controlled. The semiconductor device of the present invention includes a control electrode bonding pad that is provided on one surface side and is electrically connected to the control electrode, and between the first electrode and the control electrode bonding pad that is provided on the one surface side. An electrically connected resistor and a first conductivity type island-shaped region which is formed on one surface by diffusion in a region of the semiconductor upper layer portion below the control electrode bonding pad and electrically connected to the first electrode. And a second conductive type polysilicon layer formed in contact with a part of the surface of the island region and electrically connected to the control electrode bonding pad. Here, the island region and the polysilicon formed in contact therewith form a diode, and the diode and the resistor form a discharge circuit for discharging the charge accumulated in the insulating layer.

[Action]

In the semiconductor device according to the present invention, the resistor and the diode are electrically connected together between the first electrode and the control electrode bonding pad, that is, between the first electrode and the control electrode. The charge accumulated in the insulating layer is rapidly discharged by the function of the discharge circuit including the diode, and the dielectric strength between the first electrode and the control electrode is improved. In this case, the diode forming the discharge circuit is the first
Since it is composed of the conductive type island region and the second conductive type polysilicon layer formed in contact therewith, the junction portion of this diode can be formed shallowly. Therefore, the influence of the parasitic circuit due to the existence of this diode is reduced,
The avalanche resistance of the semiconductor device can be increased.
Further, since the diode forming the discharge circuit is formed of the polysilicon layer, the breakdown voltage of the diode can be easily adjusted by adjusting the resistance value of the polysilicon layer or the like. Furthermore, since the diode that constitutes the discharge circuit is composed of the island-shaped region formed by diffusion in the region including the lower portion of the bonding pad for the control electrode, the accuracy of the diode in terms of design placement and processing is improved. The electrode can be taken out easily, and the manufacturing process can be simplified by utilizing a part of the island-shaped region to be formed below the control electrode bonding pad as a diode.

〔Example〕

FIG. 1 is a sectional view showing an embodiment of a semiconductor device according to the present invention. As shown in the figure, in actual use, a plurality of power MOSFET elements 1a are provided on the semiconductor substrate, and the plurality of power MOSFET elements 1a are connected in parallel by the source electrode layer 80 to form one power MOSFET 1.

Also, a bonding pad is provided at an appropriate position and electrically connected to an appropriate portion of the power MOSFET 1. That is, the island-shaped P region 10 is formed in a part of the upper layer portion of the N ⁻ layer 3, and the gate bonding pad 11 is formed on the P region 10 via the insulating layer 6. Here, the reason why the P region 10 is provided in the N ⁻ layer 3 corresponding to the gate bonding pad 11 is that the electric field concentration is relaxed in the region a in FIG. 1 and that damage to the power MOSFET 1 during the bonding process is caused. This is to reduce it. Then, the gate bonding pad 11 and each gate electrode 7 are electrically connected by a wiring means (not shown), and the gate bonding pad 11 and the lead frame (not shown) are made of aluminum thin wire or the like in the wire bonding step. It is electrically connected by a bonding wire (not shown), and these gate bonding pad 11, bonding wire,
An appropriate electric potential is externally supplied to the gate electrode 7 via the lead frame and the wiring means.

Further, a source bonding region (not shown) is provided at an appropriate position of the source electrode layer 80, and in the wire bonding process, the source bonding region and the lead frame (not shown) are bonded with a bonding wire (not shown) such as an aluminum thin wire. It is electrically connected by. Then, an appropriate electric potential is externally supplied to both the P region 4 and the N ⁺ region 5 via the source electrode layer 80, the bonding wire and the lead frame.

Further, an N-type polysilicon layer 13 is formed on a part of the surface region of the P region 10 and is electrically connected to the gate bonding pad 11 via the contact hole 14. Although not shown in the figure, the P region 10 is electrically connected to the source electrode layer 80 through a contact hole provided at a predetermined position of the insulating layer 6.

Further, a resistor 15 made of polysilicon or the like is provided on the insulating layer 6 located on the P region 10, and one end of the low antibody 15 and the bonding pad 11 for gate are electrically connected, and The other end of the resistor 15 and the source electrode layer 80 are electrically connected. As a result, the gate bonding pad 11 and the source electrode layer 80 are electrically connected via the resistor 15.

FIG. 2 is a circuit diagram showing an equivalent circuit of FIG. In the figure, 16 is N ⁺ layer 2, N ^- layer 3, P region 4, N ⁺ region 5, insulating layer 6,
A power MOSFET composed of a gate electrode 7, a source electrode layer 80 and a drain electrode 9, and 17 is N-type polysilicon.
It is a diode composed of 13 and P region 10.

Since the diode 17 is connected between the gate electrode 7 and the source electrode layer 80 of the power MOSFET 1 as described above, the diode 17 functions as a clamp diode, and an excessive voltage is applied to the insulating layer 6 as is well known in the art. This prevents the insulation layer 6 from being applied and prevents dielectric breakdown of the insulating layer 6. On this occasion,
Since the diode 17 is formed of the polysilicon layer 13, the junction of the diode 17 can be formed extremely shallow just below the polysilicon layer 13 in the P region 10. Therefore, the influence of the parasitic circuit due to the presence of the diode 17 can be reduced, the withstand voltage value between the source electrode 80 and the drain electrode 9 can be increased, and the avalanche withstand capability of the power MOSFET 1 can be increased. Furthermore, since the diode 17 is formed from the polysilicon layer 13, it is possible to easily adjust the resistance value by patterning the polysilicon layer 13 and adjusting the injection amount into the polysilicon layer 13, and thereby the withstand voltage of the diode 17 is increased. It can be easily adjusted.

In addition, since the positive charge accumulated in the insulating layer 6 flows from the gate electrode 7 to the source electrode layer 80 via the resistor 15 and is discharged, the insulating layer 6 is prevented from being broken, and GS
The dielectric strength is increased, and the reliability of the power MOSFET 16 is improved.

In the above embodiment, as shown in FIG. 2, the case where the diode 17 and the resistor 15 are electrically connected between the gate electrode 7 and the source electrode layer 80 has been described, but only the resistor 15 is connected to the gate electrode. Needless to say, even when the 7-source electrode layer 80 is electrically connected, the charge accumulated in the insulating layer 6 is discharged through the resistor 15 in the same manner as described above, and sufficient prevention of the broken line of the insulating layer 6 can be obtained. .

In the above embodiment, the gate bonding pad 11
The diode 17 composed of the low antibody 15, the N-type polysilicon 13 and the P region 10 is provided in the vicinity, but the positions where the resistor 15 and the diode 17 are provided are not limited to this, and the point is appropriate. A resistor and a diode may be provided at different positions, and a parallel body of the resistor and the diode may be electrically connected between the gate electrode 7 and the source electrode 80 as shown in FIG.

Further, although the case of the N-channel power MOSFET 1 has been described in the above embodiment, the present invention is applicable to the P-channel power MO.
It can also be applied to SFET.

Further, although the power MOSFET has been described in the above embodiments, the present invention can be applied to other insulated gate type semiconductor devices, for example, an insulated gate type bipolar transistor. The dielectric breakdown resistance can be improved.

〔The invention's effect〕

As described above, according to the present invention, since the resistor and the diode are electrically connected together between the first electrode and the control electrode, insulation is achieved by the action of the discharge circuit including the resistor and the diode. The charge accumulated in the layer can be promptly discharged, the dielectric strength between the first electrode and the control electrode can be improved, and the reliability thereof can be increased. In this case, since the diode forming the discharge circuit is composed of the first conductivity type island-shaped region and the second conductivity type polysilicon layer formed in contact therewith, the junction portion of the diode is formed. Can be formed shallowly. Therefore, the influence of the parasitic circuit due to the presence of this diode can be reduced, and the avalanche withstand capability of the semiconductor device can be increased, without impairing its reliability. Further, since the diode forming the discharge circuit is formed of the polysilicon layer, the breakdown voltage of the diode can be easily adjusted by adjusting the resistance value of the polysilicon layer. Furthermore, since the diode that constitutes the discharge circuit is composed of the island-shaped region for the control electrode bonding pad, it becomes easy to pull out the electrode of this diode, and
By using a part of this island region as a diode, the manufacturing process can be simplified.

[Brief description of drawings]

FIG. 1 shows a power MOSF which is a semiconductor device according to the present invention.
FIG. 2 is a sectional view showing an ET, FIG. 2 is a circuit diagram showing a partial equivalent circuit of FIG. 1, and FIG. 3 is a sectional view showing a power MOSFET element.
FIG. 5 is an equivalent circuit diagram showing a usage example of a conventional semiconductor device.
The figure shows the voltage change between the gate and source electrodes with respect to time. In the figure, 6 is an insulating layer, 7 is a gate electrode, 9 is a collector electrode, 15 is a resistor, and 80 is a source electrode layer. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Claims] 1. A first electrode and a control electrode are formed on one surface through an insulating layer, while a second electrode is formed on the other surface, and the first electrode is formed by a potential applied to the control electrode. And an insulating gate type semiconductor device in which conduction / non-conduction between the second electrodes is controlled, the control electrode bonding pad being provided on the one surface side and electrically connected to the control electrode. A resistor provided on the one side and electrically connected between the first electrode and the control electrode bonding pad; and below the control electrode bonding pad in the semiconductor upper layer portion on the one side. A first conductive type island region that is formed in the region by diffusion and electrically connected to the first electrode; and a control electrode that is formed in contact with a part of the surface of the island region. for A second conductive type polysilicon layer electrically connected to the bonding pad, wherein the island-shaped region and the polysilicon layer formed in contact with the island-shaped region form a diode; A semiconductor device in which the resistor and the resistor form a discharge circuit for discharging a charge accumulated in the insulating layer.