JP2503283B2 - Semiconductor integrated circuit - Google Patents

Description

Detailed Description of the Invention 【Overview】

A semiconductor integrated circuit having three or more wiring layers is provided for the purpose of making it less susceptible to noise from a macro cell through which a relatively large current flows without increasing the number of power supply lines in the second wiring layer. A first wiring layer, a second wiring layer and a second wiring layer on the semiconductor substrate on which a plurality of basic cells including transistors are arranged.
A wiring layer and a third wiring layer are laminated via an insulating layer, and power supply lines are arranged in the first wiring layer and the third wiring layer along the longitudinal direction of the basic cell row formed on the semiconductor substrate. Is
In a semiconductor integrated circuit in which power supply lines are arranged in the second wiring layer at intervals of several basic cells in a direction perpendicular to the longitudinal direction of the basic cell row, the basic cells are connected by wiring. As a component of a macro cell having a certain function,
An interlayer contact and a wiring connecting the power supply line of the first wiring layer and the power supply line of the third wiring layer via the interlayer contact are provided.

[Industrial applications]

The present invention relates to a semiconductor integrated circuit having three or more wiring layers.

[Prior art]

In some semiconductor integrated circuits, a wiring layer is provided on a semiconductor substrate on which a plurality of basic cells including transistors are arranged to form a desired circuit. For example, in a gate array, a semiconductor maker pre-manufactures and prepares a large number of master chips in which basic cells composed of 4 to 8 transistors are arranged in a matrix, and wiring is performed based on user-specified specifications. A desired logic LSI is formed, and the logic LSI can be provided at a low price and in a short delivery time, which is suitable for small-quantity, high-mix production. The wiring of the gate array is determined in the following order. (1) Determine input / output peripheral circuits and power supply lines in the chip. (2) Determine the contacts that connect the power supply lines of the adjacent layers. (3) Determine the layout of logic circuits such as macro cells. (4) Determine wiring between logic circuits such as macro cells. Among the above wirings, the power supply line and its interlayer contact are predetermined by the semiconductor manufacturer side according to the type of the master chip, and it is not possible to arrange the power supply line according to the logic circuit after the logic circuit is formed. Can not. FIG. 4 shows the arrangement and connection of power supply lines in the gate array. This gate array is a basic cell with the same configuration.
Basic cell rows 11, 12, and 13 made of BC are arranged in parallel at regular intervals, and a large number of input / output interface cells 20 are arranged around them. A plurality of bonding wire pads (not shown) are arranged on the outer periphery of the input / output interface cell 20 between the basic cell rows as a wiring channel region. Above the semiconductor substrate, there are three wiring layers with an insulating layer in between. Of these, the first wiring layer closest to the semiconductor substrate is
A pair of power supply lines VD11 and VS11 (ground lines) and power supply lines along the longitudinal direction of the basic cell rows 11, 12, and 13, respectively.
VD12 and VS12 (ground line), power supply lines VD13 and VS13
(Ground line) is arranged. The mark ● shown on these power supply lines is a contact A for connecting the semiconductor substrate portion and the wiring of the first wiring layer. In the second wiring layer above the first wiring layer, a power supply line VS21 is provided at intervals of several basic cells in a direction perpendicular to the longitudinal direction of the basic cell rows 11, 12, 13.
(Ground line), VD21, VS22 (ground line), VD22 are arranged. These power supply lines VS21, VD21, VS22, VD22 and power supply lines VD11, VS11, VD12, VS12, VD13, VS13 are
At the intersecting portion, the layers are interconnected by an interlayer contact B indicated by a circle. In the third wiring layer above the second wiring layer, similarly to the power supply line of the first wiring layer, a pair of power supply lines VD31 and VS31 (ground line), power supply line VD32 and
VS32 (ground line), power supply lines VD33 and VS33 (ground line) are arranged. These power supply lines VD31, VS31, VD
32, VS32, VD33, VS33 are the first-layer power supply lines VD11, VS
11, VD12, VS12, VD13, and VS13 are arranged immediately above or in the vicinity thereof. The power supply lines VD31, VS31, VD32, VS32 and the power supply lines VD21, VS21, VD22, VS22, VD23, VS23 are interconnected at an intersection by an interlayer contact C indicated by a double circle. FIG. 6 shows a connection state between macro cells for forming a dedicated LSI. In the figure, shaded MS1 to MS10 are macrocells having a certain function, which are formed by connecting the basic cells BC by wiring. FIG. 5 shows a buffer macro cell formed by connecting the basic cells BC1 to BC4 having the same structure by wiring. Each of the basic cells BC1 to BC4 has two PMOSFETs and two NMOs.
It consists of SFET. In the figure, D and S indicated by dotted lines are a drain region and a source region, respectively, and G indicated by a dotted line is a gate electrode. This buffer macro cell is a basic cell BC
A CMOS inverter is formed by 1, and at the output of this inverter are 6 parallel-connected CMOS formed by basic cells BC2 to BC4.
The input of the inverter is connected. Second layer signal line 31
When (IN) is set to the low level, the first layer signal line 33 is set to the high level, and the plurality of driven logic circuits (not shown) connected in parallel to the second layer signal lines 37 and 38 and the first layer signal line are connected. A relatively large current flows into the power supply line VS1 through the contacts Ai3 and Ai4 between D and S of the NMOSFETs of the basic cells BCi (i = 2 to 4) 36 and 35. Further, when the second layer signal line 31 is set to the high level, the first layer signal line 33 is set to the low level and the power supply line VD1
To contacts Ai1, Ai2 (i = 2-4), basic cell BCi
A relatively large current flows into the driven logic circuit through the first-layer signal lines 34 and 36 and the second-layer signal lines 37 and 38 between S and D of the PMOSFET.

[Problems to be Solved by the Invention]

The power supply line of the second wiring layer does not pass on this buffer macro cell, and the buffer macro cell is connected from the connection point (intersection) between the power supply lines VS1 and VS3 and the connection point between the power supply lines VD1 and VD3. is seperated. Therefore, when the buffer macro cell is driven, the power supply line of the first wiring layer is easily affected by noise. To avoid this, if a large number of power supply lines are arranged in the second wiring layer, the number of signal channels in the second wiring layer is reduced, the utilization rate of the basic cells BC is deteriorated, and high integration is hindered. In view of such a problem, an object of the present invention is to make it less susceptible to noise from a macro cell in which a relatively large current flows without increasing the number of power supply lines in the second wiring layer.

FIG. 1 shows the principle configuration of the present invention. On a semiconductor substrate on which a plurality of columns of basic cells including transistors are arranged, from the semiconductor substrate side, a first wiring layer,
The second wiring layer and the third wiring layer are laminated via an insulating layer. In the first wiring layer and the third wiring layer, power supply lines VD1 and VD1, VD1 are provided along the longitudinal direction of the basic cell row formed in the bulk.
S1 and VD3, VS3 are arranged. In addition, in the second wiring layer, the power supply line VD is provided in the direction perpendicular to the longitudinal direction of the basic cell row.
2, VS2 are arranged at intervals of several basic cells. The arrangement of these power supply lines and the interlayer contacts connecting the power supply lines of the adjacent layers are predetermined, and the user cannot change them. The macro cell MS having a certain function, which is formed by connecting the basic cells with a wiring, includes the interlayer contacts B1 and C1 (B2, C2) and the interlayer contacts B1 and C1 (B2, C) as its constituent elements.
Wirings 11, 21 for connecting the power supply line VD1 (VS1) of the first wiring layer and the power supply line VD3 (VS3) of the third wiring layer via 2)
(12, 22) and.

[Action]

Since the power supply line of the second wiring layer is usually arranged every several basic cells, the second wiring layer does not always exist on the macro cell MS. Therefore, some buffer macrocells, flip-flops, adders, etc. through which a relatively large current flows are not interconnected on the macrocell MS between the power supply lines VD1 and VD3 and between the power supply lines VS1 and VS3. . However, in the present invention, since the macro cell MS has the wiring and the interlayer contact that connect between the power supply lines of the first and third wiring layers as its constituent elements, the current flowing through the power supply line of the first wiring layer is large. The density is significantly lower than in the past and the power supply voltage is stabilized. Therefore, it is possible to reduce the influence of noise generated from the macro cell in which a relatively large current flows on the power supply line. In other words, it is possible to supply power according to the layout of the logic circuit ((3) in the column of the related art) even after the layout of the power supply lines is determined (after (1) and (2) in the column). Becomes Generally, the widths of the power supply lines VD3 and VS3 of the third wiring layer, which have larger irregularities than the first wiring layer, are equal to the width of the power supply line VD of the first wiring layer.
Since the width is larger than the width of 1 and VS1, the above-mentioned effect by connecting the power supply lines of the first and third wiring layers is large. In addition, it is not necessary to dispose a large number of power supply lines in the second wiring layer, and the number of signal channels is increased accordingly, and high integration is possible.

【Example】

An embodiment of the present invention will be described below with reference to the drawings. The layout of the basic cell BC, the input / output interface cell 20, and the power supply line, which are common configurations of the gate array, is the same as that shown in FIG. Further, FIG. 2 shows a buffer macro cell having the same configuration as that of FIG. 5 except for the connection between the power supply lines of the first and third layers. This buffer macro cell is composed of basic cells BC1 to BC4 and wirings above them. Above the semiconductor substrate, a pair of power supply lines VD1 and VS1 and power supply lines VD3 and VS3 are arranged in the first wiring layer and the third wiring layer, respectively, along the longitudinal direction of the basic cell row. Power supply lines VD1 and V
D3 is on PMOSFET, power supply lines VS1 and VS3 are NMOSFET
Above. The power supply line VD1 is connected to the source region S of one PMOSFET of the basic cell BC1 via a contact A11, and is connected to the source regions S of the two PMOSFETs of the basic cell BCi (i = 2 to 4, hereinafter the same). They are connected via contacts Ai1 and Ai2, respectively. Similarly, the power supply line VS1 is connected to the basic cell BC1.
The source region S of one of the NMOSFETs is connected via a contact A12, and the source regions S of the two NMOSFETs of the basic cell BCi are connected via contacts Ai3 and Ai4, respectively. One of the gate electrodes G of the basic cell BC1 has a contact A13.
Is connected to the first-layer signal line 30 via
30 is connected to the second-layer signal line 31 via the interlayer contact B1. The drain regions D of one PMOSFET and NMOSFET of the basic cell BC1 are connected to the first-layer signal line 32 via contacts A14 and A15, respectively. The two gate electrodes G of the basic cell BCi are respectively connected to the first gate electrode G via the contacts Ai5 and Ai6.
It is connected to the layer signal line 33. The first layer signal line 33 is
It is connected to the first-layer signal line 32. The drain region D common to the two PMOSFETs of the basic cell BCi is connected to the first-layer signal line 34 via the contact Ai7. Similarly, the drain region D common to the two NMOSFETs of the basic cell BCi is the first via the contact Ai8.
It is connected to the layer signal line 35. The middle portion of the first-layer signal lines 34 and 35 is connected to the first-layer signal line 36 orthogonal to these. One end of the first layer signal line 36 is connected to the second layer signal line 37 via the interlayer contact B2, and the other end of the first layer signal line 36 is connected to the second layer signal line 38 via the interlayer contact B3. It is connected. Here, the power supply lines of the second wiring layer are arranged at intervals of a plurality of basic cells in a direction orthogonal to the longitudinal direction of the basic cell row, but since they do not exist on this buffer macro cell, On the buffer macro cell,
There is no intersection between the power supply line of the third wiring layer and the power supply line of the second wiring layer. Further, in the gate array, the layout of the interlayer contacts that interconnect the power supply lines and the power supply lines of the adjacent wiring layers is predetermined by the semiconductor manufacturer.
Therefore, conventionally, in such a macro cell, the power supply line is
The VD1 and VD3 and the power supply lines VS1 and VS3 were not interconnected. However, in this embodiment, on the PMOSFET of the basic cell BC2 and NM
On OSFET, by bridge Q1 and Q2,
The power supply lines VD1 and VD3 and the power supply lines VS1 and VS3 are interconnected. This bridge Q1 has a contact A2 at one end
A first layer signal line 40 connected to 1, an interlayer contact B4 connected to the other end of the first layer signal line 40, a second layer signal line 41 connected to the interlayer contact B4 at one end, and a second layer Layer signal line 41
Layer contact C1 connecting the other end of the power supply line VD3
Consists of Similarly, bridge Q2 is contacted at one end
A first layer signal line 42 connected to A23, an interlayer contact B5 connected to the other end of the first layer signal line 42, a second layer signal line 43 connected to one end to the interlayer contact B5, and a second layer Layer signal line
Interlayer contact C that connects the other end of 43 to the power supply line VS3
It consists of 2 and. In the above configuration, when the second layer signal line 31 (IN) is set to low level, the PMOSFET of the basic cell BC1 turns on and the basic cell
The NMOSFET of BC1 is turned off, and the first-layer signal lines 32 and 33 become high level. As a result, the plurality of driven logic circuits (not shown) connected in parallel are connected to the second layer signal lines 37, 38 (OU
T), first layer signal lines 36, 35, basic cell BCi (i = 2 to 4)
Between N and D of NMOSFET, contact Ai3, contact Ai4
A relatively large current flows into the power supply line VS1 through the bridge, but a part of the current also flows into the power supply line VS3 through the bridge Q2. When the second layer signal line 31 (IN) is set to high level, the PMOSFET of the basic cell BC1 is turned off and the N of the basic cell BC1 is turned off.
The MOSFET is turned on, and the first layer signal lines 32 and 33 become low level. As a result, from the power supply lines VD1 and VD3 to the contacts Ai1, Ai2 (i = 2 to 4), between the SD of the PMOSFET of the basic cell BCi, the first layer signal lines 34, 36, the second layer signal lines 37, 38.
A relatively large current flows into the plurality of driven logic circuits via (OUT). In the past, the voltage of the power supply lines VD1 and VS1 became unstable due to the driving of the buffer macrocell, but the power supply lines VD1, VSI and VD3, VS3 between the power supply lines VD1, VSI and VS3 are configured by the macrocell itself as in this embodiment. By connecting
The density of the current flowing in the power supply line of each layer is made more uniform than before, the power supply voltage is stabilized, and the influence of noise can be reduced. Since the third wiring layer is an upper layer than the first wiring layer and has large irregularities, the widths of the power supply lines VD3 and VS3 are made wider than the widths of the power supply lines VD1 and VS1 in order to avoid disconnection. ,
The effect is great. Since these bridges Q1 and Q2 have the constituent elements of this buffer macrocell, that is, since such bridges Q1 and Q2 have the constituent elements of the macrocell only in the macrocell through which a relatively large current flows, It is not necessary to dispose a large number of power supply lines in the two wiring layers, and the number of signal channels is increased accordingly, and high integration is possible. FIG. 3 shows a gate array having the same macrocells MS1 to MS10 as in FIG. The difference from FIG. 6 is that the macrocell MSk (k = 3, 4, 6, 8, 9) has, as its constituent elements, power supply lines VD1j and VD3j (j = 1 to 3) and a power supply line VS1j, respectively. , VS3j bridge Qk1, Q
It has a k2. The other points are the same as in FIG.

【The invention's effect】

As described above, in the semiconductor integrated circuit according to the present invention, as the constituent elements of the macrocell, the wirings and the interlayer contacts that connect between the power supply lines of the first and third wiring layers are provided, while the wirings of the third wiring layer are provided. The width of the power supply line is usually the first
Since the width of the wiring layer is wider than that of the wiring layer, the density of the current flowing through the power supply line of the semiconductor substrate side first wiring layer is much smaller than before, the power supply voltage is stabilized, and a macro cell in which a relatively large current flows It is possible to reduce the influence of noise from the power supply. In other words, it is possible to supply power according to the layout of the logic circuit even after the layout of the power supply lines is determined, and a large number of power supplies are provided in the second wiring layer. It is not necessary to dispose a supply line, and the number of signal channels is increased by that much, and it is possible to achieve high integration, which is an excellent effect.

[Brief description of drawings]

FIG. 1 is a principle block diagram of a semiconductor integrated circuit according to the present invention. 2 and 3 relate to an embodiment of the present invention. FIG. 2 is a plan pattern diagram of a buffer macrocell formed by basic cells BC1 to BC4 and wiring, and FIG. 3 is between macrocells of a gate array. It is a plane pattern view showing a connection state between a macro cell and a power supply line and between power supply lines of each wiring layer. 4 to 6 relate to a conventional example, FIG. 4 is a plan pattern diagram showing arrangement and connection of power supply lines of a gate array, and FIG. 5 is a buffer formed by basic cells BC1 to BC4 and wiring. FIG. 6 is a plan pattern diagram showing macro cells, and FIG. 6 is a plan pattern diagram showing connection states between macro cells of a gate array, between macro cells and power supply lines, and between power supply lines of each wiring layer. In the figure, VD1 and VS1 are the first layer power supply lines VD2 and VS2 are the second layer power supply lines VD3 and VS3 are the third layer power supply lines Q1 and Q2 are bridges ● are bulk (semiconductor substrate), Contact between 1 wiring layers ○: contact between 1st and 2nd wiring layers, ◎ contact between 2nd and 3rd wiring layers

Claims (1)

(57) [Claims] 1. A first wiring layer, a second wiring layer, and a third wiring layer are laminated from the semiconductor substrate side through an insulating layer on a semiconductor substrate in which a plurality of basic cells including transistors are arranged in a plurality of rows. The power supply lines (VD1, VS1, VD3, VS3) are arranged along the longitudinal direction of the basic cell row formed on the semiconductor substrate, and
Power supply lines (VD2, VS2) are arranged in the wiring layer and the third wiring layer, and the power supply lines (VD2, VS2) are arranged in the second wiring layer at intervals of several basic cells in a direction perpendicular to the longitudinal direction of the basic cell row. In the semiconductor integrated circuit, as a constituent element of a macro cell (MS) having a certain function, which is formed by connecting the basic cells with wiring, interlayer contacts (B1, C1, B2, C2) and First
A semiconductor integrated circuit comprising wiring (11, 12) connecting a power supply line of a wiring layer and a power supply line of the third wiring layer.