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JP2504232B2 - Lead frame for semiconductor device - Google Patents
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JP2504232B2 - Lead frame for semiconductor device - Google Patents

Lead frame for semiconductor device

Info

Publication number
JP2504232B2
JP2504232B2 JP1292736A JP29273689A JP2504232B2 JP 2504232 B2 JP2504232 B2 JP 2504232B2 JP 1292736 A JP1292736 A JP 1292736A JP 29273689 A JP29273689 A JP 29273689A JP 2504232 B2 JP2504232 B2 JP 2504232B2
Authority
JP
Japan
Prior art keywords
semiconductor device
lead frame
lead
semiconductor element
external leads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1292736A
Other languages
Japanese (ja)
Other versions
JPH03152966A (en
Inventor
定幸 諸井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP1292736A priority Critical patent/JP2504232B2/en
Publication of JPH03152966A publication Critical patent/JPH03152966A/en
Application granted granted Critical
Publication of JP2504232B2 publication Critical patent/JP2504232B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/931Shapes of bond pads
    • H10W72/932Plan-view shape, i.e. in top view
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置用リードフレームに関し、特にそ
の内部リードの構造を改良した半導体装置用リードフレ
ームに関する。
The present invention relates to a semiconductor device lead frame, and more particularly to a semiconductor device lead frame having an improved internal lead structure.

〔従来の技術〕[Conventional technology]

従来、この種の半導体装置に用いるリードフレーム
は、第3図に示すように、半導体素子4上の電極5と内
部リード2をワイヤボンディングするために、電極5の
位置を考慮して内部リード2を設計する必要があった。
Conventionally, as shown in FIG. 3, a lead frame used for a semiconductor device of this type has a structure in which the electrode 5 on the semiconductor element 4 and the inner lead 2 are wire-bonded to each other in consideration of the position of the electrode 5. Had to design.

〔発明が解決しようとする課題〕[Problems to be Solved by the Invention]

上述した従来の半導体装置用リードフレームは、半導
体素子上の電極の配置を考慮して内部リードを設計する
ので、同じサイズの半導体素子であっても電極の配置の
違いによっては、別々のリードフレームを用いることに
なるという欠点がある。
In the conventional lead frame for a semiconductor device described above, the internal leads are designed in consideration of the arrangement of the electrodes on the semiconductor element. Therefore, even if the semiconductor elements have the same size, different lead frames may be provided depending on the arrangement of the electrodes. There is a drawback that will be used.

本発明の目的は、同じサイズの半導体素子に共用でき
る半導体装置用リードフレームを提供することにある。
An object of the present invention is to provide a lead frame for a semiconductor device that can be shared by semiconductor elements of the same size.

〔課題を解決するための手段〕[Means for solving the problem]

半導体素子の封止領域より外部に導出された複数の外
部リードと、該外部リードのそれぞれの半導体素子搭載
台部側の先端部に延長して設けられ前記半導体素子搭載
台部に搭載された前記半導体素子の電極とワイヤにて接
続される内部リードとを有する半導体装置用リードフレ
ームにおいて、前記外部リードのそれぞれの中間の位置
に配置され隣接する前記外部リードのそれぞれに少くと
も1ケ所接続する接続部をもつ少くとも1ケの中間の内
部リードを付設し、前記半導体素子上の前記電極の位置
に合わせ前記外部リードとの接続部を選択して切断し前
記外部リードのそれぞれと切り離して用いることを特徴
とする。
A plurality of external leads led out from the sealing region of the semiconductor element, and the external leads provided on the semiconductor element mounting pedestal and extended to the tip of each semiconductor element mounting pedestal side. In a lead frame for a semiconductor device having an electrode of a semiconductor element and an internal lead connected by a wire, a connection which is arranged at an intermediate position between the external leads and is connected to at least one of the adjacent external leads. At least one intermediate internal lead having a portion is attached, and the connection portion with the external lead is selected and cut according to the position of the electrode on the semiconductor element to be used separately from each of the external leads. Is characterized by.

〔実施例〕〔Example〕

第1図(a),(b)は本発明の第1の実施例の半導
体装置用リードフレームを用いた半導体装置の製造方法
を説明する工程順に示した平面図である。
FIGS. 1 (a) and 1 (b) are plan views showing a method of manufacturing a semiconductor device using a semiconductor device lead frame according to a first embodiment of the present invention in the order of steps.

第1の実施例は、第1図(a),(b)に示すよう
に、外部リード1のそれぞれの先端部に位置し、これら
の先端部に接続する内部リード2aと、外部リード1のそ
れぞれの中間部に位置し、隣接する外部リード1のそれ
ぞれに少くとも1ケ所接続する内部リード2bが形成され
ている。
In the first embodiment, as shown in FIGS. 1 (a) and 1 (b), the internal leads 2a located at the respective tips of the external leads 1 and connected to these tips, and the external leads 1 are connected. Inner leads 2b located at the respective intermediate portions and connected to at least one position on each of the adjacent outer leads 1 are formed.

半導体装置を製造する場合には、半導体素子4上の電
極5の配置に合わせ内部リード2bを選択し、不要な接続
部を切断し半導体装置用リードフレームとして用いる。
When manufacturing a semiconductor device, the internal lead 2b is selected according to the arrangement of the electrodes 5 on the semiconductor element 4, and unnecessary connection parts are cut to be used as a semiconductor device lead frame.

第2図は本発明の第2の実施例の平面図である。 FIG. 2 is a plan view of a second embodiment of the present invention.

第2の実施例は、第2図に示すように、第1の実施例
と同様に、外部リード1と外部リード1の間に形成され
る内部リード2dは格子状に接続された構造で、半導体素
子4上の電極5の配置に合わせて使用する内部リード2d
を選択し、不用な接続部を切断する。
As shown in FIG. 2, the second embodiment has a structure in which the internal leads 2d formed between the external leads 1 and the external leads 1 are connected in a grid pattern, as in the first embodiment. Internal lead 2d used according to the arrangement of the electrode 5 on the semiconductor element 4
Select to disconnect unnecessary connections.

この実施例では、加工能力,内部リードの強度等の可
能な限り格子を細かくすることにより、内部リード2dの
選択の自由度を増すことができる利点がある。例えば、
通常用いられる板厚0.15mmのリードフレーム材ならば、
格子の線幅を0.12mm程度、また、さらに薄い0.12mm厚リ
ードフレーム材ならば、格子の線幅を0.11mm程度にでき
る為、1mm当り4〜5本の格子を形成することができ
る。
This embodiment has an advantage that the degree of freedom in selecting the inner lead 2d can be increased by making the lattice as fine as possible in terms of processing capability, strength of the inner lead, and the like. For example,
If it is a lead frame material with a thickness of 0.15 mm that is usually used,
If the lead frame material has a grid line width of about 0.12 mm or a thinner 0.12 mm thickness, the grid line width can be set to about 0.11 mm, so that 4 to 5 grids can be formed per 1 mm.

〔発明の効果〕〔The invention's effect〕

以上説明したように本発明は、隣り合う外部リードの
それぞれと少なくとも1ケ所接続する内部リードを形成
し、半導体素子上の電極の配置に合わせて内部リードを
選択して使用できることにより、同じサイズの半導体素
子に対してそれぞれリードフレームを設計,生産しなく
てよいので途中工程までは多品種の共用ができる効果が
ある。
INDUSTRIAL APPLICABILITY As described above, according to the present invention, by forming an inner lead that is connected to each of the adjacent outer leads at least at one place, and the inner lead can be selected and used according to the arrangement of the electrodes on the semiconductor element, Since it is not necessary to design and produce a lead frame for each semiconductor element, there is an effect that a wide variety of products can be shared until the intermediate process.

また、ボンディングワイヤの長さを比較的短かくする
ことができ、安定した半導体装置の製造が可能となる効
果がある。
Further, there is an effect that the length of the bonding wire can be made relatively short, and a stable semiconductor device can be manufactured.

さらに、あらかじめリードフレームを設計,生産して
おけるので半導体装置の開発期間が短縮できるという効
果もある。
Further, since the lead frame can be designed and produced in advance, the semiconductor device development period can be shortened.

【図面の簡単な説明】[Brief description of drawings]

第1図(a),(b)は本発明の第1の実施例の半導体
装置用リードフレームを用いた半導体装置の製造方法を
説明する工程順に示した平面図、第2図は本発明の第2
の実施例の平面図、第3図は従来の半導体装置用リード
フレームの一例の平面図である。 1……外部リード、2,2a,2b,2c,2d……内部リード、3
……半導体素子搭載台部、4……半導体素子、5……電
極、6……金線。
1 (a) and 1 (b) are plan views showing a method of manufacturing a semiconductor device using the semiconductor device lead frame according to the first embodiment of the present invention in the order of steps, and FIG. Second
And FIG. 3 is a plan view of an example of a conventional lead frame for a semiconductor device. 1 ... External lead, 2,2a, 2b, 2c, 2d ... Internal lead, 3
…… Semiconductor element mounting base, 4 …… Semiconductor element, 5 …… Electrode, 6 …… Gold wire.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】半導体素子の封止領域より外部に導出され
た複数の外部リードと、該外部リードのそれぞれの半導
体素子搭載台部側の先端部に延長して設けられ前記半導
体素子搭載台部に搭載された前記半導体素子の電極とワ
イヤにて接続される内部リードとを有する半導体装置用
リードフレームにおいて、前記外部リードのそれぞれの
中間の位置に配置され隣接する前記外部リードのそれぞ
れに少くとも1ケ所接続する接続部をもつ少くとも1ケ
の中間の内部リードを付設し、前記半導体素子上の前記
電極の位置に合わせ前記外部リードとの接続部を選択し
て切断し前記外部リードのそれぞれと切り離して用いる
ことを特徴とする半導体装置用リードフレーム。
1. A plurality of external leads led out from a sealing region of a semiconductor element, and the semiconductor element mounting base provided by extending to the tip of each of the external leads on the side of the semiconductor element mounting base. In a lead frame for a semiconductor device having an internal lead connected to the electrode of the semiconductor element mounted on a wire by a semiconductor device, the external lead is arranged at an intermediate position between the external leads and at least adjacent external leads are provided at least. Each of the external leads is provided with at least one intermediate inner lead having a connecting portion for connecting at one location, and selecting and disconnecting the connecting portion with the external lead according to the position of the electrode on the semiconductor element. A lead frame for a semiconductor device, which is used separately from the lead frame.
JP1292736A 1989-11-09 1989-11-09 Lead frame for semiconductor device Expired - Lifetime JP2504232B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1292736A JP2504232B2 (en) 1989-11-09 1989-11-09 Lead frame for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1292736A JP2504232B2 (en) 1989-11-09 1989-11-09 Lead frame for semiconductor device

Publications (2)

Publication Number Publication Date
JPH03152966A JPH03152966A (en) 1991-06-28
JP2504232B2 true JP2504232B2 (en) 1996-06-05

Family

ID=17785662

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1292736A Expired - Lifetime JP2504232B2 (en) 1989-11-09 1989-11-09 Lead frame for semiconductor device

Country Status (1)

Country Link
JP (1) JP2504232B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0693469B2 (en) * 1989-11-28 1994-11-16 株式会社東芝 Resin-sealed semiconductor device
JP2009176912A (en) * 2008-01-24 2009-08-06 Sumitomo Metal Mining Co Ltd Film carrier tape and semiconductor device using the same
JP6352876B2 (en) * 2015-09-15 2018-07-04 東芝メモリ株式会社 Manufacturing method of semiconductor device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5010967A (en) * 1973-05-28 1975-02-04
JPS5029163A (en) * 1973-07-17 1975-03-25

Also Published As

Publication number Publication date
JPH03152966A (en) 1991-06-28

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