JP2506759B2 - Shifter circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shifter circuit used in a central processing unit of a digital computer or the like.

As a conventional shifter circuit, for example, U.S. Pat.
It is shown in issue 556.

FIG. 6 is a block diagram showing the input / output of a conventional shifter circuit. 2 is a barrel shifter having 64-bit input / output, 5 is a 64-bit input data bus, 7 is a 64-bit output data bus, and 9 is a barrel shifter. A 7-bit shift number control line representing the number of shifts to be executed by 2, 10 is a 2-bit shift control line that specifies the operation of the barrel shifter 2, and 12 is a carry output line. FIG. 7 is a diagram showing the input / output relationship of the barrel shifter 2, where the input data is A _{63 to} A ₀ and the shift number is S ₆
To S ₀ , output data when shift control is C _{1 to} C ₀ Y ₆₃
~ Y ₀ and carry CR are illustrated. Number of shifts is S ₆ ~
It is represented by a signed number of 7 bits by S _0. When positive, it means left shift or left rotate up to 63 bits, and when negative, it means right shift or right rotate up to 64 bits. Also, the shift operation is specified by C ₁ and C ₀ , and C ₁ =
Arithmetic shift (shift in bit at right shift is sign bit) when 0 to C ₀ = 0, logical shift (shift in bit at right shift is 0) when C ₁ = 0 and C ₀ = 1, C ₁
When = 1 (C ₀ is irrelevant), it operates as rotate.

In the conventional shifter circuit configured as described above, the input data is supplied to the barrel shifter 2 via the input data bus 5 and the shift number is supplied to the barrel shifter 2 through the shift number control line 9, and at the same time, the operation of the barrel shifter 2 is designated through the shift control line 10. As a result, desired output data and carry are obtained from the output data bus 7 and carry output line 12.

Problems to be Solved by the Invention However, in the above-mentioned configuration, the barrel shifter 2
Shift with a data length of 64 bits equal to the bit width of /
Only the rotate operation can be executed, and as shown in FIG. 8a, the lower 32 bits are valid input data (the upper 32 bits are undefined) are supplied to the barrel shifter 2 through the input data bus 5 and 32 bits are set as the data length. Even if an attempt is made to execute the 1-bit left logical shift, the shift result is correctly obtained, but the upper undefined bit of the input data is reflected in the carry, and the correct carry cannot be obtained. Also, as shown in FIG. 6B, the carry can be obtained correctly even if an attempt is made to execute a 1-bit right logical shift with the data length of 32 bits for the same input data, but the upper undefined bits of the input data are shifted. Since it is down, a correct shift result cannot be obtained in the lower 32 bits of the output data bus 7. As described above, the conventional shifter circuit has a problem that the shift / rotate operation with the data length smaller than the bit width of the barrel shifter 2 cannot be performed.

In view of such a point, the present invention provides a shifter circuit capable of performing a shift / rotate operation of not only a data length equal to the bit width of the barrel shifter to be used but also half or less than half the bit width of the barrel shifter. The purpose is to

The present invention relates to a barrel shifter having a function equivalent to that of a barrel shifter that constitutes a conventional shifter circuit, having a bit width of L bits, and performing arithmetic shift / logical shift / rotate.
LSB (Least Significant Bit) of L-bit input data
MSB from k bits (1 ≤ k ≤ L / 2 or k = L)
Input conversion circuit that copies from (Most Significant Bit) to k bit position and outputs it as barrel shifter shift data. The number of shifts in the barrel shifter is left when n bits (1 ≤ n ≤ k) left (MSB direction) shift or rotate. Outputs a control signal that becomes n bits and outputs n bits right (LSB
The shifter circuit includes a shift number control circuit that outputs a control signal in which the shift number in the barrel shifter becomes right (n + L−k) bits during (direction) shift or rotation.

Actions It will be described with reference to FIG. 5 that the above-mentioned means achieves the object of the invention.

Valid input data having a data length of k bits to be shifted or rotated is obtained at a position of k bits from the LSB of the L bit input data bus. When the data copied by the input conversion circuit is shifted or rotated to the left by n bits, the data is shifted / rotated to the left by n bits. This is shown in FIG. When shifting or rotating to the right by n bits, the copied data is shifted / rotated to the right by (n + L−k) bits by the shift number control circuit.
This is shown in FIG. As a result, valid output data of left or right shifted or rotated k bits is obtained at a position of k bits from the LSB of the L bit output data bus from the barrel shifter, and a carry is obtained on the carry output line. Further, the same result and carry (0) are obtained for 0-bit shift / rotate.

As described above, the present invention has the above-mentioned structure.
For any k that satisfies ≦ k ≦ L / 2 or k = L, k
It becomes possible to shift and rotate the data length of bits in the range of left and right k bits.

Embodiment FIG. 1 shows a block diagram of a shifter circuit in an embodiment of the present invention. Reference numeral 1 is a shifter circuit according to the present invention, 2 is a barrel shifter having a bit width of 64 bits having a function equivalent to that of a barrel shifter constituting a conventional shifter circuit, 3 is 8 bits from LSB of 64-bit input data, 1
Copy 6-bit or 32-bit part from MSB to 8-bit, 16-bit, 32-bit position and output, or 64
Input conversion circuit that outputs bit input data as it is,
4 has a negative shift number (right shift / rotate)
A shift number control circuit for subtracting 56, 48 or 32 from the shift number depending on the data length of the shift / rotate operation executed when, 5 is a 64-bit input data bus, and 6 is an output of the input conversion circuit 3 of 64 bits Barrel shifter input data bus, 7 is a 64-bit output data bus, 8 is a 2-bit data length control line representing the data length of the shift / rotate operation executed in the shifter circuit 1, and 9 is the shifter circuit 1.
7-bit shift number control line indicating the shift number
10 is a 2-bit shift control line that specifies the operation of the barrel shifter 2, 11 is a 7-bit barrel shifter shift number control line that represents the number of shifts executed by the barrel shifter 2 at the output of the shift number control circuit 4, and 12 is a carry output line. is there. FIG. 2 is a diagram showing the input / output relationship of the input conversion circuit 3. The barrel shifter input data bus 6B ₆₃ when the input data bus 5 is A _{63 to} A ₀ and the data length control line 8 is SZ ₁ to SZ _0. ~ B ₀ is a graphical representation of the data above. Here, * represents 0 or 1. The data length of the shift / rotate operation performed by the shifter circuit 1, 8-bit (byte) when SZ ₁ = 0 and _{SZ 0 = 0, SZ 1 =} 0 and 16-bit (half word when SZ ₀ = 1 ), SZ ₁ = 1 and SZ ₀ = 0 are defined as 32 bits (word), and SZ ₁ = 1 and SZ ₀ = 1 are defined as 64 bits (double word). FIG. 3 is a diagram showing the input / output relationship of the shift number control circuit 4, in which the shift number control line 9 is S _{6 to} S ₀ and the data length control line 8 is SZ ₁ to SZ _0. It illustrates the bit pattern on line 11D ₆ to D _0. The input / output relation of the barrel shifter 2 is the shift control line 10
Is C _{1 to} C _0, and in FIG. 7, A _{63 to} A ₀ is replaced with B _{63 to} B ₀ by S ₆ to
Equivalent to reading S ₀ from D _{6 to} D ₀ . The shift operation executed by the shifter circuit 1 is the same as the shift operation of the barrel shifter 2. The arithmetic shift is performed when C ₁ = 0 and C ₀ = 0, the logical shift is performed when C ₁ = 0 and C ₀ = 1, and the C ₁ = 1. When, it becomes rotate.

The operation of the shifter circuit of the present embodiment configured as above will be described below.

The data length of the shift / rotate operation to be executed is given to the data length control line 8, the selection of arithmetic shift / logical shift / rotate is specified by the shift control line 10, the input data is the input data bus 5, and the shift number is the shift number control. It is given to the shifter circuit 1 through the line 9.

(B) When the data length is 8 bits (bytes) The input conversion circuit 3 changes the LSB of the input data bus 5 to 8
The valid part of the bit is copied from the MSB to the 8-bit position and output to the barrel shifter input data bus 6. On the other hand, in the shift number control circuit 4, the shift number control line 9 is regarded as a signed integer in the lower 4 bits, zero-extended to 7 bits when 0 to 7, and 56 is subtracted when -8 to -1. Output to the barrel shifter shift number control line 11. The barrel shifter 2 shifts or rotates the 64-bit data of the barrel shifter input data bus 6 by the number of shifts of the barrel shifter shift number control line 11. The shift / rotate result is obtained in the 8-bit portion from the LSB of the output data bus 7, and the carry is obtained in the carry output line 12.

(B) When the data length is 16 bits (half wide) The input conversion circuit 3 changes the LBS of the input data bus 5 to 16 bits.
The valid part of the bit is copied from the MSB to the 16-bit position and output to the barrel shifter input data bus 6. On the other hand, in the shift number control circuit 4, the shift number control line 9 is regarded as a signed integer in the lower 5 bits, zero-extended to 7 bits when 0 to 15 and subtracted from 48 when -16 to -1. Output to the barrel shifter shift number control line 11. The barrel shifter 2 shifts or rotates the 64-bit data of the barrel shifter input data bus 6 by the number of shifts of the barrel shifter shift number control line 11. The shift / rotate result is obtained in the 16-bit portion from the LSB of the output data bus 7, and the carry is obtained in the carry output line 12.

(C) When the data length is 32 bits (word) The input conversion circuit 3 changes the LSB of the input data bus 5 to 32.
The valid part of the bit is copied from the MSB to the 32-bit position and output to the barrel shifter input data bus 6. On the other hand, in the shift number control circuit 4, the shift number control line 9 is regarded as a signed integer in the lower 6 bits, zero-extended to 7 bits when 0 to 31, and subtracted by 32 when −32 to −1. Output to the barrel shifter shift number control line 11. The barrel shifter 2 shifts or rotates the 64-bit data of the barrel shifter input data bus 6 by the number of shifts of the barrel shifter shift number control line 11. The shift / rotate result is obtained from the LBS of the output data bus 7 in the 32-bit portion, and the carry is obtained on the carry output line 12.

(D) When the data length is 64 bits (double word), the input conversion circuit 3 keeps the 64-bit valid data of the input data bus 5 as it is on the barrel shifter input data bus 6, and the shift number control circuit 4 keeps the shift number control line 9 as it is. Output to each of the barrel shifter shift number control lines 11. The barrel shifter 2 shifts or rotates the 64-bit data of the barrel shifter input data bus 6 by the number of shifts of the barrel shifter shift number control line 11. The 64-bit shift / rotate result is obtained on the output data bus 7 and the carry is obtained on the carry output line 12.

As described above, according to the present embodiment, the input conversion circuit and the shift number control circuit are preceded by the 64-bit barrel shifter, so that the 8-bit data length is 16 bits up to the left 7 bits and the right 8 bits. Arithmetic shift up to left 15 bits / right 16 bits for left data length, left 31 bits / right 32 bits up to 32 bit data length, left 63 bits / right 64 bits up to 64 bit data length・
Logical shift / rotate can be performed.

Incidentally, FIG. 4 is a logic circuit diagram of the shift number control circuit in the embodiment. The subtraction of 56, 48, 32 corresponding to the data length can be easily realized by setting the bits of D _{5 to} D ₃ , D _{5 to} D ₄ , and D ₅ to 0, respectively.

EFFECTS OF THE INVENTION As described above, according to the present invention, not only the data length equal to the bit width of the barrel shifter to be used but also the shift / rotate operation of half or less than the bit width of the barrel shifter is performed. Can be achieved, and its practical effect is great.

[Brief description of drawings]

FIG. 1 is a block diagram of a shifter circuit in an embodiment of the present invention, FIG. 2 is an input / output relational diagram of an input conversion circuit of the embodiment,
FIG. 3 is an input / output relational diagram of the shift number control circuit of the same embodiment,
FIG. 4 is a logic circuit diagram of the shift number control circuit of the same embodiment, FIG. 5 is an explanatory diagram showing the operation of the present invention, FIG. 6 is a block diagram of a conventional shifter circuit, and FIG. FIG. 8 is an input / output relationship diagram of the barrel shifter, and FIG. 8 is an explanatory diagram showing the problems of the conventional example. 1 ... Shifter circuit, 2 ... Barrel shifter, 3 ... Input conversion circuit, 4 ... Shift number control circuit, 5 ... Input data bus, 6 ... Barrel shifter input data bus, 7 ... Output data bus, 8 ... ... data length control line, 9 ... shift number control line, 10 ... shift control line, 11 ... barrel shifter shift number control line, 12 ... carry output line.

Claims (1)

(57) [Claims] 1. A barrel shifter having an L-bit width and performing arithmetic shift / logical shift / rotate, and a portion of L bits of input data from k bits (1 ≦ k ≦ L / 2 or k = L). And an input conversion circuit for copying the data from the MSB to a position of k bits and outputting it as shift data of the barrel shifter, and the number of shifts in the barrel shifter is left n when n bits (1 ≦ n ≦ k) left (MSB direction) shift or rotate. A shift number control circuit that outputs a control signal that becomes a bit and outputs a control signal that outputs a right (n + L−k) bit shift number in the barrel shifter at the time of n-bit right (LSB direction) shift or rotate, and the entire shifter circuit. A shifter circuit capable of performing arithmetic shift / logical shift / rotate with a data length of k bits.