JP2506782B2 - Image data parallel processing device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to image data processing, and more particularly, to an image data parallel processing device for enlargement and reduction thereof.

2. Description of the Related Art Conventionally, image enlargement / reduction processing techniques have been known.
FIG. 6 is a diagram for explaining the operation principle when a conventional image is enlarged or reduced. The example in the figure is a case where an original image composed of 8 pixels is reduced to a resultant image of 5 pixels. This principle is based on Kei. K. Kawakami and S. S. Shimazaki, "Special LSI Processor (D Special Algorithm) that uses DDA algorithm for image conversion
LSI Processor Using the DDA Algorithm for Image T
ransformation) ", JP-A-59-214376 and USP 4,60
This is described in detail in Japanese Patent No. 2,346, but its outline will be described below.

In FIG. 6, an intersection of a vertical line passing through the center of the pixel a _i and a straight line L having an inclination of 5/8 is P _i . Assuming that a result pixel penetrated by a horizontal line passing through the point P _i is b _j , the density transfer of a _i → b _j (1) is performed to obtain b _{1 to} b _{5, that} is, the density of the result pixel.

Such a correspondence relationship between the original image and the result image can be sequentially obtained by addition and condition determination. Here, the correspondence between a _i and b _j will be described as a _{i to} b _j .

Let a _{1 to} b ₁ a _{i to} b _j Is. Where h _i is the value of the Y coordinate of the point P _i , and [h _i ] is h _i
It is an integer not exceeding. That is, when it is known that a _i and b _j correspond to each other, the operation of h _i − [h _i ] +5/8 is performed, and it is determined whether or not it becomes larger than 1, that is, whether or not a carry occurs. , pixels corresponding to b j _{+ 1} is able to determine whether a _{i + 1} is a _i. Now R _n = h _n - and [h _n] (3), when the in carry information to the addition of 5/8 and R _n 'and C _n, the result of the successive operations described above as in the seventh Figure become.
It can be seen from FIG. 7 that five carry occurs during the eight additions. Therefore, the pixel density transfer is performed 8 times for the 5 resultant pixels, and an image reduced to 5/8 is obtained.

FIG. 8 shows an example of a conventional apparatus for reducing an image using the above principle. In the figure, reference numeral 800 is a ratio register for setting an enlargement / reduction ratio, 810 is a residual register (residual holding means) for holding a quantization error, and 811 is a carry information register (residual holding means) for holding carry information. . 814
Reference numeral 815 is an original image register (original image holding means) for holding an original image, and 815 is a result image register (result image holding means) for holding a result image. Reference numeral 812 is an original pixel pointer (original pixel instructing means) that points to a pixel in the original image, and 813 is a result pixel pointer (resulting pixel instructing means) that points to a pixel in the result image. 850 is a start (drive) signal.

Next, the operation will be described. When a pulse is applied to the activation signal 850, the content of the original pixel pointer 812 is incremented by 1, and at the same time, the content of the ratio register 800 is added to the content of the residual register 810. If a carry is generated as a result of this addition, 1 is stored in the carry register 811 and the content of the result pixel pointer 813 is incremented by 1. If no carry occurs, the content of the result pixel pointer 813 is unchanged.

After this, the original pixel pointer 812 is inserted into the original image register 814.
To the position of the pixel indicated by the result pixel pointer 813 in the result image register 815 in the result image register 815.
Transfer through 17.

By repeating the above operation, the original image register 81
A reduced image is obtained in the result image register 815 with respect to the original image stored in 4.

For example, if the ratio 5/8 is stored in the ratio register 800 and the initial value of the residual register 810 is 5/16, the carry register 811
1 is generated as shown in FIG. Therefore, when eight pulses are applied to the start signal 850, the original pixel pointer 812 is incremented eight times, the result pixel pointer 813 is incremented five times, and the density information from the original image register 814 to the result image register 815 is transferred. The transfer is performed 8 times. This results in a reduced image of 5 pixels in the result image register.

Further, according to the same calculation, the pixel density is transferred from the result image register 815 to the original image register 814 in reverse, so that 8
Obviously, we get the image magnified by / 5 in the original image register 814.

However, the apparatus shown in FIG. 8 has a drawback in that the rounding error in the ratio register 800 is accumulated in the residual register 810.

FIG. 9 shows a conventional example in which the defect of rounding error in the apparatus of FIG. 8 is improved.

In FIG. 9, 900 is a numerator register holding a numerator, and 917 is a denominator register holding a denominator. 910,911,912,193,91
Reference numerals 4,915 correspond to the residual register 810, the carry information register 811, the original pixel pointer 812, the result pixel pointer 813, the original image register 814, and the result image register 815 in FIG. Reference numeral 916 is an adder, and reference numeral 918 is a subtracter for subtracting the contents of the denominator register 912 from the output of the adder 916. Reference numeral 919 denotes a multiplexer, which performs selection control based on the borrowed information in the subtraction of the subtractor 918. That is, the subtractor 918 is used only when the content of the denominator register 917 is smaller than the output of the adder 816.
Is selected and becomes the output of the multiplexer 919.
In other cases, the output of the adder 916 is selected and becomes the output of 919. The activation signal 950 corresponds to the activation signal 850 in FIG.

If the values stored in the numerator register 900 and the denominator register 917 are integers and are f and g, respectively, the reduction ratio of this device is f / g. Numerator register 900 and residual register 910
In this case, the values g times the respective values of the ratio register 800 and the residual register 810 shown in FIG. In the device shown in FIG. 8, when the carry is generated in the adder 816 and the value of the residual register 810 becomes smaller by 1 than the value one time before, the output of the adder 916 of FIG. 9 is the denominator register 917.
Corresponding to the fact that the value is larger than the content of the, the subtraction is performed, and the result is stored in the residual register 910.

As can be seen from the above description, the carry information 911 in the apparatus of FIG. 9 is generated exactly the same number of times as the carry information 811 of FIG. In this device, rounding errors do not occur because only integer operations are performed.

Problems to be Solved by the Invention In the conventional apparatus as described above, the addition of the ratio and the residual is performed by the same adder (for example, the adder 816 in FIG. 8) in the processing of all pixels. However, the processing speed of the entire device is affected by the speed of this adder, and high-speed processing cannot be performed.

As a method for solving the above problem, parallelization of the conventional apparatus shown in FIG. 8 is conceivable. However, the point cloud forming the original image is divided into a plurality of point clouds, and each point cloud is processed independently. Then, the configuration becomes complicated, such as calculating the starting points separately.

It is an object of the present invention to provide an image data parallel processing apparatus capable of high-speed processing, which has a simple structure and solves the above-mentioned conventional problems by calculating and collecting continuous original pixels independently by a plurality of processing units. And

Means for Solving the Problems The present invention relates to a ratio setting unit for setting a reduction or enlargement ratio of an image, and an image parallel processing unit including a predetermined number of partial image processing units for inputting outputs of the ratio setting unit. A collecting means for outputting a reduced or enlarged image by inputting and collecting the outputs of the partial image processing sections, and a distribution means for distributing the original image into a plurality of parts and outputting the divided images to the respective partial image processing sections. Further, the partial image processing unit adds a residual holding means for holding a quantization error of a pixel position as a residual, and outputs the carry information by adding the residual and the predetermined multiple of the ratio and a new residual. To the residual holding means, an original image holding means for holding the partial original image, an original pixel instructing means for instructing one pixel of an image held by the original image holding means based on a drive signal, The result image holding means connected to the original image holding means and the result pixel indicating means for indicating one pixel of the holding pixels of the result image holding means based on the carry information, The predetermined number of original pixels are distributed to the partial image processing units one by one, and the pixel values in the result image holding means of the partial image processing units corresponding to the same pixel position of the result image are collected by the collecting means. To do.

Operation The present invention is capable of performing high-speed image processing with a simple structure without using a complicated structure such as division due to the above structure.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram for explaining the principle of the present invention. Similar to the conventional example, an example will be described in which an original image composed of 8 pixels is reduced to a result image composed of 5 pixels.
The slope of the straight line L in FIG. 1 is 5/8. The correspondence relationship between the pixel a _{i of the} original image and the pixel b _j of the resulting image is also the same as in FIG.

According to the principle of the present invention, the result pixel corresponding to the odd-numbered pixel a _2i-1 and the result pixel corresponding to the even-numbered pixel a _2i are independently calculated and are operated in parallel to speed up the process. It is intended.

A vertical line passing through the center of the odd-numbered original pixel a _2i-1 and a straight line L
Let Q _i be the point of intersection with X and S _i be the point of intersection of the straight line L with a vertical line passing through the center of the even-numbered original pixel a _2i . The resulting pixels penetrated by the horizontal line passing through Q _i and S _i are b _j and b _h , respectively.

Let the values of the Y coordinates of Q _i and S _{i be} y _{Q, i} and y _{S, i} , respectively. And Because as well as Becomes However, p is the reduction ratio, which is 5/8 in the case of FIG.

From the above, in the same device as in FIG. 8, the contents of the ratio register are doubled and two devices are operated in parallel to correspond to the odd-numbered original pixels and the even-numbered original pixels, respectively. Resulting pixels can be calculated in parallel.

FIG. 2 is a block diagram of an example of an apparatus based on this principle, that is, an image data parallel processing system in an embodiment of the present invention. In the figure, reference numeral 290 denotes an image data parallel processing unit that processes image data in parallel. 200 is a ratio register that sets the ratio. Reference numerals 210, 211, 212, 213, 214, 215 and 216 respectively correspond to the residual register 810, carry information register 811, original pixel pointer 812, result pixel pointer 813, original image register 814, result image register 815 and adder 816 of FIG. 8 and have similar functions. Are different in the following points. That is,
The value R _n of the residual register 210 is the same as the residual register 810 of FIG. 8 in that it takes the value 0 ≦ R _n <1, but the value of the ratio register 200 takes the value 0 ≦ p <2. . Therefore, when both are expressed in binary, the width of the ratio register 200 is
It is longer than the residual register 210 by the integer part, ie by one bit. Therefore, the output of the adder 216 that adds the two is
The integer part can take values from 0 to 2. The carry information register 211 stores the integer part of this addition result, and the residual register 210 stores the decimal part. An adder 217 adds the output of the result pixel pointer 213 and the output of the carry information register 211.

220, 221, 222, 223, 224, 225, 226, 227 of FIG. 2 correspond to the residual register 210, carry information register 211, original pixel pointer 212, result pixel pointer 213, original image register 214 and result image register 215, adder 216 and adder 217, respectively, and are the same. It has the function of. 250 is a start signal. 251 is an original image input buffer, and 252 is a distributor (means). 253 is an aggregator (means), and 254 is a result output buffer. 255 is an image storage device.

 Next, the operation of this embodiment will be described.

The one row of pixels read from the image storage device 255 is once stored in the input buffer 251, read serially from the input buffer 251, and distributed by the distributor 252 to odd-numbered pixels and even-numbered pixels, Original image register 214,
Input to 224. The pixels stored in the original image registers 214 and 224 are the residual registers 210 and 220 that operate as described above.
Or original pixel pointer 21 determined by the function of adders 216, 226, etc.
2, 222 and the result pixel pointers 213 and 223 are selected according to the instruction, and the density thereof is transferred and stored in the result image registers 215 and 225. The contents of the result image registers 215, 225 are collected by the aggregator 253 into the corresponding pixels, stored in the result output buffer 254, and written in the image memory 255.

FIG. 3 shows the relationship in which the contents of the result buffer 254 are generated from the data of the result image registers 215 and 225. The contents of the result image registers 215 and 225 are 315 and 325, respectively.
It corresponds to the state shown in. From these two pixel groups, an operation such as addition or logical sum is performed between pixels corresponding to the same position to generate data as shown at 354.

The original pixel pointers 212 and 222 are incremented by one each time the activation signal 250 is pulsed. Therefore, each time a pulse is applied, the original pixel pointer 212 sequentially indicates an odd-numbered pixel, and the original pixel pointer 222 sequentially indicates an even-numbered pixel. Further, the result pixel pointers 213 and 223 indicate Q _i , S _i
The result pixels corresponding to are sequentially designated.

Therefore, by transferring the densities of the pixels designated by the original pixel pointers 212 and 222 to the pixels designated by the result pixel pointers 213 and 223, respectively, b _j corresponding to Q _i is stored in the result image register 215 and S _i is stored in the result image register 225. A corresponding _bk is generated. The densities of the corresponding pixels between the two registers 215 and 225 are added or averaged and stored in the output buffer 254 to obtain a reduced image.

FIG. 4 shows a second embodiment of the present invention in the case of a system for preventing the accumulation of rounding errors of the ratio register 200 in FIG. In the figure, 400, 411, 416, and 450 are ratio registers 200 in FIG.
The carry information register 211, the adder 216, and the activation signal 250 correspond to each other and have the same function. 418 and 403 are adders 41
The subtractor subtracts the contents of the denominator register 417 and the denominator register 402 from the output of 6. 404 is an exclusive OR device.

The principle of FIG. 4 is the same as that of FIG. When the reduction ratio is f / g (f and g are integers), f is stored in the numerator register 400.
2g is stored in the denominator register 402 and g is stored in the denominator register 417. The multiplexer 419 includes an adder 416 and a subtractor 417.
Alternatively, one of the outputs of the subtractor 403 is selected and output.
This selection is controlled by the borrow information of subtractors 417 and 403 and is as follows. That is, _assuming that the output of the adder 416 is x, the output of the multiplexer is R _n , and the value stored in the carry register 411 is C, when 0 ≦ x <g, R _n = x, c = 00 g ≦ x < When 2g, R _n = x−g, c = 01, and when 2g ≦ x, R _n = x−2g, c = 10. From the above, it can be seen that the carry information register 411 is similar to the carry information registers 211 and 221 in FIG. Therefore, each of the two devices shown in FIG. 4 has the ratio register 200, the residual registers 210 and 220, and the carry information register 21 shown in FIG.
By applying it to 1,221 and adders 216, 226, 217, and 227, it is possible to perform an accurate calculation without accumulating rounding errors.

FIG. 5 shows another embodiment of the present invention in which n modules of the partial image processing units 590, 590, ... Are processed in parallel. In the figure, reference numerals 500, 510 to 517, 550 to 555 correspond to the elements 200, 210 to 217, 250 to 255 of FIG. 2, respectively, and have the same functions except for the following points. That is, the bit width of the carry information register 511 is an integer equal to or greater than log ₂ ⁿ , the distributor 552 distributes the original image to the n destinations, and the aggregator 553 uses the n collectors. Module 5
The difference is that data is collected from 30 and combined into one.

With the above configuration, n modules operate in parallel, and the entire processing is processed in 1 / n of the time when one module executes.

In accordance with the same calculation, the density values are transferred from the result image registers 215 and 225 to the original image registers 214 and 224 in reverse, so that the image stored in the result image register 215 is enlarged to 8/5 and the original image register is displayed. Obtained in 214. In that case, it goes without saying that the distributor 252 and the collector 253 perform reverse operations.

It goes without saying that in the above embodiments, the processing of various registers can be processed by software of the computer.

EFFECTS OF THE INVENTION As described above, the image data parallel processing apparatus according to the present invention can calculate a continuous original pixel independently and in parallel by a plurality of processing units, and can collect the original pixels without using a complicated configuration such as division. With the configuration, high-speed image processing can be realized.

[Brief description of drawings]

FIG. 1 is a conceptual diagram for explaining the principle of an image data parallel processing system in an embodiment of the present invention, FIG. 2 is a block diagram of an apparatus of the same system, and FIG. 3 is data of the same apparatus of FIG. FIG. 4 is a diagram for explaining the operation of the gathering unit, FIG. 4 is a block diagram of essential parts of another embodiment of the present invention, FIG. 5 is a block diagram of essential parts of another embodiment of the present invention, and FIG. FIG. 7 is a conceptual diagram for explaining the principle of the image data processing system of FIG. 7, FIG. 7 is a diagram for explaining the operation of the device by the conventional system, FIG. 8 is a block diagram of the device of the conventional system, and FIG. 9 is a rounding error. FIG. 6 is a block diagram of an apparatus of a conventional method that does not accumulate. 200,400 …… Ratio setting means, 210,220 …… Residual holding means,
211,221 ... Carry information register, 212,222 ... Original pixel indicating means, 213,223 ... Result pixel indicating means, 214,224 ... Original image holding means, 215,225 ... Result image holding means, 216,226
...... Adder, 250 …… Starting (driving) signal, 252 …… Distributing means, 253 …… Assembling means, 290 …… Image parallel processing section, 590 ・ ・ ・
... Partial image processing unit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Chika Onodera 3-10-1 Higashisanda, Tama-ku, Kawasaki City Matsushita Giken Co., Ltd. (56) Reference JP-A-60-189579 (JP, A) JP 59-214376 (JP, A) JP-A-63-26781 (JP, A)

Claims (1)

(57) [Claims] 1. A ratio setting means for setting a reduction or enlargement ratio of an image, an image parallel processing section having a predetermined number of partial image processing sections for inputting the output of the ratio setting means, and those partial image processing sections. Each of the outputs is input and aggregated to output a reduced or enlarged image, and a distribution unit that distributes the original image into a plurality of parts and outputs the images to each of the partial image processing units. The processing unit adds a residual holding means for holding a quantization error of a pixel position as a residual, and outputs the carry information by adding the residual and the ratio of the predetermined number of times and outputs a new residual to the residual holding means. Adding means,
Original image holding means for holding the partial original image, original pixel instructing means for instructing one pixel of the held image of the original image holding means based on a drive signal, and result image holding connected to the original image holding means Means and a result pixel designating means for designating one pixel of the holding pixels of the result image holding means based on the carry information, wherein the distributing means has the continuous predetermined number of original pixels one by one. An image data parallel processing device, characterized in that the pixel values in the result image holding means of each of the partial image processing portions corresponding to the same pixel position of the result image are collected by the collecting means.