JP2508457B2 - Digital video signal recorder - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital video signal recording apparatus for recording a component video signal on a magnetic tape by a rotary head.

[Outline of Invention]

The present invention reduces the influence of burst errors occurring in the recording / reproducing process by using block shuffling in units of blocks and field shuffling in units of one field when recording a component video signal. The error correction or error correction is effectively performed.

[Conventional technology]

In the conventional digital VTR, shuffling is used to change the order of recorded data from the original order in order to cope with a transmission error occurring in the recording / reproducing process. According to shuffling, continuous sample data can be prevented from being erroneous, a plurality of data included in the same code sequence can be prevented from being erroneous, and error correction ability and error correction ability can be substantially improved. You can In a conventional digital VTR, for example, a digital VTR for recording / reproducing a high-definition television signal described in JP-A-60-255454, a shuffling circuit is provided in a stage subsequent to the error correction encoder.

[Problems to be solved by the invention]

Since the conventional digital VTR performs only one stage of shuffling, there is a problem that when a long burst error occurs, the error gater cannot be properly corrected or a large amount of error data that cannot be corrected occurs.

Therefore, it is an object of the present invention to provide a digital video signal recording apparatus in which the error correction ability and the error correction ability are further improved by performing two-stage shuffling.

[Means for solving problems]

According to the present invention, in a digital video signal recording apparatus for recording a component video signal on a recording medium by a rotary head, a luminance signal component of a component video signal and first and second color signal components are supplied, and a predetermined number of screens are displayed. Screen dividing means for distributing the luminance component and the first and second color signal components so as to be divided, and the distributed luminance signal component and the first and second color signal components are respectively supplied from the screen dividing means, A plurality of multiplexing circuits that multiplex the luminance signal component and the first and second color signal components and then distribute and output to the first and second output channels, and the luminance supplied from each of the plurality of multiplexing circuits. A plurality of blocks that perform shuffling in block units so that the signal components and the first and second color signal components are aligned in the horizontal direction in the data diagonal direction. A block shuffling circuit is connected to each of the block shuffling circuits, and the luminance signal components and the first and second chrominance signal components of a plurality of blocks shuffled are arranged horizontally in a diagonal direction. An apparatus for recording a digital video signal, comprising: a plurality of field shuffling circuits for performing shuffling in units of fields; and a plurality of heads for recording output signals of the field shuffling circuits on a recording medium.

[Action]

The block shuffling performed by the block shuffling circuit changes the order of data from the original order and prevents continuous data from becoming error data. The field shuffling circuit puts the shuffled data of one field or one frame in block units into an order different from the original order. Due to the field shuffling, the recording positions of continuous data are further separated, and it is possible to favorably perform error correction by interpolating error data with an average value of correct data located before and after the data. Further, it is possible to prevent a plurality of data included in the same code sequence from being concentrated and become error data, and improve the error correction capability.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. This embodiment is for recording / reproducing a component signal of a high definition television signal.

A high-definition television signal consists of a luminance signal (Y signal) and two color difference signals (CW signal and CN signal). When digitizing this component video signal, Y
The sampling frequency of the signal is 64.8 MHz, and the sampling frequencies of the CW signal and the CN signal are 32.4 MHz, respectively. Therefore, the amount of data of the digitized high-definition television signal becomes extremely large, and when recording it,
The screen is divided into four, and each screen is converted into a 2-channel data series. The resulting 8-channel data series is recorded on the magnetic tape as eight parallel tracks.

In FIG. 1, analog component video signals are supplied to the input terminals 1A, 1B and 1C. The component video signal is supplied to the A / D converter 2 and the A / D converter 2
In the above, each is converted into a digital signal with the above sampling frequency. Digital Y signal, CW signal,
The CN signal is supplied to the screen division circuit 3. As shown in FIG. 2, each of the component signals (Y signal, CW signal, CN signal) forming one screen is horizontally divided into four.

The component signals of the respective areas from the screen division circuit 3 are supplied to the recording processors 4A, 4B, 4C and 4D, respectively. Since these recording processors 4A to 4D have the same configuration as each other, the recording processor 4A will be described and the other processors will be described.
A description of 4B, 4C and 4D is omitted.

The recording processor 4A is provided with a multiplexing circuit 5 to which the component video signal in one area from the screen division circuit 3 is supplied. The multiplexing circuit 5 forms 2-channel serial data. FIG. 3A shows a component video signal from the screen division circuit 3.

As shown in FIG. 3A, parallel data of Y signal, CW signal, and CN signal is supplied from the screen division circuit 3 to the multiplexing circuit 5. Y1, Y2, Y3 ... Represent sampling data of Y signal, CW1, CW3, CW5 ... Represent sampling data of CW signal, CN1, CN3, CN5 ... Represent sampling data of CN signal Are shown respectively. The CW signal and the CN signal have a sampling rate that is half the sampling rate of the Y signal.

In the multiplexing circuit 5, the odd-numbered data of the Y signal and the even-numbered data of the Y signal are separated, and the CW signal and the CN signal are inserted into the empty time slots as shown in FIG. 3B. . The serial data of the data channel CH1 including the odd-numbered data of the Y signal and the serial data of the data channel CH2 including the even-numbered data of the Y signal are output from the multiplexing circuit 5.

Channel CH1 data is lock shuffling circuit 6A
And is rearranged (block shuffling) in one block. The output data of the block shuffling circuit 6A is supplied to the parity generation circuit 7A, and the error correction code is encoded. The data and parity from the parity generation circuit 7A are supplied to the field shuffling circuit 8A. Field shuffling circuit 8A
Thus, the arrangement of the data array included in one field is rearranged (field shuffling).

The serial data of the other channel CH2 from the multiplexing circuit 5 is the block shuffling circuit 6B, the parity generation circuit, as in the above-mentioned serial data of the channel CH1.
7B and field shuffling circuit 8B are sequentially passed.

Two-channel output data from the recording processor 4A is supplied to the data distribution circuit 9. Other recording processor 4
Two-channel data from B, 4C, and 4D are also supplied to the data distribution circuit 9. The data distribution circuit 9 outputs the data of eight channels for which recording processing has been performed to eight heads H1 to H8.
It is a circuit for distributing to. Data of eight head channels corresponding to each head from the data distribution circuit 9 is passed through the digital modulation circuits 10A to 10H, the recording amplifier, the recording / reproducing changeover switch 11 and the rotary transformer (not shown) to the heads H1 to H8. Is supplied to. The heads H1 to H8 are arranged close to each other on the rotating drum and simultaneously scan the magnetic tape. As described above, since the data distributed to the 8 channels is recorded, it becomes possible to record a digital high definition television signal having a high data rate.

Each of the reproduction signals of the heads H1 to H8 includes a rotary transformer (not shown), a recording / reproduction changeover switch 11, a reproduction amplifier,
It is supplied to the data distribution circuit 21 via the digital demodulation circuits 20A to 20H, respectively. The data distribution circuit 21 is provided to convert the eight head channels into the input data channels of the reproduction processors 22A, 22B, 22C and 22D. The reproduction processors 22A to 22D have the same configuration as each other.

Channel from head H1 via data distribution circuit 21
CH1 serial data is supplied to the field deshuffling circuit 23A. Field deshuffling circuit 2
In 3A, the operation opposite to the field shuffling at the time of recording is performed. The output data of the field deshuffling circuit 23A is supplied to the error correction circuit 24A, and the error data is corrected. The output data of the error correction circuit 24A is supplied to the block deshuffling circuit 25A.

The block deshuffling circuit 25A performs an operation reverse to that of the block shuffling at the time of recording. Output data of block deshuffling circuit 25A is error correction circuit 26A
The error data that is supplied to the error correction code and cannot be completely corrected by the error correction code is subjected to correction processing such as mean value interpolation. The output data of the error correction circuit 26A is supplied to the separation circuit 27.

Through the data distribution circuit 21, the reproduction data of the data channel CH2 from the head H2 is the same as the reproduction data of the data channel CH1, and the field deshuffling circuit 23
B, error correction circuit 24B, block deshuffling circuit
It is supplied to the separation circuit 27 via 25B and the error correction circuit 26B. The separation circuit 27 is a circuit for converting the Y signal, CW signal, and CN signal, which are respectively multiplexed into two channels, into parallel data. A component video signal of one area of the divided screen is obtained from the separation circuit 27.

The same processing as that of the reproduction processor 22A is performed from each of the other reproduction processors 22B, 22C and 22D via the data distribution circuit 21 with respect to the reproduction data of the data channels CH3 to CH8 from the heads H3 to H8. The data of the component video signal of each screen area from the reproduction processors 22A to 22D is supplied to the screen synthesis circuit 28. From this screen synthesis circuit 28, digital Y signal, CW signal and CN signal included in one screen are obtained, and this digital component video signal is
It is supplied to the D / A converter 29. Output terminal 30 of D / A converter 29
An analog component video signal is extracted to each of A, 30B, and 30C.

Block shuffling performed in the block shuffling circuit 6A of the recording processor 4A will be described with reference to FIG.

As shown in FIG. 4A, the serial data from the multiplexing circuit 5, for example, 56 sampling data is (7 ×
They are arranged in one block BI in a matrix of 8). Fourth
The numbers in FIG. A indicate the input order (indicated by →) of each sampling data of the input data. Each block BI is shuffled to form an output block BO shown in FIG. 4B.

The block shuffling is a rearrangement of the data which is arranged in the diagonal direction as the output data BO by arranging the sampling data of the input block BI in the horizontal direction as shown by → in FIG. 4B. For block shuffling, a memory that stores one block of data is required. The data in the output block BO is transmitted as the output data sequentially from the first row.

By performing this block shuffling, it is possible to prevent the sampling data from continuously becoming error data in the order of the original data. However, when a long burst error occurs due to a long dropout or the like, continuous sampling data may become error data, and the error correction may not be improved. To solve this problem, the field shuffling circuit 8A
Each data contained in the field is shuffled.

The field shuffling will be described with reference to FIG. In FIG. 5, for simplification of description, one field of data and error correction are performed by four blocks BI1, BI2, BI3, BI4 (shown in FIG. 5A) having the same size as the block shuffling block. Including the parity of the government name) is configured. The 56 pieces of data included in each of the four input blocks BI1 to BI4 are numbered in the order of input to the field shuffling circuit 8A.
The input blocks BI1 to BI4 shown in FIG. 5A are converted into the output blocks BO1 to BO4 shown in FIG. 5B.

The field shuffling outputs the sampling data arranged in the diagonal direction of the input blocks BI1 to BI4 to the output block BO.
This is a process of rearranging 1 to BO4 arranged in the horizontal direction. For example, the first sampling data (1) in the diagonal direction of each of the input blocks BI1 to BI4 is the first sampling data of the output block BO1.
The second sampling data (10) of the input blocks BI1 to BI4 in the diagonal direction are arranged in the first row of the output block BO1, and then the second sampling data of the input blocks BI1 to BI4 are arranged in the first row. The third sampling data (19) in the diagonal direction is arranged in the second row of the output block BO1. The same shuffling is performed thereafter.

Field memory is used for field shuffling. Field shuffled data,
That is, the respective data of the output blocks BO1 to BO4 are transmitted in order starting from the first row of the block BO1. Due to this field shuffling, the position of continuous sampling data is further moved away.

The block shuffling and the field shuffling are independently performed in each of the eight data channels. Further, the size of one block is actually larger than the size described above, for example, (48 × 50), and the number of blocks in one field is more than four. Is.

FIG. 6 shows conversion of data channels and head channels (so-called head interleaving) performed in the data distribution circuit 9.

FIG. 6A shows the data contained in each of the eight data channels CH1 to CH8 supplied from the recording processors 4A to 4D to the data distribution circuit 9. The M (= 8) pieces of data of each data channel are distributed to the eight head channels. For example, eight continuous data D ₁ 1, D ₁ 2, D ₁ 3 ... D ₁ 8 of the data channel CH1 are distributed to eight head channels as shown in FIG. 6B. Next, 8 consecutive data D ₂ 1, D of data channel CH2
₂ 2, D ₂ 3 ... D ₂ 8 are distributed to eight head channels as shown in FIG. 6B. Thereafter, the same distribution processing is performed by the data distribution circuit 9.

This head interleaving is performed to prevent many errors from occurring in only a specific data channel due to variations in head characteristics.

The present invention is applicable not only to recording / reproducing of digital high-definition television signals, but also to recording / reproducing of component video signals of NTSC system or PAL system.

〔The invention's effect〕

According to the present invention, shuffling in block units and 1
Since the shuffling in field units or in 1 frame units is doubled, it is possible to improve the error correction ability and the error correction ability. That is, as a result of field shuffling and block deshuffling of the reproducing circuit, error sampling data can be prevented from concentrating in both the vertical direction and the horizontal direction on the reproducing screen, and good error correction can be performed. It is possible to prevent error data from concentrating on the same code sequence of the correction code, and increase the number of cases in which error correction can be performed.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a schematic diagram for explaining processing of screen division when recording a high-definition television signal, and FIG. 3 is an embodiment of the present invention. 4 is a schematic diagram for explaining multiplexing of component video signals in FIG. 4, FIG. 4 is a schematic diagram for explaining block shuffling in one embodiment of the present invention, and FIG. 5 is in an embodiment of the present invention. FIG. 6 is a schematic diagram for explaining the field shuffling, and FIG. 6 is a schematic diagram for explaining the head interleave in one embodiment of the present invention. Description of main symbols in the drawings 1A, 1B, 1C: component signal input terminal of high-definition television signal, 4A ~ 4D: recording processor, 6A, 6B: block shuffling circuit, 8A, 8B: field shuffling circuit, 9: Data distribution circuit.

Claims (1)

(57) [Claims] 1. A digital video signal recording apparatus for recording a component video signal on a recording medium by a rotary head, wherein a luminance signal component and first and second color signal components of the component video signal are supplied to a predetermined screen. Screen dividing means for dividing the luminance component and the first and second color signal components so that the luminance component and the first and second color signal components are divided into the respective screen divisions. A plurality of multiplexing circuits which are supplied from the means, multiplex the luminance signal component and the first and second chrominance signal components, and then distribute and output to the first and second output channels; The luminance signal component and the first and second chrominance signal components respectively supplied from the circuit are aligned in the horizontal direction. A plurality of block shuffling circuits for performing the shuffling, and data connected in the diagonal direction of the luminance signal component and the first and second color signal components of the plurality of block shuffled blocks respectively connected to the block shuffling circuit. A plurality of field shuffling circuits that perform shuffling in field units so that the fields are arranged in the horizontal direction, and a plurality of heads that record the output signals of the field shuffling circuits on a recording medium. Video signal recording device.