JP2508976B2 - Reset device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reset device for electronic equipment, and more particularly to improvement of a reset device for a computer system.

[0002]

2. Description of the Related Art An electronic device using a microprocessor typified by a so-called personal computer is generally provided with a reset switch for initializing the system after power is turned on. It had only the function dedicated to the initialization of, and did not have other functions at the same time. On the other hand, among the electronic devices using the microprocessor as described above, in many cases, the system settings of a device having a display unit such as a CRT can be set on the screen of the display unit. And in such a device,
For example, a program that the microprocessor executes to press a specific key on the keyboard at power-on, or, if the power is already on, to press multiple specific keys. Detected by
A so-called menu screen for system settings was displayed.

[0003]

However, if the switch for resetting and the switch for system setting are separately provided as described above, if only the operability is focused, the user, especially For those who are unfamiliar with the kind of equipment, it has the advantage of being easy to use.
Providing a dedicated key for one function increases the number of parts and raises the cost of the device, and the space allocated to each part becomes even smaller in the limited mounting space. There is a problem that there is a fear of arranging parts with low operability. In addition, if the system setting screen is obtained by operating a plurality of keys, the operability is rather deteriorated. Therefore, for example, it is conceivable to provide a dedicated key for calling the menu screen for system setting, but it not only requires a mounting space, but also increases the number of parts, which eventually leads to an increase in the price of the device. There was a problem of leaving.

The present invention has been made in order to solve such a conventional problem, and it becomes possible for the reset switch to have not only system initialization but also a plurality of functions, and to be sure even when a program runs out of control. It is an object of the present invention to provide a reset device capable of resetting a system.

[0005]

In order to achieve the above object, the reset device of the present invention counts the reset switch means for generating a signal each time the switch is operated and the number of times the signal is output from the reset switch means. Then, when the count value reaches a set value, a count detection means for outputting a detection signal and a reset monitoring pulse for outputting a pulse signal of a constant width by the operation of the reset switch means performed first after system reset While the generating means and the reset monitor pulse generating means are outputting a pulse having a constant width, a detection signal indicating that the number of signal outputs from the reset switch means has reached a set value is output from the count detecting means. In this case, a decoding means for outputting a decoding signal as a system reset signal is provided. In still another aspect, the count detection unit is set with a plurality of set values as a count value of the number of times the signal is output from the reset switch unit, and the count value of the signal from the reset switch unit is set to a predetermined set value. When it reaches, it outputs a detection signal, and the decoding means outputs a count value indicated by the detection signal from the count detection means, which is output while the reset monitoring pulse generation means outputs a pulse having a constant width. According to the configuration, decoded signals having different pulse widths are output.

[0006]

According to the present invention, the reset switch means is operated a predetermined number of times, that is, a preset number of times in the count detecting means, while the pulse of the constant width generated by the reset monitoring pulse means is being output. And a decoding signal is output from the decoding means. By using this decoding signal as a system reset signal, the operation of the reset switching means is performed when the reset switching means is operated a number of times other than the set value of the counting detection means. It is possible to start the operation other than the system reset.

[0007]

Embodiments of the present invention will now be described in detail with reference to the drawings. The configuration of this reset device is shown in FIG. As shown in FIG. 1, the present reset device includes a reset switch unit 2 for performing a system reset of a microcomputer system mainly composed of a CPU 1, and a counter unit 3 for counting the number of times the reset switch unit 2 is activated.
A reset monitor pulse generator 4 for generating a pulse having a constant width when the reset switch unit 2 is activated, and a decoder unit 5 for decoding the output signals of the counter unit 3 and the reset monitor pulse generator 4. ing.

The reset switch section 2 generates a reset switch activation pulse, for example, each time the user depresses an operation section (not shown). In the present embodiment, as shown in FIGS. 2A and 2B, when the reset switch unit 2 is activated, the logic High state is changed to the logic Lo state.
A so-called negative logic signal is output which falls to the state of w and is in the state of logic low for a certain period of time. It should be noted that the signal output from the reset switch unit 2 is set in order to prevent malfunction of peripheral circuits.
It is assumed that noise has been removed by known / known circuit technology.

The counter section 3 has the number of times of activation of the reset switch section 2, that is, in the present embodiment, a logical Low.
The number of times the negative logic signal is output is counted, and when the count value reaches a preset number, for example, W times, a logic low signal is output as a detection signal as described later. ing.

The reset monitor pulse generator 4 generates a reset monitor pulse having a constant pulse width when the reset switch unit 2 is first activated after a system reset, and the pulse width can be arbitrarily changed. It is what This reset monitoring pulse generator 4
Is realized by using, for example, a monostable multivibrator or a programmable counter, or by adopting a configuration in which the counter value is set by software. Both the reset monitor pulse generator 4 and the counter 3 described above operate in synchronization with a synchronous clock pulse (hereinafter referred to as "synchronous CLK") input from the outside.

The decoder unit 5 outputs the system reset signal when the counter unit 3 detects the count value W as described above while the reset monitoring pulse signal having the constant pulse width is output from the reset monitoring pulse generating unit 4. Is output (details will be described later).

FIG. 2 shows a timing chart in the main part of this apparatus, and the operation of this apparatus will be described below with reference to the figure. First, a case where the reset switch unit 2 is activated only once while the reset monitor pulse generator 4 outputs a reset monitor pulse having a constant pulse width will be described with reference to FIG. When the reset switch unit 2 is activated, its output is logical Hi.
It falls from gh to logic low, and becomes logic high again after a fixed time. In the reset monitor pulse generator 4, the output of the reset switch unit 2 is logical Hi.
After falling from gh to logic low, the logic low output of the reset switch unit 2 is read at the rising edge of the first input synchronization CLK, so that the reset monitoring pulse of logic low for a preset time width is read. Will be output.

The negative logic output of the reset monitor pulse generator 4 can be used as, for example, an interrupt signal of the CPU 1. When this signal is input to an interrupt controller (not shown) of the system, the CPU 1 Interrupt processing will be started. Then, in the interrupt processing, it is determined that the interrupt request is generated due to the user activating the reset switch unit 2. In this case, the firmware is programmed so as to be in a standby state for a proper time. This is because there is a possibility that the system reset signal is generated after the generation of the interrupt based on the activation of the reset switch unit 2 by the user's operation described above. There is no problem as long as this waiting time is longer than the pulse width of the reset monitoring pulse generated from the reset monitoring pulse generator 4.

On the other hand, in the counter unit 3, immediately after the output of the reset switch unit 2 changes from logic High to logic Low, the logic Low of the reset switch unit 2 is read at the rising edge of the first input synchronization CLK. As a result, the count value becomes 1. Since the count value of the counter unit 3 has not yet reached the set value w at this point, the output of the counter unit 3 does not change and the logic H
It remains high.

If it is assumed that the reset switch section 2 has not been activated since the reset monitoring pulse generating section 4 has finished outputting the reset monitoring pulse having a constant pulse width, the counter section is eventually activated. Since the count value of 3 remains 1, the output of the counter unit 3 remains at the output even if the reset monitoring pulse generation unit 4 finishes outputting the reset monitoring pulse.
It remains at logic high.

In the decoder section 5, an inverted output of the logical sum of the output of the counter section 3 and the reset monitoring pulse from the reset monitoring pulse generating section 4, that is, in other words,
As a result of the logical product of the negative logic inputs, the output is a logic H
The high state is maintained without being affected by one operation of the reset switch unit 2.

As described above, when the reset switch unit 2 is activated only once, the CPU 1 may be caused to continue the processing without performing the system reset. In this case, for example, a CRT (not shown) is used. By displaying the system setting screen on the screen, it is possible for the user to recognize that one activation of the reset switch unit 2 functions as a call switch for the system setting screen.

Next, during the output period of the reset monitoring pulse,
The reset switch unit 2 sets the count value W of the counter unit 3 to W.
The case of being activated twice will be described with reference to FIG. The point that a reset monitor pulse that functions as an interrupt signal is generated by the first activation of the reset switch unit 2 is the same as in the case of FIG. 2A. When the reset switch unit 2 is activated for the Wth time, in the counter unit 3, this logic Low is read at the rising edge of the synchronous CLK input first after the output of the reset switch unit 2 becomes the logic Low, and the count is calculated. The numerical value is W. At the same time, the output of the counter section 3 falls from the logic High to the logic Low.

As described above, the decoder section 5 of the present embodiment is in a state where the reset monitoring pulse is generated from the reset monitoring pulse generating section 4 and the count value of the counter section 3 reaches the set value. Since the reset monitoring pulse of logic low is output, in the example shown in FIG. 2B, the output of the reset monitoring pulse generator 4 changes from the time when the output of the counter 3 changes to logic low. Until the time of rising to the logic High, the signal of the logic Low is output from the decoder unit 5 as the system reset signal.

The output signal of logic low output from the decoder unit 5 can be used as a so-called system reset signal in a device of this type having a conventional CPU. That is, when the user activates the reset switch unit 2 once while the reset monitoring pulse is being output, the reset switch unit 2 operates as follows.
While performing a function as a screen call switch for displaying a system setting screen on a display unit such as a CRT (not shown), when the reset switch unit 2 is activated W times during the output of the reset monitoring pulse, the reset switch unit 2 is , Which will function as a system reset. In the present embodiment, the CPU 1 resets the counter unit 3 via the counter reset circuit 6 when system initialization occurs.
Specifically, the output of the counter unit 3 is set to logic High.

Next, a second embodiment will be described with reference to FIG. The same components as those shown in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.
In the following description, different points will be mainly described. In the second embodiment, in the counter unit 3 of the first embodiment shown in FIG. 1, only one count value can be set, and accordingly, the decoder unit 5 decodes only one kind of state. On the contrary, in the second embodiment, the first point is that the counter unit 30 can simultaneously set N count values and the decoder unit 50 can also decode N states. The embodiment is different from the embodiment. That is, the counter unit 3 according to the second embodiment.
0 is composed of, for example, N counter circuits 30A, each counter circuit 30A is set with a different count value, and when the set count value is reached, a logical low signal is output at the output. In terms of output,
It is the same as the counter unit 30 of the first embodiment shown in FIG.

The decoder section 50 is adapted to decode the N output signals from the counter section 30. That is, in the present embodiment, the pulse width of the signal output from the decoding unit 5 differs depending on the value counted by the counter unit 3.

Next, the operation of the apparatus of the second embodiment will be described. First, when the reset switch unit 2 is activated once, the reset monitoring pulse is generated for a certain period from that point, which is the same as the first embodiment shown in FIG. Then, while the reset monitoring pulse is being generated, the count value of the counter unit 30 reaches any of the N count values set in the counter unit 30, so that the decoder unit 50 obtains the count value. A decode signal having a corresponding pulse width can be obtained. Then, by setting the operation in advance by the software or the firmware so that the CPU 1 performs the operation according to the decoding result, one reset switch unit 2 can perform N operations (count values that can be simultaneously set in the counter unit 30). Number) can be set.

In the above embodiment, the counter section 30
The operation of the reset monitor pulse generator 4 is performed by the synchronous CLK.
However, the operation is not limited to this, and the operation may be performed at the falling edge of the synchronous CLK. Further, although the counter units 3 and 30, the reset monitor pulse generating unit 4 and the decoder units 5 and 50 of the above-described embodiment are set to operate with reference to negative logic, of course, this is also limited to negative logic. It is not necessary, and operating on a positive logic basis does not change the essence of the invention. Further, in the above-described embodiment, the case where the present invention is applied to the system reset in the microcomputer device has been described, but the present invention is not limited to such a case, and can be applied to other devices, and a general-purpose reset. It is applicable as a device.

Next, specific circuit examples of the counter section 3, the reset monitoring pulse generating section and the decoder section 5 described above will be described with reference to FIGS. 4 and 5. First, the counter unit 3 is formed of a hexadecimal counter with four D-type flip-flops as main constituent elements. The counter unit 3 is provided with a CPU via a counter reset circuit 6.
It is a so-called down counter capable of setting count values of 1 to 16 by 1. Here, the conditions of the flip-flop, which is the main constituent element of the counter unit 3, are the D-type flip-flop if the so-called direct reset method, the reset priority method, and the rising edge detection are satisfied. It need not be limited to. Further, in this circuit example, the set value of the counter unit 3 is 3.

Further, the counter section 3 outputs the output signal of the reset switch section 2 to the synchronization C of the D-type flip-flop.
It is configured to operate as an LK.

The reset monitor pulse generator 4 is constructed by using an LS123 which is an IC of a one-shot multivibrator, and its output pulse width is set by the size of a so-called external resistor 7 and capacitor 8. Is. In this specific circuit example, the output of the reset monitoring pulse generator 4 is connected to the enable terminal of the analog switch circuit 9, and while the reset monitoring pulse having the logical value Low is applied to the enable terminal, the analog signal is output. The output signal of the reset switch unit 2 is input to the counter unit 3 via the switch circuit 9.

Next, the operation of this specific circuit example will be described with reference to FIG.
Will be described with reference to. Here, FIG. 5A shows the case where the reset switch unit 2 is operated only once during the output of the reset monitoring pulse, and FIG. 5B shows the case where the reset switch unit 2 operates the set number of times during the output of the reset monitoring pulse. These are the cases in which they have been performed. First, the case where the reset switch unit 2 is operated only once during the output of the reset monitoring pulse will be described.

The presetting of the counter section 3 is performed by the system initialization which has occurred immediately before. That is, at the rise of the system initialization signal from logic low to logic high, a signal is input via the counter reset circuit 6 so that the outputs QA and QB of the D-type flip-flops are both 1. At this time, a reset monitor pulse of logic low is simultaneously generated. When the reset switch section 2 is operated once while the reset monitoring pulse is being output,
A logic low reset activation pulse is input to the counter section 2, and the counter section 2 decrements the set value by one at the rising edge of the reset activation pulse. In this embodiment, the counter unit 2 is configured so that the Q output of each D-type flip-flop becomes zero when counting by the set value.

When the reset switch section 2 is operated only once during the output of the reset monitoring pulse, the decode signal is not output and its output is the logic High.
It remains h.

Next, while the reset monitor pulse is being output, the reset switch section 2 is operated a predetermined number of times (3 in this embodiment).
Times) will be explained. The generation of the preset and reset monitoring pulses of the counter unit 2 is the same as in the case of FIG. 5 (a) described above, and therefore a repetitive description will be omitted, and the different points will be mainly described. If the reset switch unit 2 is operated three times during the output of the reset monitoring pulse, the count value of the counter unit 3 becomes zero at the third rising of the reset switch activation pulse from the logic Low to the logic High. A decode signal of logic low is output from the decode part 5, and at the rising of the reset switch activation pulse from logic low to logic high in association with the fourth activation of the reset switch part 2,
The output of the decode signal is ended. Although the present invention has been described with reference to the preferred embodiments, the present invention is not necessarily limited to the above embodiments.

[0032]

As described above, according to the reset device of the present invention, the reset switch means is set within a predetermined time.
When the reset switch means is operated other than the predetermined number of times, the system reset signal is output for the first time when the reset switch is operated a predetermined number of times. Since it is possible to perform a plurality of functions by one reset switch means, it is not necessary to provide an operation key for each function, which is different from the conventional one, so that the apparatus can be simplified and an inexpensive apparatus can be provided. be able to. In addition, it is possible to prevent the system from being reset immediately by only one operation of the reset switch means, so that an inadvertent system reset when the reset switch means is accidentally operated once is avoided. It is possible to obtain the effect that the safe operation of the device can be secured. Further, according to the present invention, since the reset operation is possible without using the CPU of the computer system, it is possible to reliably reset the system even when the program of the system runs out of control. .

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a main part of a reset device according to a first embodiment of the present invention.

FIG. 2 is a timing chart of a main part for explaining the operation of the reset device according to the first embodiment.

FIG. 3 is a block diagram showing a configuration of a main part of a reset device according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a specific circuit example of a reset device according to the present invention.

5 is a timing diagram of a main part for explaining the circuit operation shown in FIG.

[Explanation of symbols]

 1 CPU 2 reset switch section 3,30 counter section 4 reset monitoring pulse generation section 5,50 decoder section 6 counter reset circuit

Claims (2)

(57) [Claims] 1. A reset switch means for generating a signal each time the switch is operated, and the number of output times of the signal from the reset switch means is counted, and a detection signal is output when the count value reaches a set value.
Counting detection means for a reset monitor pulse generating means for outputting a pulse signal of predetermined width by the operation of said reset switch means made first after system reset by the reset monitor pulse generator pulse having a constant width is outputted While the signal is being output, the detection signal indicating that the number of signal outputs from the reset switch means has reached the set value is
When it is output from the count detection means, the system reset
A reset device comprising: a decoding unit that outputs a decode signal as a remote signal. 2. The reset detection means includes:
As a count value of the number of times the signal is output from the switch means.
A fixed value is set and the signal from the reset switch means is set.
The detection signal is output when the count value of reaches the specified value.
However , the decoding means is the reset monitoring pulse generating means.
Is output while a pulse of constant width is being output by
It responds to the count value indicated by the detection signal from the count detecting means.
2. The reset device according to claim 1, wherein the reset signals are also output with different pulse widths .