JP2512925B2 - Digital VTR - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital VTR, and more particularly to a digital VTR which encodes a digital video signal with a high efficiency code to compress the amount of information.

[Outline of Invention]

In the present invention, a plurality of predetermined length tracks are sequentially formed from one tape edge to the other tape edge, and then a plurality of predetermined length tracks are sequentially formed from the other tape edge to one tape edge. In a digital VTR that performs recording in which the operations that are formed are repeated,
On the tracks located on one tape edge and the other tape edge, the record data processed at a compression rate of about 1/2 of the compression rate of the digital video signal recorded on the other track is recorded and reproduced at high speed. The image quality is good.

[Conventional technology]

As one of the rotary head type VTRs, a structure has been proposed in which the rotary head moves up and down to sequentially form tracks of a predetermined length in the width direction of the magnetic tape. In this type of VTR, high-speed reproducing operation is performed by continuously scanning the tracks located on the upper or lower tape edge. Since the amount of information in the digital video signal is large, the above rotary head type VTR
When recording / reproducing is performed on the digital video signal by using, it is conceivable to compress the information amount of the digital video signal. For example, it is possible to use a high-efficiency coding device as described in Japanese Patent Application No. 60-268817, which performs variable-length coding by adapting to the dynamic range of a block.

A high-efficiency coding apparatus that performs coding adapted to the dynamic range of this block obtains a dynamic range defined by maximum and minimum values of a plurality of pixels included in the block, and divides the dynamic range into a plurality of level ranges. Then, the code signal corresponding to the level range to which the pixel data after the minimum value removal belongs is formed. In this case, the number of bits of the code signal is changed according to the dynamic range so that the maximum distortion generated when the quantization is performed becomes substantially constant.

High efficiency code (AD
(Referred to as RC) is suitable for a digital VTR because it can significantly reduce the amount of data to be transmitted. In particular,
The variable length ADRC can increase the compression rate.

[Problems to be solved by the invention]

However, even with variable length ADRC,
Since the original digital video signal for one frame, for example, is compressed and recorded in one track, deterioration of the image quality of the reproduced image cannot be avoided. In particular, during high-speed reproduction, only the track located at the tape edge is scanned to obtain a reproduced image, so that there is a drawback that the image quality is significantly deteriorated.

Therefore, it is an object of the present invention to pay attention to the fact that the track to be scanned is located on one side of the tape edge in the case of high-speed reproduction operation, and the track located on this tape edge is recorded on the other track. It is to provide a digital VTR capable of obtaining a reproduced image of high quality during high-speed reproduction by recording the record data whose compression ratio is reduced to about 1/2 of that of the record data.

[Means for solving problems]

In the present invention, a plurality of predetermined length tracks are sequentially formed from one tape edge to the other tape edge, and then a plurality of predetermined length tracks are sequentially formed from the other tape edge to one tape edge. In a digital VTR that performs recording in which the operations that are formed are repeated,
A quantizer circuit for encoding a high-efficiency code with a digital video signal at a first compression rate, and a high-efficiency code with a digital video signal at a second compression rate which is approximately 1/2 of the first compression rate. And a quantizing circuit for performing the encoding of the recording data processed by the second compression rate are recorded on the tracks located on one tape edge and the other tape edge, and other tracks not located on the tape edge are recorded. No 1 on the truck
The record data processed at the compression rate of is recorded.

[Action]

For each of the tracks formed other than the tape edge,
For example, a digital video signal for one frame has a variable length AD
It is compressed by RC, and this compressed record data is recorded. In addition, the compression rate of the track located at the tape edge is reduced to about 1/2 of the compression rate of the other tracks. Therefore, in the case of the track located at the tape edge, two tracks are equivalent to one frame. The digital video signal of is recorded. During high-speed reproduction, the track located at the tape edge is continuously reproduced, and the restored image is obtained from the data having a low compression ratio, so that a reproduced image of good quality can be obtained.

〔Example〕

A digital VTR to which the present invention is applied will be described in detail with reference to the drawings. This explanation is made according to the following items.

ADRC encoder and ADRC decoder b. Variable-length quantization and buffering c. Drum mechanism and recording pattern d. Modified example a. ADRC encoder and ADRC decoder In FIG. 1, for example, one sample is 8 at the input terminal indicated by 1. A digital video signal quantized into bits is supplied, and an input digital video signal is blocked by a blocking circuit 2
Is supplied to. The block circuit 2 converts the input digital video signal into a continuous signal for each two-dimensional block which is a unit of encoding. In the blocking circuit 2, for example, the screen of one frame of (570 lines × 720 pixels) is the second
As shown in the figure, it is subdivided into (M × N) blocks.
One block has a size of (4 lines × 4 pixels), for example, as shown in FIG. From the block formation circuit 2, a digital video signal converted into the order of blocks B ₁₁ , B ₁₂ , B _13, ... B _NM is generated.

The output signal of the blocking circuit 2 is supplied to a maximum value detection circuit 3 for detecting a maximum value MAX for each block, a minimum value detection circuit 4 for detecting a minimum value MIN for each block, and a delay circuit 5. The detected maximum value MAX and minimum value MIN are supplied to the subtraction circuit 6, and the dynamic range DR represented by (MAX-MIN = DR) is obtained from the subtraction circuit 6. The delay circuit 5 delays the data for the time required to detect the minimum value MAX and the minimum value MIN. The minimum value MIN is subtracted from the video data from the delay circuit 5 in the subtraction circuit 7, and the data PDI from which the minimum value has been removed is obtained from the subtraction circuit 7.

The data PDI after the removal of the minimum value is supplied to the quantization circuits 9A and 9B via the delay circuit 8. The quantization circuits 9A and 9B are supplied with data of the quantization widths Δa and Δb from the ROMs 11A and 11B, respectively. The quantization circuits 9A and 9B have a quantization width Δ
Variable-length ADR that quantizes the data PDI using a and Δb
Perform C encoding respectively. That is, in the quantization circuits 9A and 9B,
The pixel data PDI from which the minimum value MIN shared by the pixel data in the block is removed is gradually divided by the quantization widths Δa and Δb, and the variable number of bits is quantized according to the dynamic range DR of the block.

Since the quantization width Δb is 1/2 with respect to the quantization width Δa, the compression rate of the ADRC encoding performed by the quantization circuit 9B is the same as the compression rate of the ADRC encoding performed by the quantization circuit 9A. 1/2
Becomes That is, if the number of bits of the code signal DTa output from the quantization circuit 9A is (0 to 4 bits), the number of bits of the code signal DTb output from the quantization circuit 9B is (0
~ 8 bits).

Since the video signal in the block has a two-dimensional correlation and a three-dimensional correlation, the dynamic range DR is smaller than the original data value and is quantized with a bit number less than 8 bits. However, the quantization distortion is not noticeable. The quantization circuits 9A and 9B are composed of ROM, for example. From the quantizing circuits 9A and 9B, 4-bit and 8-bit code signals DTa and DTb, which are the maximum number of bits, are generated, respectively. The code signals DTa and DTb from the quantizing circuits 9A and 9B are supplied to the input terminals a and b of the switch circuit 14B, respectively. The code signal selected by the switch circuit 14B is supplied to the framing circuit 16.

Of the output signals of the quantizing circuits 9A and 9B, effective bits are selected in the framing circuit 16 in the subsequent stage. For this reason,
In the ROMs 11A and 11B, data Na and Nb indicating the number of bits of the block are formed together with the quantization widths Δa and Δb. The data Na and Nb are supplied to the input terminals a and b of the switch circuit 14A, respectively, and the data selected by the switch circuit 14A is supplied to the framing circuit 16. The switch circuits 14a and 14b are controlled by a control signal from the terminal 15. This control signal has different levels when the rotary head of the VTR scans a track located at the tape edge of the magnetic tape and when it scans another track. When recording the digital data from the output terminal 17 on the track located at the tape edge, the switch circuits 14A and 14B are connected to the input terminal b and the output terminal c, and the digital data are recorded on the tracks other than the track located at the tape edge. When recording, the input terminal a and the output terminal c are connected.

With a digital VTR, the transmission rate of recorded data is constant, so if you do not limit the amount of transmission data, some data cannot be recorded, or the compression rate becomes higher than necessary and the quality of the reproduced image deteriorates. To do Therefore, the buffering circuit 10 is provided, and the buffering circuit 10 checks the frequency distribution of the dynamic range DR of all the blocks of one screen to be ADRC encoded, and performs the optimum variable length encoding.

The dynamic range DR is supplied from the subtraction circuit 6 to the buffering circuit 10. In the buffering circuit 10, a threshold value T that keeps the transmission data rate constant
1, T2, T3, T4 are obtained, and the parameter code Pi corresponding to this threshold value is output. The parameter code Pi and the dynamic range DR of the block are supplied to the ROMs 11A and 11B, and the quantization widths Δa and Δb are read from the ROMs 11A and 11B, respectively. The ADRC encoding performed by the quantizing circuit 9B is the same as the ADRC encoding performed by the quantizing circuit 9A.
Although the compression rate is 1/2, the code signal DTb from the quantizing circuit 9B is recorded in two tracks located at the tape edge as described later, and therefore, common processing is performed for buffering. Is done.

The delay circuits 12 and 13 delay the dynamic range DR and the minimum value MIN until the optimum threshold value is obtained by the buffering circuit 10 and variable length quantization is performed. Parameter code Pi from buffering circuit 10 and delay circuit
Dynamic range DR and minimum value MIN from 12, 13 and data of bit number from switch circuit 14A and switch circuit 14B
And the code signal from the frame are supplied to the framing circuit 16.

The framing circuit 16 performs error correction coding on the code signal as variable length data and the additional codes Pi, DR, MIN as fixed length data, and adds a synchronization signal. Transmission data is obtained at the output terminal 17 of the framing circuit 16. One parameter code Pi is transmitted on one screen,
DR and MIN data are transmitted for each block, and the code signal DT is transmitted for each pixel. Further, in the framing circuit 16, as described above, the effective bit of the code signal from the switch circuit 14B is selected using the data indicating the number of bits from the switch circuit 14A.

The received data is supplied to the input terminal 21 shown in FIG. 4, and the frame decomposition circuit 22 causes the parameter code Pi, the dynamic range DR, and the code signal DT (DTa
Or DTb) and the minimum value MIN. Decoding circuit
A converter 23 converts each of the code signals DTa and DTb into a restoration level, contrary to the quantization circuits 9A and 9B of the ADRC encoder. The restoration level from the decoding circuit 23 is supplied to the addition circuit 25, the minimum value MIN is added to the restoration level, and the restored data from the addition circuit 25 is supplied to the block decomposition circuit 26. From the output terminal 27 of the block decomposing circuit 26, output data in the same order as the television signal is obtained.

b. Variable length quantization and buffering FIG. 5 explains variable length quantization performed in the quantization circuit 9A, in which T1, T2, T3, and T4 are thresholds that determine the number of allocated bits, respectively. is there. These thresholds are
(T4 <T3 <T2 <T1).

When the dynamic range DR is (DR = T4-1), as shown in FIG. 5A, only the maximum value MAX and the minimum value MIN are transmitted, and at the receiving side, the intermediate level L0 is set as the restoration level. It Therefore, as shown in FIG. 5A, when the dynamic range DR is (T4-1), the quantization width is Δ0. When the dynamic range DR is (0 ≦ DR ≦ T4-1), the number of allocated bits is 0 bit.

FIG. 5B shows the case where the dynamic range DR is (T3-1). Dynamic range DR is (T4 ≦ DR ≦ T3-1)
When, the number of allocated bits is 1 bit. Therefore, the detected dynamic range DR is divided into two level ranges, and the pixel data PDI after the minimum value of the block is removed.
Is examined using the quantization width (Δa = Δ1), one of the code signals “0” or “1” corresponding to the level range is assigned, and the restoration level is set to L0 or L1.

In the variable length coding shown in FIG. 5, the quantization width Δa becomes (Δ0 <Δ1 <Δ as the dynamic range increases.
Non-linear quantization that is increased to 2 <Δ3 <Δ4) is performed. Non-linear quantization increases the maximum distortion in a block having a small dynamic range where quantization distortion is easily noticed, and conversely increases the maximum distortion in a block having a large dynamic range, and the compression rate is made higher.

If the dynamic range DR is (T2-1), the fifth
As shown in FIG. C, the detected dynamic range DR is divided into four level ranges, and 2 bits (00) (01) (10) (11) are assigned to each of the level ranges. The level at the center of the level range is the restoration level L0, L1, L
2, L3. Therefore, the level range to which the data PDI belongs is examined using the quantization width (Δa = Δ2). When the dynamic range DR is (T3 ≦ DR ≦ T2-1), the number of allocated bits is 2 bits.

Further, when the dynamic range DR is (T1-1), the detected dynamic range DR is divided into eight level ranges as shown in FIG. 5D, and 3 bits are set for each level range. (000) (001) ... (111) are assigned, and the central level of each level range is set as the restoration level L0, L1 ... L7. Therefore, the quantization width Δa is Δ3
Becomes When the dynamic range DR is (T2 ≦ DR ≦ T1-1), the number of allocated bits is 3 bits.

Furthermore, when the maximum dynamic range is 255,
As shown in FIG. 5E, the detected dynamic range
DR is divided into 16 level ranges, 4 bits (0000) (0001) ... (1111) are allocated to each level range, and the central level of each level range is the restoration level.
L0, L1 ... L15. Therefore, the quantization width Δa is Δ4
Becomes When the dynamic range DR is (T1 ≦ DR ≦ 255), the number of allocated bits is 4 bits.

As the threshold values T1 to T4, for example, the following eleven sets which are distinguished by the parameter code Pi when the maximum transmission rate is (2 bits / pixel) are prepared.

Among the above thresholds, the set of thresholds specified by the parameter code P ₁ can minimize the quantization distortion.
The buffering circuit 10 obtains the frequency distribution of the dynamic range DR of all the blocks in one frame.
The total number of bits (generated information amount) of the code signal DTa (or DTb) when ADRC encoding is performed by sequentially applying the threshold value set indicated by the parameter code P ₁ to this frequency distribution.
Is calculated. This generated information amount is compared with a known data threshold value, and a set of threshold values having distortion as small as possible within a range not exceeding the data threshold value is determined.

That is, in the number of blocks included in the five ranges of the dynamic range DR divided by the threshold values T1 to T4,
The generated information amount is obtained by multiplying each of the block numbers excluding the block to which 0 bit is assigned by the assigned bit number. When this amount of generated information is compared with the data threshold value and exceeds the data threshold value,
A larger threshold set is applied and the amount of generated information is calculated in the same manner.

c. Drum mechanism and recording pattern FIG. 6 shows the outline of the drum mechanism of the rotary head type VTR in this embodiment. In FIG. 6, 31 is a tape guide drum. A magnetic tape (not shown) is wound around the peripheral surface of the tape guide drum 31, and the rotary head 32a,
32b scans the magnetic tape. The rotary heads 32a and 32b are rotated by the motor 33. Further, the tape guide drum 31 and the motor 33 are integrally moved up and down by the motor 34. 35
Is a gear for vertically moving the tape guide drum 31 and the motor 33 by the motor 34.

The recording pattern of the VTR having the above-mentioned drum mechanism is as shown in FIG. In FIG. 7, tracks having a track width W and a track length L are sequentially formed in the width direction of the magnetic tape indicated by 36 as indicated by arrows. For example, data for one frame is recorded on one track. However, in the case of a track located at the tape edge formed by hatching, data for one frame is recorded on two tracks.

During recording and normal reproduction, the rotary heads 32a and 32b scan the magnetic tape 36 in the order shown by the arrows. Also,
During high-speed reproduction, the tape guide drum 31 and the motor 33 are not moved up and down, and only the tracks located on one of the upper and lower tape edges with diagonal lines are continuously scanned. As described above, since the ADRC encoding compression rate of 1/2 is recorded on the tracks located at these tape edges, the restored data obtained during high-speed reproduction has good quantization distortion and good quality. Will be things. Since the track length assigned to one frame in the track located at the tape edge is doubled, the number of screens during high-speed playback is halved, but this is not a problem because it is not normal playback. Further, in the vertical track row having the track width W, the number of frames that can be recorded one by one is small, but when viewed from the entire recording time, the influence is small. Rather, even during normal reproduction, a high-quality restored data frame appears every predetermined number of frames, so that the reproduction image quality can be improved to some extent.

d. Modified Example The present invention can be applied to ADRC of a three-dimensional block. When a three-dimensional block is composed of, for example, two two-dimensional regions each belonging to two frames, the number of pixels in one block is doubled. In addition, in three-dimensional block ADRC,
For the purpose of increasing the compression ratio, it is determined whether or not there is motion between the two two-dimensional regions, and when there is a motion, the pixel data of the two two-dimensional regions, that is, encoding of all the pixel data in the block is performed. When there is no motion, a process of encoding pixel data of one two-dimensional area is performed. Further, a background memory is provided, and whether the background memory matches or does not match is determined, all the frames of the data in the block match, and when the data in this block differs from the data in the background memory, the background memory is updated, The present invention can also be applied to the case of using the method of ADRC encoding only the data of the mismatched frames. As the data stored in the background memory, the data located at the tape edge and having a low compression rate is used, and the stationary portion which requires the resolution and the low noise may be of good quality.

The present invention can also be applied to the case of performing the variable-length ADRC that performs the linear quantization that makes the maximum distortion constant, and the case of performing the ADRC after performing the sub-sampling to increase the compression rate.

〔The invention's effect〕

According to the present invention, for example, high-efficiency-encoded data having a lower compression rate than data recorded on other tracks is recorded on a tape edge track scanned during high-speed reproduction. It is possible to improve the playback image quality during high-speed playback.

[Brief description of drawings]

1 is a block diagram showing the configuration of an ADRC encoder according to an embodiment of the present invention, FIGS. 2 and 3 are schematic diagrams for explaining the blocks, FIG. 4 is a block diagram of an ADRC decoder, and FIG. FIG. 7 is a schematic diagram for explaining variable length quantization, FIG. 6 is a perspective view of a drum mechanism of a rotary head type VTR to which the present invention can be applied, and FIG. 7 is a rotary head type VTR to which the present invention can be applied.
It is a schematic diagram showing a recording pattern of. Description of main symbols in the drawings 1: Digital video signal input terminal, 2: Blocking circuit, 3: Maximum value detection circuit, 4: Minimum value detection circuit, 6,7: Subtraction circuit, 9A, 9B: Quantization circuit , 10: Buffering circuit.

Claims (1)

(57) [Claims] 1. A plurality of tracks of a predetermined length are sequentially formed from one tape edge toward the other tape edge,
Next, in a digital VTR for recording in which the operation of sequentially forming a plurality of tracks of a predetermined length from the other tape edge to the one tape edge is repeated, a digital video signal is transferred at a first compression rate. A means for encoding a high efficiency code, and the digital video signal is approximately 1 / th of the first compression rate.
And a means for performing encoding of the high efficiency code with a second compression rate of 2. The tracks located on the one tape edge and the other tape edge are processed at the second compression rate. Recorded data is recorded, and the recorded data processed at the first compression rate is recorded on other tracks not located at the tape edge.
R.