JP2513018B2 - Semiconductor integrated circuit and manufacturing method thereof - Google Patents
Semiconductor integrated circuit and manufacturing method thereofInfo
- Publication number
- JP2513018B2 JP2513018B2 JP1037656A JP3765689A JP2513018B2 JP 2513018 B2 JP2513018 B2 JP 2513018B2 JP 1037656 A JP1037656 A JP 1037656A JP 3765689 A JP3765689 A JP 3765689A JP 2513018 B2 JP2513018 B2 JP 2513018B2
- Authority
- JP
- Japan
- Prior art keywords
- light
- resin
- film
- integrated circuit
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/015—Manufacture or treatment of bond wires
- H10W72/01515—Forming coatings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Light Receiving Elements (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、光感応素子外部からの光が入射するように
透光性樹脂で封止した光感応素子を含む半導体集積回路
およびその製造方法に関する。Description: TECHNICAL FIELD The present invention relates to a semiconductor integrated circuit including a photosensitive element sealed with a translucent resin so that light from the outside of the photosensitive element is incident, and a method for manufacturing the same. Regarding
光感応素子とその信号を処理する回路部とを同一基板
上に作り込んだ半導体集積回路をパッケージングするに
は、光感応素子部に外部からの光を入射させる容器を用
いる方法もあるが、透光性樹脂でモールドすればそれに
比して安価にできる。In order to package a semiconductor integrated circuit in which a light sensitive element and a circuit portion for processing the signal are formed on the same substrate, there is a method of using a container that allows light from the outside to enter the light sensitive element portion. Molding with a translucent resin makes it possible to reduce the cost.
光感応素子を含む半導体基板を透光性樹脂へモールド
する場合、樹脂に密着性強化剤などの添加物を混入する
ことは透光性を保持することができず、また半導体基板
表面には配線その他で凹凸が存在するため、モールド樹
脂に剥離,亀裂等が発生しやすく、光感応素子の光学的
特性の変動が大きく外観不良率が約50%と低い。さらに
使用中にも樹脂に基づく進行性の不良も発生し、信頼性
の点で問題があった。When a semiconductor substrate containing a photosensitive element is molded into a translucent resin, it is not possible to maintain translucency by mixing additives such as adhesion enhancers into the resin, and wiring on the surface of the semiconductor substrate In addition, since there are irregularities, peeling and cracks are likely to occur in the mold resin, the optical characteristics of the photosensitive element fluctuate greatly, and the appearance defect rate is as low as about 50%. Further, during use, progressive defects due to the resin also occurred, and there was a problem in terms of reliability.
本発明の目的は、従来技術で多発している半導体基板
とモールド樹脂の界面における剥離,亀裂の防止、含ま
れる光感応素子の光学的特性の安定化、さらに進行性の
不良を防止することによる信頼性の向上した半導体集積
回路およびその製造方法を提供することにある。The object of the present invention is to prevent peeling and cracks at the interface between the semiconductor substrate and the mold resin, which are frequently generated in the prior art, to stabilize the optical characteristics of the photosensitive element included therein, and to prevent progressive defects. An object of the present invention is to provide a semiconductor integrated circuit having improved reliability and a method for manufacturing the same.
上記の目的の達成のために、本発明による半導体集積
回路は、透光性注型用樹脂によってパッケージされる半
導体基板の光感応素子部表面に接して膜厚2μm以上、
20μm以下の範囲の透光性樹脂が塗布され、光感応素子
部以外の前記半導体基板表面に接して遮光性樹脂が塗布
されているものとする。また本発明による半導体集積回
路の製造方法は、光感応素子を含む半導体集積回路基板
を樹脂によりパッケージングする際に、半導体基板の表
面に遮光性ポリイミド樹脂を塗布する工程と、該遮光性
ポリイミド樹脂をパターニングして光感応素子部表面の
遮光性ポリイミド樹脂を除去する工程と、透光性ポリイ
ミドを塗布して表面を平坦化する工程と、基板を囲んで
透光性注型用樹脂をモールドする工程とを有するものと
する。To achieve the above object, a semiconductor integrated circuit according to the present invention has a film thickness of 2 μm or more in contact with the surface of a photosensitive element portion of a semiconductor substrate packaged with a transparent casting resin.
It is assumed that a light-transmissive resin having a range of 20 μm or less is applied, and a light-shielding resin is applied in contact with the surface of the semiconductor substrate other than the photosensitive element portion. Further, the method for manufacturing a semiconductor integrated circuit according to the present invention includes a step of applying a light-shielding polyimide resin to the surface of the semiconductor substrate when packaging the semiconductor integrated circuit substrate including a photosensitive element with a resin, and the light-shielding polyimide resin. Patterning to remove the light-shielding polyimide resin on the surface of the light-sensitive element, applying light-transmitting polyimide to flatten the surface, and molding a light-transmitting casting resin around the substrate. And a process.
光感応素子の上に塗布されるインナーコートとしての
透光性樹脂膜の膜厚を2μm以下とすると膜厚のばらつ
きにより素子表面の被覆が十分でなく、接着性とひずみ
の緩和に対しては薄すぎ、剥離の原因となる。20μm以
上となるとキュア後の膜質均一性が不十分であり、内部
の溶剤,水分の除去,重合反応等の反応が十分進行せ
ず、漏れ電流の増加が観測される。塗布される樹脂とし
て少なくとも光感応素子の表面では透光性であるポリイ
ミド樹脂を用いると、ポリイミド樹脂は有機物,無機物
との密着性がよいので、基板表面によく密着する。さら
に、その上にエポキシ樹脂のような透光性樹脂をモール
ドする場合、注型樹脂はポリイミド樹脂面によく密着
し、剥離,亀裂が生ずることがない。If the thickness of the translucent resin film as an inner coat applied on the light-sensitive element is 2 μm or less, the element surface is not sufficiently covered due to the variation in the film thickness, and the adhesion and the relaxation of strain are reduced. It is too thin and may cause peeling. When the thickness is 20 μm or more, the uniformity of the film quality after curing is insufficient, the reactions such as removal of internal solvent and water, and the polymerization reaction do not proceed sufficiently, and an increase in leakage current is observed. When a polyimide resin that is translucent at least on the surface of the photosensitive element is used as the resin to be applied, the polyimide resin has good adhesion to organic substances and inorganic substances, and therefore adheres well to the substrate surface. Furthermore, when a translucent resin such as an epoxy resin is molded thereon, the casting resin adheres well to the polyimide resin surface, and peeling or cracking does not occur.
第1図は本発明の参考例の半導体基板の端部を拡大し
た図である。光感応素子2を含む素子を形成したシリコ
ン基板1の表面には金属配線3およびパッド部4が設け
られ、パッド部を除いて例えば窒化膜のようなCVD保護
膜5で覆われている。この基板1はリードフレームのマ
ウント部6の上に固着され、パッド部4と第1図には図
示しないリードフレームのワイヤボンディング部と導線
7で接続されている。次いでジメチルアセトアミドを溶
剤とする5%濃度の透光性ポリイミド10を、基板1の周
辺および基板1上にマイクロディスペンサのノズル8を
走査しながら総量50μl滴下する。滴下後、ちっ素気流
中に一時間放置したのち加熱する。加熱はオーブン中で
100℃で1時間、200℃で1時間の加熱を行い、基板上に
厚さ2μm以上,20μm以下で屈折率1.7の透光性ポリイ
ミド被膜11を形成する。その結果、基板1の上の配線,
ワイヤボンディング部を覆い、基板周辺のフレーム6上
に延びる被膜が形成され、基板表面上の平坦化とフレー
ム面との段差の緩和化を達成される。FIG. 1 is an enlarged view of an end portion of a semiconductor substrate according to a reference example of the present invention. The metal wiring 3 and the pad portion 4 are provided on the surface of the silicon substrate 1 on which the elements including the photosensitive element 2 are formed, and the portion other than the pad portion is covered with a CVD protective film 5 such as a nitride film. The substrate 1 is fixed on the mount portion 6 of the lead frame, and is connected to the pad portion 4 and the wire bonding portion of the lead frame (not shown in FIG. 1) by the conductor wire 7. Then, a transparent polyimide 10 having a concentration of 5% and using dimethylacetamide as a solvent is dripped on the periphery of the substrate 1 and on the substrate 1 in a total amount of 50 μl while scanning the nozzle 8 of the microdispenser. After the dropping, leave for 1 hour in a nitrogen stream and heat. Heating in the oven
By heating at 100 ° C. for 1 hour and at 200 ° C. for 1 hour, a translucent polyimide film 11 having a thickness of 2 μm or more and 20 μm or less and a refractive index of 1.7 is formed on the substrate. As a result, the wiring on the substrate 1
A film covering the wire bonding portion and extending on the frame 6 around the substrate is formed, and flattening on the substrate surface and mitigation of the step between the frame surface are achieved.
さらにフレームマウント部6の裏面にも絶縁膜12をロー
ルコータを使用して塗布し、加熱して形成する。加熱は
表面上のポリイミド膜の加熱と同時に行うことが有効で
ある。この絶縁膜12はポリイミド膜に限らず透光性の必
要もないが、金属および注型樹脂との密着性のよいもの
を選ぶ必要がある。リードフレーム上に搭載したシリコ
ン基板は、このあと金型中に収容し第2図に示すように
屈折率1.55の透光性エポキシ樹脂13によりモールドす
る。ボンディングワイヤ7により接続されるリードフレ
ームのワイヤボンディング部の大部分は樹脂13の外に突
出して金属端子14を形成する。このパッケージングで
は、屈折率の組合わせが1.55/1.77となり、外光が光感
応素子上に達するまでの反射による損失が少なく、素子
の実質的感度が向上する。Further, the insulating film 12 is applied to the back surface of the frame mount portion 6 by using a roll coater and heated to form the insulating film 12. It is effective to perform heating at the same time as heating the polyimide film on the surface. The insulating film 12 is not limited to the polyimide film and does not need to have a light-transmitting property, but it is necessary to select a material having good adhesion to the metal and the casting resin. The silicon substrate mounted on the lead frame is then housed in a mold and molded with a translucent epoxy resin 13 having a refractive index of 1.55 as shown in FIG. Most of the wire bonding portion of the lead frame connected by the bonding wire 7 projects out of the resin 13 to form the metal terminal 14. In this packaging, the combination of the refractive indexes is 1.55 / 1.77, the loss due to reflection of external light until reaching the photosensitive element is small, and the substantial sensitivity of the element is improved.
第3図は本発明の実施例の半導体基板の端部を拡大し
た図である。先ず基板表面上に遮光性ポリイミドをスピ
ンコータで塗布し、フォトプロセスでパターニングを行
い、100℃,200℃,350℃で注型樹脂30分キュアして硬化
させ、遮光性ポリイミド膜15を形成する。パターニング
の際、光感応素子2の上およびパッド部4の上には窓明
けし、遮光性のポリイミド膜15が存在しないようにす
る。このポリイミド膜15の厚さは2μm程度が適当であ
る。次に透光性ポリイミドを用いてスピンコータで全面
に塗布し、ちっ素気流中に一時間放置後オーブンにより
100℃,200℃,350℃でそれぞれ30分キュア,硬化させ2
〜20μmの厚さの被膜11を形成する。このあと、通常の
フォトレジストを用いパッド部4の上に窓を有するパタ
ーニングをする。ひきつづき、この窓よりヒドラジンを
用いてパッド部上の被膜11を除去し、さらにフォトレジ
スト膜を東京応化(株)製商品名OMR剥離液を用いて除
去し、350℃,30分のベークを行う。これにより基体表面
保護膜としてのCVD膜5は必要とせず、遮光性および透
光性ポリイミド膜15,11に表面保護膜を兼ねさせる。ま
た遮光性ポリイミド膜は光感応素子以外の部分の金属膜
による遮光を不必要とする。露出したパッド部4はリー
ドフレームのワイヤボンディング部と導線7で接続され
る。リードフレームマウント部6の裏面に絶縁樹脂をロ
ールコータで塗布し、100℃30分,200℃30分の加熱で絶
縁膜12を形成することは第1図の場合と同様である。こ
のあと、第2図に示すように樹脂モールドすることも同
様である。FIG. 3 is an enlarged view of the edge portion of the semiconductor substrate according to the embodiment of the present invention. First, a light-shielding polyimide is applied on the surface of a substrate with a spin coater, patterned by a photo process, and cured by curing the casting resin for 30 minutes at 100 ° C., 200 ° C. and 350 ° C. to be cured to form a light-shielding polyimide film 15. At the time of patterning, a window is opened on the photosensitive element 2 and the pad portion 4 so that the light-shielding polyimide film 15 does not exist. A suitable thickness of this polyimide film 15 is about 2 μm. Next, use a spin coater to coat the entire surface with translucent polyimide, leave it in a nitrogen stream for 1 hour, and then in an oven.
Cure and cure at 100 ℃, 200 ℃, 350 ℃ for 30 minutes each 2
A coating 11 having a thickness of 20 μm is formed. Then, patterning having a window on the pad portion 4 is performed using a normal photoresist. Continuing on, the film 11 on the pad is removed from this window using hydrazine, and the photoresist film is removed using OMR stripper, trade name, manufactured by Tokyo Ohka Co., Ltd., and baked at 350 ° C for 30 minutes. . As a result, the CVD film 5 as the substrate surface protection film is not required, and the light-shielding and translucent polyimide films 15 and 11 also serve as the surface protection film. Further, the light-shielding polyimide film does not need to be shielded by the metal film in the portion other than the photosensitive element. The exposed pad portion 4 is connected to the wire bonding portion of the lead frame by the conductive wire 7. The insulating resin is applied to the back surface of the lead frame mount portion 6 by a roll coater, and the insulating film 12 is formed by heating at 100 ° C. for 30 minutes and 200 ° C. for 30 minutes, as in the case of FIG. After that, the same applies to resin molding as shown in FIG.
第4図は透光性ポリイミド樹脂を1μmの厚さに塗布
した場合で光感応素子の位置A部では塗膜の剥離があ
り、B部では剥離がなく、剥離のあったA部では感度が
B部より低下しており、膜厚が1μmでは薄すぎること
を示している。第5図はポリイミド膜厚さに対する漏れ
電流の比較で、定数を漏れ電流で割った値(相対値)が
膜厚が20μmを越えると小さくなり、膜厚が厚すぎると
漏れ電流が増加することがわかる。FIG. 4 shows a case where a translucent polyimide resin is applied to a thickness of 1 μm, the coating film is peeled off at the position A of the photosensitive element, there is no peeling at the portion B, and the sensitivity is at the peeled portion A. It is lower than that of the part B, indicating that a film thickness of 1 μm is too thin. Fig. 5 is a comparison of leakage current with respect to polyimide film thickness. The value (relative value) obtained by dividing the constant by the leakage current decreases when the film thickness exceeds 20 μm, and increases when the film thickness is too thick. I understand.
以上の結果から、透光性インナーコートとしてポリイ
ミド膜を用いた時、膜厚を2〜20μmにする必要がある
ことが明らかになったが、ポリイミド膜の代わりにシリ
コーン樹脂あるいはアクリル樹脂の塗膜をインナーコー
トとして用いる場合も同じ結果を得ている。From the above results, it is clear that when a polyimide film is used as the translucent inner coat, the film thickness needs to be 2 to 20 μm, but a coating film of silicone resin or acrylic resin is used instead of the polyimide film. The same result is obtained when is used as the inner coat.
本発明によれば、光感応素子を含み透光性樹脂の注型
によりパッケージングされる半導体集積回路の半導体基
板の光感応素子上に透光性樹脂、特にポリイミド樹脂か
らなる塗膜をインナーコートとして用いることにより、
基板表面の平坦化ができ、密着性強化剤を添加できない
注型用透光性樹脂をモールドして直接半導体基板に接触
させる場合と異なり、インナーコート膜の有機物,無機
物との密着性および表面平坦化の効果により、注型用樹
脂の剥離,亀裂の発生を防止でき、歩留まりの向上,信
頼性の向上をはかることができる。さらに、インナーコ
ート膜の膜厚を限定することによりこれらの効果を確実
にすることができる。According to the present invention, a coating film made of a light-transmissive resin, particularly a polyimide resin, is inner-coated on the light-sensitive element of a semiconductor substrate of a semiconductor integrated circuit that includes the light-sensitive element and is packaged by casting of a light-transmissive resin. By using as
Unlike the case of molding a translucent resin for casting, which can flatten the substrate surface and does not add an adhesion enhancer, and directly contact the semiconductor substrate, the adhesion of the inner coat film to organic and inorganic substances and the surface flatness Due to the effect of improvement, peeling and cracking of the casting resin can be prevented, yield can be improved, and reliability can be improved. Furthermore, these effects can be ensured by limiting the film thickness of the inner coat film.
また、ポリイミド膜を表面保護膜として兼用できるこ
と、遮光ポリイミド膜を光感応素子部以外の部分の遮光
膜に代替できることにより、透光性樹脂モールド光感応
半導体集積回路の製造に関して多大の経済的効果を与え
ることができる。In addition, since the polyimide film can also be used as the surface protective film and the light-shielding polyimide film can be replaced with the light-shielding film for the portion other than the light-sensitive element part, a great economic effect can be obtained in manufacturing a light-transmissive resin-molded light-sensitive semiconductor integrated circuit. Can be given.
第1図は本発明の参考例における半導体基板端部の拡大
断面図、第2図は本発明の実施例による半導体集積回路
の断面図、第3図は本発明の実施例における半導体基板
端部の拡大断面図、第4図はポリイミド膜の膜厚の薄い
場合の光感応素子の位置と光応答時間の関係線図、第5
図はポリイミド膜の膜厚と漏れ電流の大きさとの関係線
図である。 1:シリコン基板、2:光感応素子、3:配線、4:パッド部、
11:透光性ポリイミド膜、13:注型透光性エポキシ樹脂、
15:遮光性ポリイミド膜。FIG. 1 is an enlarged sectional view of an edge portion of a semiconductor substrate in a reference example of the present invention, FIG. 2 is a sectional view of a semiconductor integrated circuit according to an embodiment of the present invention, and FIG. 3 is an edge portion of a semiconductor substrate in an embodiment of the present invention. FIG. 4 is an enlarged cross-sectional view of FIG. 4, and FIG. 4 is a relationship diagram between the position of the photosensitive element and the photoresponse time when the thickness of the polyimide film is thin.
The figure is a relationship diagram between the film thickness of the polyimide film and the magnitude of the leakage current. 1: Silicon substrate, 2: Photosensitive element, 3: Wiring, 4: Pad part,
11: translucent polyimide film, 13: cast translucent epoxy resin,
15: Light-shielding polyimide film.
Claims (2)
る半導体基板の光感応素子部表面に接して膜厚2μm以
上、20μm以下の範囲の透光性樹脂が塗布され、光感応
素子部以外の前記半導体基板表面に遮光性樹脂が塗布さ
れていることを特徴とする半導体集積回路。1. A light-transmitting resin having a film thickness of 2 μm or more and 20 μm or less is applied in contact with the surface of a light-sensitive element portion of a semiconductor substrate packaged with a light-transmissive casting resin, except for the light-sensitive element portion. 2. A semiconductor integrated circuit, wherein a light-shielding resin is applied to the surface of the semiconductor substrate.
脂によりパッケージングする際に、半導体基板の表面に
遮光性ポリイミド樹脂を塗布する工程と、該遮光性ポリ
イミド樹脂をパターニングして光感応素子部表面の遮光
性ポリイミド樹脂を除去する工程と、透光性ポリイミド
を塗布して表面を平坦化する工程と、基板を囲んで透光
性注型用樹脂をモールドする工程とを有することを特徴
とする請求項1記載の半導体集積回路の製造方法。2. A step of applying a light-shielding polyimide resin to the surface of a semiconductor substrate when packaging a semiconductor integrated circuit substrate including a light-sensitive element with a resin, and patterning the light-shielding polyimide resin to form a light-sensitive element. Characterized in that it has a step of removing the light-shielding polyimide resin on the surface of the portion, a step of applying a transparent polyimide to flatten the surface, and a step of surrounding the substrate and molding a transparent casting resin. The method for manufacturing a semiconductor integrated circuit according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1037656A JP2513018B2 (en) | 1988-08-05 | 1989-02-17 | Semiconductor integrated circuit and manufacturing method thereof |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63-195489 | 1988-08-05 | ||
| JP19548988 | 1988-08-05 | ||
| JP1037656A JP2513018B2 (en) | 1988-08-05 | 1989-02-17 | Semiconductor integrated circuit and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02146750A JPH02146750A (en) | 1990-06-05 |
| JP2513018B2 true JP2513018B2 (en) | 1996-07-03 |
Family
ID=26376787
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1037656A Expired - Lifetime JP2513018B2 (en) | 1988-08-05 | 1989-02-17 | Semiconductor integrated circuit and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2513018B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10058593A1 (en) * | 2000-11-25 | 2002-06-06 | Bosch Gmbh Robert | Packaged electronic component and method for packaging an electronic component |
| DE102004060367A1 (en) * | 2004-12-15 | 2006-06-29 | Infineon Technologies Ag | Chip component has semiconductor body, element which can be switched and arranged in subarea of semiconductor body, integrated switching to take out a configuration from two configurations and also housing which surrounds semiconductor body |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6444653U (en) * | 1987-09-10 | 1989-03-16 |
-
1989
- 1989-02-17 JP JP1037656A patent/JP2513018B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02146750A (en) | 1990-06-05 |
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