JP2513616B2 - High frequency etching equipment - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a high-frequency etching apparatus used in, for example, a sputtering apparatus used in a semiconductor wafer process, and has a set value due to a matching error (mismatch) during high-frequency power supply. To an interlock control device for automatically detecting a power shortage to generate an error output and stopping the power supply.

[Technical Background of the Invention] With the increase in the number of wiring layers in a semiconductor wafer, an interlayer insulating film is often formed by a high frequency etching method. Further, a sputtering apparatus equipped with a high-frequency etching apparatus is often used so that wiring can be formed on a wafer and an insulating film as a pretreatment thereof can be formed in the same vacuum container (sputtering chamber).

Briefly describing the principle of the above high frequency etching method, after evacuating the inside of the container to a high vacuum, a predetermined gas is introduced so as to have an appropriate pressure, and a predetermined frequency and electric power are externally applied between the electrode pair in the container. A high frequency signal is applied to generate plasma due to discharge between the electrodes to etch the surface of the wafer held on one of the electrodes.

[Problems of background technology]

By the way, a matching circuit is provided for impedance matching between the high-frequency power source that supplies the high-frequency signal and the plasma, but if a matching error or the like occurs,
When the applied power becomes lower than the set value, the etching amount becomes insufficient and the etching cannot be performed well. Further, since the wafer product interlayer conduction resistance that is the target of the etching process at this time is often a defective wafer, there is a problem that the yield of the wafer is significantly reduced.

However, in the above-described sputtering apparatus, when plasma is generated within a certain time after the high frequency power is applied, a negative DC voltage (bias voltage) is generated in the vicinity of the cathode, so that the matching circuit control device detects this bias voltage. As a result, the wafer process controller generates a power-on signal indicating that power is being applied. In this case, conventionally, as long as the detected value of the bias voltage is a certain value or more, error display is not performed assuming that the normal discharge is performed, and the constant value is applied with the power applied at the set value. Was about 10% of the bias voltage generated by. Therefore, conventionally, a case where the applied power is insufficient due to a misalignment or the like is not accurately detected, so that a defective wafer is generated due to insufficient etching as described above, which is a factor of lowering the yield.

[Object of the Invention]

The present invention has been made in view of the above circumstances, and it is possible to accurately detect when the applied power of a high frequency signal is insufficient and stop the generation of an error output and the supply of the high frequency power. The present invention provides a high-frequency etching apparatus capable of improving reliability, improving yield, and improving operation efficiency of the apparatus.

[Outline of Invention]

The high-frequency etching apparatus of the present invention measures the elapse of a fixed time from the start of discharge by applying high-frequency power, and when the bias voltage generated by the generation of plasma by the discharge does not exceed the set value by the end of this time measurement, and When the bias voltage becomes lower than the set value during the etching after the time measurement is completed, the high-frequency power supply is stopped and the error output is controlled (interlock is applied). Interlock control It is characterized by comprising means.

As a result, the interlock is applied when the high frequency power is insufficient, the occurrence of etching defects can be prevented, and the reliability of the quality of products to be etched and the yield can be improved. Further, since an error output is generated during the interlock, the operator can easily manage the device and the operating efficiency of the device can be improved.

Example of Invention

An embodiment of the present invention will be described in detail below with reference to the drawings. In the figure, 1 is an etching chamber (sputtering chamber) for performing high frequency etching in a sputtering apparatus, 2 is a matching circuit, 3 is a matching circuit controller, 4 is a high frequency power source, and generates a high frequency signal of 13.56 MHz, for example. Reference numeral 5 denotes a process control device for controlling the etching process, which includes the etching chamber 1 through the matching circuit 2 from the high frequency power source 4.
It has a function of outputting a discharge start signal when discharge is started by applying high-frequency power between the electrodes, and a function of detecting when plasma is generated after the start of discharge and outputting a power-on signal. Also, the matching circuit control device 3 has a function of detecting a bias voltage generated near the cathode due to the plasma generation,
Is a bias meter for displaying the bias voltage detection output.

Reference numeral 10 denotes an interlock control circuit provided in the present invention. The photocoupler 11 is on / off controlled according to the presence or absence of the discharge start signal output of the process control device 5, and the on output of the photocoupler 11. A timer circuit 13 that starts operation in response to this, and turns on the built-in timer relay 12 when a preset fixed time elapses.
And a normally-closed contact 14 'of the bias relay 14 which is provided in the bias meter 6 and is turned on and off according to the result of judgment as to whether or not the bias voltage input exceeds an externally settable value. And the normally open contact 12 'of the timer relay 12 are both in the ON state, the interlock control relay 15 is supplied with the drive current satisfying the logical condition, and the normally closed contact 15' of the interlock control relay 15 On
An interlock relay control circuit 16 for controlling on / off of supply of a drive current to an interlock relay (not shown) for controlling the on / off state of the output of the high-frequency power source 4 according to the off state, and the above-mentioned interlock relay control circuit 16. Error output circuit 17 for generating an error output (alarm sound output, alarm display output, or other abnormal occurrence output) when the lock relay changes from the ON state to the OFF state, and whether or not the interlock function is activated can be set. To this end, the interlock function reset switch 18 is inserted in series with the photocoupler 11.

Next, the operation of the interlock control circuit 10 having the above configuration will be described. In the initial state, the normally open contact 12 'of the timer relay 12 is off, and the normally closed contact 14' of the bias relay 14 is in the off state.
Is on, the interlock control relay 15 is off, and its normally closed contact 15 'is on. When electric discharge is started in the etching chamber 1 by the power supply from the high frequency power supply, the process control device 5 outputs a discharge start signal. At this time, the interlock function reset switch 18
Is set to the ON state (function selection state), the discharge start signal drives the photocoupler 11 via the switch 18, and the photocoupler 11 is turned on. This starts the operation of the timer circuit 13, and after a certain time, the timer relay 12 turns on and its normally open contact
12 'is turned on. By this time etching room 1
If plasma is generated and the bias voltage exceeds the set value (for example, the bias voltage obtained in the normal state x 0.8), the bias relay 14 turns on and its normally closed contact 14 'turns off. Therefore, the interlock control relay 15 remains off, and the interlock operation is not performed. The magnitude of the bias voltage is instructed to the bias meter 14.

However, after that, when the applied voltage to the etching chamber 1 becomes insufficient for some reason and the bias voltage becomes lower than the set value, the bias relay 14 returns to the off state and its normally-closed contact.
14 'returns to ON state, so interlock control relay
When 15 is turned on and its normally closed contact 15 'is turned off, the interlock relay is turned off and the interlock is applied. That is, the power supply from the high frequency power supply 4 is cut off and the error circuit 17 produces an error output. Similarly, even when the bias voltage does not exceed the set value when the timer relay 12 is turned on (for example, when the matching circuit 2 is not matched), the bias relay
Since the normally closed contact 14 'of 14 remains in the on state, the interlock control relay 15 is turned on, and the interlock is applied as described above.

If the interlock function reset switch 18 is set to the off state (reset state), the discharge start signal is not input to the photocoupler 11, so the interlock control circuit 10 remains in the initial state and the interlock It will not be applied (reset).

Further, the specific configuration of the interlock control circuit is not limited to the above example, but may be configured using an electronic switch circuit, a microcomputer, or the like.

〔The invention's effect〕

As described above, according to the high-frequency etching apparatus of the present invention, when the bias voltage accompanying plasma generation does not exceed the set value within a certain time from the time of applying the high-frequency power, and during the etching even when the bias voltage exceeds the set value. Since it is set to interlock when it becomes lower than the set value,
This can largely contribute to the prevention of the generation of defective wafers due to the insufficient etching amount due to the insufficient applied power. Further, since the error output is generated when the interlock is applied, the operator can easily manage the device and improve the operation efficiency thereof. Therefore, it can be applied to the process of a wafer having a multilayer wiring, and can greatly contribute to the improvement of the reliability of the quality of wafer products and the yield.

[Brief description of drawings]

The drawing is a structural explanatory view showing a main part of an embodiment of a high-frequency etching apparatus of the present invention. 1 ... Etching room, 2 ... Matching circuit, 3 ... Matching circuit control device, 4 ... High frequency power supply, 5 ... Process control device, 10 ... Interlock control circuit, 12 ...
Timer relay, 13 …… Timer circuit, 14 …… Bias relay, 15 …… Interlock control relay, 16 …… Interlock relay control circuit, 17 …… Error output circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Nobuhiro Kajikawa 1-226 Nishishinjuku, Shinjuku-ku, Tokyo Within Tokyo Electron Ltd. (72) Jun Sugiyama 1-226 Nishishinjuku, Shinjuku-ku, Tokyo Issue: Tokyo Electron Limited (56) References JP-A-55-118637 (JP, A) JP-A-58-79722 (JP, A)

Claims (1)

(57) [Claims] 1. A high-frequency etching apparatus for etching a material to be etched on an electrode by applying high-frequency power to the electrode in an etching chamber in which a predetermined gas is introduced at a predetermined pressure to generate plasma by discharge between the electrodes. A timer circuit that counts a lapse of a certain time from the start of discharge; a first switch that operates when the timer circuit finishes timing; a detection circuit that detects a bias voltage generated by the plasma generation; a bias detection by the detection circuit A second switch that operates when the output is less than or equal to a set value, a control circuit that operates when both the first switch and the second switch are operating, and the high frequency wave according to the operation of the control circuit. An interface having means for cutting off the supply of electric power and means for generating an error output when the high-frequency power is cut off. RF etching apparatus characterized by comprising providing a click control circuit.