JP2514394B2 - Method of measuring shot length or alignment accuracy of shotgate - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] Regarding a method of measuring the gate length or the gate alignment accuracy of a Schottky gate in the manufacture of GaAs MES FET, the alignment of the gate length or the source region and the gate that cannot be visually measured is performed. , For the purpose of providing a method that can be measured without relying on visual observation, the step of forming an ion implantation layer on the compound semiconductor substrate, providing current electrodes (C, D) at both ends of the ion implantation layer, A step of providing two voltage electrodes (A, B) separated by an interval (L) between them, a finger of width (g) and a finger of this in the same step as the Schottky gate metal formation in the center of the current electrodes (C, D) When a current (I) is applied between the electrodes (C, D), it includes a step of forming a connected electrode (G), and the current (I) is applied to one electrode (C) and the other electrode (D). When The values of V _L , Va, and Vb are obtained, and the dimension g is g = L
_{(V L -Va-Vb) /} V a difference between the actual dimension and the mask design length determined by _L, also, d = L (Va-Vb ) / 2V L by alignment error between the ion implantation layer and the Schottky metal pattern And a method for measuring the gate length or alignment accuracy of the Schottky gate.

[Industrial applications]

The present invention relates to a method for measuring the gate length or gate alignment accuracy of Schottky gates in the manufacture of GaAs MES FETs.

[Conventional technology]

GaAs MES FET originally begins to form the mesa, to grow a large buffer layer of the resistance on a semi-insulating GaAs substrate, an n-type channel layer formed by epitaxial method thereon, the channel layer n ⁺ Make a mold layer and put the sauce on it
Forming a drain electrode and a gate between both electrodes was performed. If the gate length is shortened to improve the performance of the GaAs MES FET, the gate will be cut at the step of the mesa, and in order to solve it, the n-type layer is formed into a planar type by ion implantation of Si. It was way.
In order to improve the characteristics of GaAs MES FET, the gate length is becoming shorter and shorter, while the gate cross section is T-shaped (or mushroom type) to prevent the increase of the gate resistance due to the shortening of the gate length. It became so.

In addition, it is necessary to bring the position of the ion-implanted layer in the source region and the position of the gate as close to each other as possible and to align them with high accuracy. Referring to FIG. 3, source / drain regions 12 are formed in the channel layer 11 by ion implantation,
A source / drain electrode 13 is provided thereon, and a gate 14 having a T-shaped cross section is formed between these electrodes. In the recent technology, the gate length Lg of the gate is reduced to about 0.5 μm, and the distance l from the boundary where the source region and the channel layer have different concentrations to the gate is reduced to about 0.3 μm. Is designed to be about 1 to 1.5 μm to suppress an increase in gate resistance.

[Problems to be solved by the invention]

As described above, the source region and the gate are located close to each other, and high precision is required for the alignment. On the other hand, since the gate has a T-shaped cross section, it contacts GaAs when viewed from above. It is impossible to measure the gate length, and it has to be broken down and inspected by SEM.
Further, although the source region and the gate are aligned with respect to the same alignment mark, the boundary between the source regions cannot be seen, so that there is a problem that the positional deviation between the source region and the gate cannot be visually measured.

Therefore, an object of the present invention is to provide a method capable of measuring the gate length or the alignment between the source region and the gate, which cannot be measured by visual observation, without depending on visual observation.

[Means for solving problems]

The above problems are caused by the step of forming an ion-implanted layer on the compound semiconductor substrate and the current electrodes (C, D) at both ends of the ion-implanted layer.
And two voltage electrodes (A, B) separated by an interval (L) between them, and fingers of width (g) in the same step as the Schottky gate metal formation in the center of the current electrodes (C, D). And a step of forming an electrode (G) connected thereto, and when an electric current (I) is passed between the electrodes (C, D), one electrode (C) and the other electrode (D) from the electrode (G) When flowing into, the values of V _L , Va, and Vb are obtained, respectively, and the dimension g
Is determined by g = L (V _L −Va−Vb) / V _L, and the difference between the actual size and the mask design length is determined by d = L (Va−Vb) / 2V _L. It is solved by a method of measuring the gate length or the alignment accuracy of a Schottky gate, which is characterized by obtaining an alignment error with.

[Action]

In the present invention, an ion-implanted conductive layer is formed by utilizing ion implantation when forming a source region, a probe terminal is formed in this conductive layer, a Schottky finger is formed therein, and a resistance of the conductive layer is formed. The gate length or the distance between the source region and the gate is measured by electrically detecting the finger size and position shift by utilizing the difference from the resistance when a current is applied from the finger.

〔Example〕

Hereinafter, the present invention will be specifically described with reference to the illustrated embodiments.

According to the principle of the present invention, referring to FIG. 1 which is a plan view of a measuring element, first, a conductive layer pattern 21 of the measuring element is formed at the time of ion implantation of a source region of a GaAs MES FET. Although this pattern is formed only in one direction (X direction) in the drawing, it can be formed in two directions by forming it in the Y direction as necessary.

Next, when forming a Schottky gate of a GaAs MES FET, a detection electrode (gate electrode) pattern 22 connected to a finger 23 extending in a perpendicular direction is arranged in the center of the conductive layer pattern 21 of the measuring element, and a sandy area is shown in the figure. The ohmic electrodes A, B, C and D shown as attached are formed. The width of the conductive layer pattern 21 is W, the width of the finger 23 is g, and the distances from the centers of the ohmic electrodes A and B to one side of the nearer gate electrode are a and b, respectively, and the ohmic electrodes (hereinafter simply referred to as electrodes). ) A, B
Let L be the distance between the centers of the conductive layers and t be the thickness of the conductive layer 11 (first
(See FIG. 2 which is a cross-sectional view of the measuring element in the figure).

In the method of the present invention, (1) a current I is passed between the electrodes C and D, and the ohmic electrode A-
The voltage V _AB between B is measured to obtain V _L , r _L (see FIG. 2).

(2) + is applied to the electrode pattern 22 and-is applied to the electrode C, and a current I is passed. The voltage V _AB between the electrodes A and B is measured to obtain Va and ra.

(3) + is applied to the electrode pattern 22 and-is applied to the electrode D, and a current I is passed. The voltage V _AB between the electrodes A and B is measured to obtain Vb, rb.

If the conductivity and cross-sectional area between the electrodes A and B are constant, r _L is L, ra is a, and rb is proportional to b. Thus, the gate electrode dimension g is _{g = L (r L -ra-} rb) / r L = L (V L -Va-Vb) / V L electrodes A, the position d of the gate electrode between the B is d = L ( _{ra-rb) / 2r L =} L (Va-Vb) / 2V L is obtained.

Specifically, 175 KeV, 2 × 10 ¹³ cm ^{-2 on} a semi-insulating GaAs substrate.
Si ⁺ ions were implanted and cap annealing was performed at 810 ° C. The sheet resistance of the conductive layer was about 200 Ω / □. AuGe-Ni-Au is used for the ohmic electrode, and the Schottky electrode is
Au plating was performed on W Si.

The pattern size on the mask is W = 10 μm, L = 10
μm, a = b = 4 μm, g = 2 μm, measured current I was 1 mA, _VL was 210.0 mV, Va = 84.0 mV, Vb = 77.7 mV.

From this, g = 10 × (210.0-84.0-77.7) /210.0=2.30 (μm) was obtained, and it was found that the gate was 0.3 μm larger than the design length.

As a misalignment, d = 10 (84.0-77.7) /2×210=0.15 (μm) was obtained, and it was found that the deviation was 0.15 μm in the direction of the electrode B.

It was possible to electrically measure the distribution of shift amount and misalignment from the designed length of the gate length in the in-plane X and Y directions.

G at the time of SEM observation of the gate cross section and formation of the conductive layer pattern
As a result of etching and observing aAs, it was confirmed that the method of the present invention had an accuracy of ≦ ± 0.05 μm and was suitable for practical use.

〔The invention's effect〕

As described above, according to the present invention, the gate dimension that cannot be optically measured can be accurately estimated by electrical measurement, and the misalignment between the conductive layer pattern and the Schottky metal that cannot be optically measured is electrically high. The measurement can be performed with accuracy, and further, the electrical data can be input to the computer for statistical processing, and the X and Y direction components can be separated and measured.

[Brief description of drawings]

 FIG. 1 is a plan view of an embodiment of the present invention, FIG. 2 is a sectional view of the embodiment of FIG. 1, and FIG. 3 is a sectional view of an essential part of a GaAs MES FET. In the figure, 11 is a channel layer, 12 is a source / drain region, 13 is a source / drain electrode, 14 is a gate, 21 is a conductive layer pattern and 22 is an electrode pattern.

Claims (1)

(57) [Claims] 1. A step of forming an ion-implanted layer on a compound semiconductor substrate, wherein current electrodes (C, D) are provided at both ends of the ion-implanted layer, and two voltage electrodes (A) separated by an interval (L) therebetween. , B), a step of forming a finger (23) having a width (g) and an electrode (G) connected to the same in the same step as the Schottky gate metal formation in the center of the current electrode (C, D), When (I) is flown between the electrodes (C, D), the electrodes (G)
From one electrode (C) and the other electrode (D), the values of _VL , Va, and Vb are obtained, and the dimension g is given by g = L ( _VL- Va-Vb) / _VL. The gate length of the Schottky gate is characterized by obtaining the alignment error between the ion implantation layer and the Schottky metal pattern by the difference between the obtained actual size and the mask design length, and d = L (Va-Vb) / 2V _L. Or how to measure the alignment accuracy.