JP2514435B2 - Semiconductor memory device and manufacturing method thereof - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method for manufacturing the same, and more particularly to a charge storage section (stacked transistor) having a laminated structure.
The present invention relates to a dynamic random access memory (hereinafter referred to as DRAM) including a capacitor cell and a manufacturing method thereof.

[Prior Art] DRAM is already well known. FIG. 6 is a block diagram showing an example of the overall structure of such a conventional DRAM.

Referring to FIG. 6, the DRAM includes a memory cell array 1000 including a plurality of memory cells, which are storage portions, and a row decoder 20 connected to an address buffer for selecting the address thereof.
00, a column decoder 3000, and an input / output interface unit including a sense amplifier connected to the input / output circuit. The plurality of memory cells, which are storage portions, are provided in a matrix including a plurality of rows and a plurality of columns. Each memory cell is
The memory cell array 1000 is configured by being connected to the corresponding word line connected to the row decoder 2000 and the corresponding bit line connected to the column decoder 3000. Upon receiving a row address signal and a column address signal given from the outside, a memory cell is selected by each one word line and bit line selected by the row decoder 2000 and the column decoder 3000. Data is written to the selected memory cell, or data stored in the memory cell is read. The reading / writing of data is instructed by a reading / writing control signal applied to the control circuit.

Data is N (= n × m) bit memory cell array 10
Accumulated at 00. Address information regarding memory cells to be read / written is stored in the row and column address buffers, and a specific word line is selected by the row decoder 2000 (of one word line among n word lines). Choice)
Connects the m-bit memory cell to the sense amplifier via the bit line. Next, by selection of a specific bit line by the column decoder 3000 (selection of one bit line among m bit lines), one sense amplifier therein is coupled to the input / output circuit, and the control circuit Is read or written in accordance with the command.

FIG. 7 is an equivalent circuit diagram of one memory cell 100 of the DRAM shown for explaining the write / read operation of the memory cell. According to this figure, one memory cell 100 is composed of a pair of field effect transistor Q and capacitor Cs.
The gate electrode of the field effect transistor Q is connected to the word line 200, and one source / drain electrode is the capacitor Cs.
One of the electrodes is connected to one of the electrodes, and the other source / drain electrode is connected to the bit line 300. At the time of writing data, the field effect transistor Q becomes conductive by applying a predetermined voltage to the word line 200.
The electric charge applied to 0 is stored in the capacitor Cs. On the other hand, at the time of reading data, the field effect transistor Q is rendered conductive by applying a predetermined voltage to the word line 200, so that the charge accumulated in the capacitor Cs is stored in the bit line 30.
Retrieved through 0.

FIG. 8 shows, for example, IEDM (International electron
FIG. 8 is a partial cross-sectional view showing a memory cell of a DRAM having a conventional stacked capacitor cell of a bit line embedded type shown in devices meeting) 88-pp.596-599. here,
The bit line embedded type refers to a type in which a bit line is formed in the lower layer of the charge storage part. FIG. 9 is a plan view thereof. FIG. 8 shows a cross section taken along the line VIII-VIII in FIG. In the figure, a gate electrode 3 also serving as a word line is formed on a silicon substrate 1 with a gate oxide film 2 interposed therebetween at a distance. On the silicon substrate 1, one and the other impurity regions 52 separated by the gate electrode 3 are formed as source / drain regions.
Bit line 82 is formed so as to be connected to one impurity region 52. The bit line 82 is formed so as to be orthogonal to the word line 3. The insulating film 4 is formed between the word line 3 and the bit line 82. A storage node 112 is formed on the bit line 82 via the insulating film 14.
Storage node 112 is formed so as to make electrical contact with the other impurity region 52. Cell plate 132
Is the storage node 1 through the capacitor dielectric film 122.
It is formed to face twelve. In this way, the storage node 112 and the cell plate 132, which serve as charge storage units, are
Since the bit line 82 is formed under the
182 is arranged diagonally with respect to the bit line 82 and the word line 3.

On the other hand, the sectional structure of the memory cell in which the bit line is located above the charge storage portion is shown in FIG. Referring to FIG. 10, bit line 83 is connected to one impurity region 53 through underlying pad 93. A storage node 113 is connected to the other impurity region 53 via an underlay pad 93. A cell plate 133 is formed on the storage node 113 via a capacitor dielectric film 123. In order to form the bit line 83 in the upper layer of the charge storage portion including the storage node 113 and the cell plate 133 as described above, it is necessary to form the thick interlayer insulating film 103 therebetween. Therefore, a margin M is required between the end of the cell plate 133 and the side wall of the contact hole.

However, in the structure shown in FIG. 8, the storage node 112 and the cell plate 132 are connected to the bit line 82.
Can be formed so as to extend over the contact portion connected to the impurity region 52. Therefore, the plane area of the charge storage portion can be increased. Therefore, it is possible to increase the capacitance of the capacitor.

Further, FIG. 11 shows, for example, IEDM88-pp.246-249.
With the conventional stacked capacitor cell shown in
FIG. 3 is a partial cross-sectional view showing a DRAM memory cell. FIG. 12 is a plan view thereof. FIG. 11 shows a cross section taken along the line XI-XI in FIG. In the figure, a tungsten plug 84a is formed via an underlay pad 94b so as to be electrically connected to one impurity region 54. Tungsten bit line 84 so that it touches this tungsten plug 84a
Are formed. The storage node 1 is provided via the underlay pad 94a so as to make electrical contact with the other impurity region 54.
14 are formed. The storage node 114 is formed along the inner surface of the recess selectively formed in the thick flat interlayer insulating film 104 and the flat upper surface of the interlayer insulating film 104. The cell plate 134 is the storage node 114.
Is formed on the above with a capacitor dielectric film 144 interposed therebetween. Although not shown in FIG. 12, the bit line 84 is formed along the line XI-XI so as to be orthogonal to the word line 3 and electrically connected to the impurity region 54 via the contact 164. It Storage node 114 is connected to impurity region 54 via contact 154. In this way, the contact 1 of the storage node 114 extends in the direction in which the bit line
Since 54 exists, the active region 184 is arranged so as to be orthogonal to the word line 3. Further, in this structure, the field shield 74 is adopted as the isolation region.

According to the structure of the memory cell shown in FIG. 11, the storage node 114 forming the charge storage portion is formed along the inner surface of the recess formed in the thick, flat interlayer insulating film and the upper surface of the interlayer insulating film. Being formed, the surface area of the charge storage portion can be expanded in the vertical direction. Therefore, it is possible to increase the capacitance of the capacitor within the limited area occupied. Moreover, since the storage node forming the charge storage portion is formed by patterning on the flat interlayer insulating film, the processing can be easily performed.

[Problems to be Solved by the Invention] However, according to the conventional bit line buried type stacked capacitor cell shown in FIG. 8, the surface area of the storage node forming the charge storage portion is laterally enlarged. This is the limit to the expansion of the surface area in the lateral direction. Therefore, it is difficult to cope with a remarkable reduction in the plane area occupied by the charge storage portion as the semiconductor element is further miniaturized and highly integrated.

On the other hand, according to the conventional stacked capacitor cell shown in FIG. 11, a margin M is required between the edge of the cell plate and the edge of the contact portion of the bit line. Further, when the storage node, which is a charge storage portion, is formed by extending in the vertical direction with the miniaturization of the semiconductor element,
The depth of the contact hole for connecting the bit line to the impurity region becomes deep. Therefore, it is difficult to accurately open the contact hole. Further, it is difficult to selectively form a tungsten film in the contact hole.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to solve the above problems, and to provide a semiconductor memory device having a stacked capacitor cell capable of obtaining a large capacitance with a smaller occupied plane area, and a manufacturing method thereof. It is to be.

[Means for Solving the Problems] A semiconductor memory device according to the present invention is a semiconductor substrate of the first conductivity type having a main surface, one and the other impurity regions, a gate electrode, a wiring layer, and a storage node. And a cell plate. The one and the other impurity regions are formed in the semiconductor substrate and are spaced from each other so as to define the channel region. The gate electrode is formed on the channel region with an insulating film interposed. The wiring layer is formed so as to be in electrical contact with one of the impurity regions and extend above the gate electrode. The storage node includes a bottom wall layer portion and a standing wall layer portion. The bottom wall layer portion is formed so as to be in electrical contact with the other impurity region and extend above the gate electrode and the wiring layer along the respective surface shapes of the gate electrode and the wiring layer. The standing wall layer portion electrically contacts the portion inside the edge of the bottom wall layer portion, and extends from the portion inside the edge of the bottom wall layer portion in a direction substantially perpendicular to the main surface of the semiconductor substrate to the bottom wall. It is formed so as to extend above the layer portion. The cell plate is formed on the storage node so as to extend along the surface shape of the storage node with a dielectric film interposed.

A method of manufacturing a semiconductor memory device according to the present invention includes the following steps.

(A) A step of forming gate electrodes on a main surface of a first conductivity type semiconductor substrate with an insulating film interposed therebetween with a space therebetween.

(B) A step of forming one impurity region and the other impurity region separated by the gate electrode.

(C) A step of electrically connecting to one impurity region and forming a wiring layer extending above the gate electrode.

(D) A step of forming an insulating layer that covers the wiring layer and exposes the surface of the other impurity region.

(E) A bottom wall layer forming a storage node so as to be in electrical contact with the other impurity region and extend along the respective surface shapes of the gate electrode and the wiring layer above the gate electrode and the wiring layer. Forming a part.

(F) From the portion inside the edge of the bottom wall layer portion to the bottom wall layer portion that is in electrical contact with the portion inside the edge of the bottom wall layer portion and is substantially perpendicular to the main surface of the semiconductor substrate. Forming a standing wall layer portion that constitutes the storage node so as to extend above.

(G) A step of forming a cell plate on the storage node so as to extend along the surface shape of the storage node with a dielectric film interposed.

[Operation] In the present invention, the storage node that is the charge storage portion includes the bottom wall layer portion and the standing wall layer portion. The bottom wall layer portion extends along the respective surface shapes of the gate electrode and the wiring layer above the gate electrode and the wiring layer. The standing wall layer portion extends above the bottom wall layer portion from a portion inside the edge of the bottom wall layer portion. Therefore, the surface area of the storage node is further expanded not only by the surface area of the bottom wall layer portion but also by the surface area including both side surfaces of the standing wall layer portion, so that the capacitance of the capacitor can be increased.

Further, since the wiring layer electrically contacting one of the impurity regions is formed below the storage node, it is not necessary to form a deep contact hole for contacting the bit line and the substrate. Further, since the storage node extends sufficiently in the lateral direction without being affected by the contact region of the bit line, it is possible to increase the capacitance of the capacitor in plan view.

Therefore, it is possible to form the charge storage portion capable of obtaining a large capacitor capacitance with a smaller occupied plane area.

[Embodiment of the Invention] First, an example of a memory cell related to the present invention will be described with reference to the drawings.

1A is a partial sectional view conceptually showing the structure of a DRAM memory cell having stacked capacitor cells according to the present invention, and FIG. 1B is a partial plan view corresponding to the sectional view. It is a figure. It should be noted that FIG. 1A shows a cross section taken along the line I-I of FIG. Further, FIG. 2 shows the first
It is a top view which changes the direction of the partial top view shown in FIG. An example of the structure of the memory cell related to the present invention will be described with reference to these drawings.

A gate electrode 3 also serving as a word line is formed of polycrystalline silicon on a p-type silicon substrate 1 with a gate oxide film 2 interposed therebetween. The word lines 3 are formed so as to extend in a certain direction with a predetermined space therebetween. The n-type impurity region to be the source or drain region has an LDD structure including a low concentration impurity region 5 and a high concentration impurity region 6. Bit line 8 made of polycrystalline silicon is formed so as to be electrically connected to one of the impurity regions. The bit line 8 is formed so as to be orthogonal to the word line 3. A storage node 11 is formed in the other impurity region so as to be electrically connected via an underlay pad 9 made of polycrystalline silicon. The storage node 11 is formed along the inner surface of the storage node opening 11a formed in the interlayer insulating film 10 formed above the bit line 8. A cell plate 13 is formed on the storage node 11 via a capacitor dielectric film 12.

Bit line 8 is formed in bit line contact 16 so as to electrically contact the impurity region. Storage node 11 is formed so as to be in electrical contact with the impurity region through storage pad 9 at the storage node contact 15. Since the electrical contact with the silicon substrate 1 is formed in this manner, the active region 18 is connected to the bit line 8 and the word line 3 as shown in FIGS. 1 (b) and 2. Are provided so as to diagonally intersect with each other.

Next, a method for forming a specific structure of the above memory cell will be described. 3A to 3M are partial cross-sectional views showing a method of manufacturing a memory cell having a stacked capacitor cell according to the present invention in the order of steps.

First, referring to FIG. 3A, isolation regions 7 made of a silicon oxide film are formed at intervals so as to surround the element formation region on the p-type silicon substrate 1. After that, a thermal oxidation process is performed on the entire surface to form a thermal oxide film having a film thickness of about several hundred liters. A polycrystalline silicon film 31 and a silicon oxide film 41 are formed on the thermal oxide film 21 by a chemical vapor phase thin film growth method (CVD method). A resist film 17a having a predetermined pattern is formed on the silicon oxide film 41.

As shown in FIG. 3B, using the resist film 17a as a mask, the silicon oxide film 41 and the polycrystalline silicon film 31 are formed.
Are selectively removed using anisotropic etching such as reactive ion etching. In this way, the gate electrode 3 and the silicon oxide film 41a are formed in a desired portion in the active region. Using the gate electrode 3 and the isolation region 7 as a mask, low concentration arsenic or phosphorus of about 10 ¹² to 10 ¹³ cm ⁻² is implanted into the silicon substrate 1.

Referring to FIG. 3C, a silicon oxide film 42 is formed on the entire surface of silicon substrate 1.

Further, as shown in FIG. 3D, anisotropic etching is used to selectively perform etching,
The sidewall 4 made of a silicon oxide film is formed only on the sidewall of the gate electrode 3. This sidewall 4
Using the isolation region 7 as a mask and a high concentration of phosphorus or arsenic is implanted into the silicon substrate 1.

Referring to FIG. 3E, by performing in-furnace annealing treatment at a temperature of 850 to 900 ° C. or rapid annealing treatment by lamp annealing at a temperature of 1000 ° C. or more,
The phosphorus or arsenic implanted in the silicon substrate 1 is thermally diffused to form a source or drain region 10 ¹⁶ to 10 ¹⁸
n − type impurity region 5 with a low concentration of about cm ⁻³ and 10 ¹⁹ to 10 ²¹ cm ⁻¹
An LDD structure composed of the impurity regions 6 of high concentration is formed.

As shown in FIG. 3F, the insulating film 1 made of a silicon oxide film is first formed on the impurity regions 5 and 6 to which the bit lines are not connected.
40 are formed. After that, a polycrystalline silicon film 81 and a silicon oxide film 141 whose resistance is lowered by implanting arsenic or phosphorus are formed on the entire surface of the silicon substrate 1 by the CVD method. A resist film 17b is formed on the silicon oxide film 141 according to a predetermined pattern.

Referring to FIG. 3G, by performing anisotropic etching treatment using this resist film 17b as a mask,
The silicon oxide film 141 and the polycrystalline silicon film 81 are selectively removed. In this way, the bit line 8 is formed so as to be connected to only one of the impurity regions 5 and 6.

Then, again as shown in FIG.
142 is formed on the entire surface of the silicon substrate 1 by using the CVD method.

As shown in FIG. 3I, the anisotropic etching process is performed to selectively leave the silicon oxide film only on the sidewalls of the bit lines 8 to form the sidewalls 14. At the same time, the impurity regions 5 and 6 connected to the capacitor section are
Is exposed.

As shown in FIG. 3J, a polycrystalline silicon film 91 is formed on the entire surface of the silicon substrate 1 by using the CVD method. A resist film 17c is formed on the polycrystalline silicon film 91 according to a predetermined pattern. Anisotropic etching is performed using the resist film 17c as a mask to form the underlying pad 9 made of polycrystalline silicon.

As shown in FIG. 3K, a silicon oxide film 101 having a thick and flat surface is formed on the entire surface of the silicon substrate 1 by the CVD method. Then, this silicon oxide film 101
A resist film 17d is formed thereon according to a predetermined pattern. Anisotropic etching is performed using the resist film 17d as a mask, so that the underlying pad 9
A contact hole is opened to expose the surface of the.

As shown in FIG. 3L, the polycrystalline silicon film is formed on the entire surface along the inner surface of the contact hole and the upper surface of the interlayer insulating film 10.
111 is formed. On this polycrystalline silicon film 111,
A resist film 17e is formed according to a predetermined pattern.
By using this resist film 17e as a mask, anisotropic storage is applied to form storage node 11.

Finally, as shown in FIG. 3M, the capacitor dielectric film 12
Are formed on the surface of the storage node 11. A cell plate 13 made of polycrystalline silicon is formed on the entire surface of the silicon substrate 1 on the capacitor dielectric film 12.
Thus, the memory cell having the stacked capacitor cell related to the present invention is completed.

Next, an embodiment of a memory cell having a stacked capacitor cell structure related to the present invention will be described. FIG. 4 is a partial sectional view showing the structure of a memory cell as an embodiment of the present invention. The difference from the structure shown in FIG. 1 is that the storage node 11 has a side wall portion formed so as to extend substantially perpendicularly to the main surface of the silicon substrate 1, and both side surfaces of the side wall portion are cell-shaped. That is, it is formed so as to face the surface of the plate 13. As a result, the capacitance of the capacitor is further expanded. That is, according to the structure shown in FIG.
In the storage node 11 formed along the side wall of the interlayer insulating film 10, only one side wall surface thereof is used as a capacitor, whereas according to the structure shown in FIG. Both sides of are used as capacitors. Therefore, the capacitance of the capacitor having the structure of FIG. 4 is further increased as compared with the capacitor having the structure of FIG. Further, the structure shown in FIG. 4 differs from the structure shown in FIG. 1 in that a silicon nitride film 19 is formed, as will be described in detail in the following manufacturing method.

Next, a method of manufacturing the memory cell structure shown in FIG. 4 will be described. 5A to 5P are partial cross-sectional views showing a method of manufacturing a memory cell according to an embodiment of the present invention in the order of steps. The manufacturing process shown in FIGS.
Since the manufacturing process is the same as that shown in FIGS. 3A to 3J, description thereof will be omitted.

Referring to FIG. 5J, an underlying pad 9 made of polycrystalline silicon is formed so as to come into contact with impurity regions 5 and 6 connected to the capacitor portion.

Referring to FIG. 5K, silicon nitride film 19 is formed so as to cover at least the region where bit line 8 is formed.

Referring to FIG. 5L, a thick silicon oxide film 101 is formed on the entire surface of silicon substrate 1.

As shown in FIG. 5M, a deep contact hole is formed in the interlayer insulating film 101a so as to expose the surface of the underlying pad 9 by using the resist film 17d formed on the silicon oxide film 101 according to a predetermined pattern as a mask. It is opened.

As shown in FIG. 5N, a polycrystalline silicon film 111 is formed on the entire surface along the inner surface of the contact hole and the upper surface of the interlayer insulating film 101a.

As shown in FIG. 5O, anisotropic etching such as reactive ion etching is performed without using a mask, so that the polycrystalline silicon film 111 is entirely etched off. In this way, the interlayer insulating film 101a
The polycrystalline silicon film 111 is left only on the side wall of the deep contact hole portion of. As a result, storage node 11 is formed so as to be bonded to underlying pad 9 made of polycrystalline silicon. After that, the interlayer insulating film 101a is entirely removed by wet etching. At this time, the bit line 8
The silicon oxide film formed on the bit line 8 is not removed by using the silicon nitride film 19 formed above the formation region of (3) as a mask.

Finally, as shown in FIG. 5P, a capacitor dielectric film 12 is formed so as to cover the surfaces of the underlying pad 9 and the storage node 11. A cell plate 13 made of polycrystalline silicon is formed on the capacitor dielectric film 12.
As described above, the memory cell as one embodiment of the present invention is completed.

In the above embodiment, the memory cell is constructed.
Although the LDD structure is used for the MOS transistor, any structure may be adopted as long as it operates as a switching element such as a single structure, a DDD structure, and a gate overlap structure.

Further, in the above embodiments, polycrystalline silicon is used as the material for the gate electrode, the bit line, the underlying pad, the storage node, and the cell plate, but it may be a metallized film of silicon or a laminated film in which these are laminated. May be adopted.

As described above, according to the present invention, the storage node can be formed so as to extend substantially vertically and horizontally with respect to the main surface of the semiconductor substrate. Can be further expanded. Therefore, the capacitance of the capacitor can be further increased. Further, since the bit line is located in the lower layer of the storage node, a deep contact between the bit line and the substrate is not necessary, so that the disadvantage in the manufacturing process can be eliminated.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a partial cross-sectional view showing a structure of a memory cell of a semiconductor memory device according to the present invention and a partial plan view corresponding thereto. FIG. 2 is a partial plan view showing a planar arrangement of memory cells of the semiconductor memory device according to the present invention. 3A, 3B, 3C, 3D, 3E, 3F,
3G, 3H, 3I, 3J, 3K, 3L, 3M
The drawings are partial cross-sectional views showing, in the order of steps, a method of manufacturing a memory cell of a semiconductor memory device according to the present invention. FIG. 4 is a partial cross-sectional view showing the structure of the memory cell of the semiconductor memory device according to the embodiment of the present invention. 5A, 5B, 5C, 5D, 5E, 5F,
5G, 5H, 5I, 5J, 5K, 5L, 5M
FIG. 5, FIG. 5N, FIG. 5O, and FIG. 5P are partial cross-sectional views showing a method of manufacturing a memory cell in a semiconductor memory device according to an embodiment of the present invention in the order of steps. FIG. 6 is a block diagram showing the overall structure of a conventional DRAM. FIG. 7 is an equivalent circuit diagram corresponding to one memory cell of the DRAM shown in FIG. FIG. 8 is a partial cross-sectional view showing the prior art of the structure of a memory cell having a stacked capacitor cell. FIG. 9 is a partial plan view showing a planar arrangement of memory cells corresponding to the structure shown in FIG. FIG. 10 is a partial cross-sectional view showing the structure of a memory cell having a conventional stacked capacitor cell. FIG. 11 is a partial cross-sectional view showing another prior art structure of a memory cell having stacked capacitor cells. FIG. 12 is a partial cross-sectional view showing a planar arrangement of memory cells corresponding to the structure shown in FIG. In the figure, 1 is a silicon substrate, 2 is a gate oxide film, 3
Is a gate electrode, 5 is a high concentration impurity region, 6 is a low concentration impurity region, 8 is a bit line, 11 is a storage node, 12 is a capacitor dielectric film, and 13 is a cell plate. In each drawing, the same reference numerals indicate the same or corresponding parts.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Hirotsugu Kimura, 4-chome, Mizuhara, Itami City, Hyogo Prefecture Mitsubishi Electric Corporation LSI Research Laboratory (72) Shinichi Sato, 4-chome, Mizuhara, Itami City, Hyogo Prefecture Address Mitsubishi Electric Corporation LSI Laboratory (56) Reference JP-A-63-278363 (JP, A) JP-A-2-257671 (JP, A) JP-A-3-46363 (JP, A) ) JP-A-2-94558 (JP, A)

Claims (2)

(57) [Claims] 1. A field effect transistor having one and the other impurity regions formed on a semiconductor substrate, a wiring layer connected to one impurity region of the field effect transistor, and connected to the other impurity region. A semiconductor memory device having a charge storage portion, wherein a first conductivity type semiconductor substrate having a main surface and one of the semiconductor substrates formed on the semiconductor substrate and spaced apart from each other to define a channel region. And the other impurity region, a gate electrode formed on the channel region with an insulating film interposed, and formed to make electrical contact with the one impurity region and extend above the gate electrode. Electrically connected to the other impurity region and extending along the surface shape of each of the gate electrode and the wiring layer above the gate electrode and the wiring layer. The bottom wall layer portion formed so as to electrically contact the portion inside the edge of the bottom wall layer portion, and the bottom wall layer portion in a direction substantially perpendicular to the main surface of the semiconductor substrate. A storage node including a standing wall layer portion formed to extend above the bottom wall layer portion from a portion inside an edge of the storage node, and a surface of the storage node with a dielectric film interposed on the storage node. And a cell plate formed so as to extend along the shape. 2. A field effect transistor having one and the other impurity regions formed on a semiconductor substrate, a wiring layer connected to one impurity region of the field effect transistor, and connected to the other impurity region. A method of manufacturing a semiconductor memory device comprising a charge storage part, the method comprising: forming gate electrodes on a main surface of a first-conductivity-type semiconductor substrate with an insulating film interposed between them; Forming one and the other impurity regions separated by electrodes; forming a wiring layer electrically contacting the one impurity region and extending above the gate electrode; Forming an insulating layer that covers and exposes the surface of the other impurity region; electrically contacting the other impurity region and above the gate electrode and the wiring layer; Forming a bottom wall layer portion forming a storage node so as to extend along the respective surface shapes of the electrodes and the wiring layer; and electrically forming a portion inside the edge of the bottom wall layer portion. A standing wall layer portion that constitutes a storage node so as to extend in contact with and extend above the bottom wall layer portion from a portion inside the edge of the bottom wall layer portion in a direction substantially perpendicular to the main surface of the semiconductor substrate. And a step of forming a cell plate on the storage node so as to extend along the surface shape of the storage node with a dielectric film interposed therebetween, and a method of manufacturing a semiconductor memory device. .