JP2517064B2 - Denormalized number processing method - Google Patents

Description

DETAILED DESCRIPTION [Table of Contents] Outline Industrial field of application Conventional techniques and problems to be solved by the invention Means for solving the problem Action Example Effect of the invention [Outline] American Institute of Electrical and Electronics Engineers (IEEE) ) Regarding the processing method of denormalized numbers in the floating point processing device using the standard or the binary floating point representation format conforming to this standard, deletion of the pre-operation normalization circuit and the processing speed of floating point arithmetic including denormalized numbers In order to improve the performance of the two input operand data in a binary floating point processor equipped with a mechanism for operating the operand data as having an infinite exponent range even in the case of the above denormalized number. For each of them, means for detecting whether or not all the bits constituting the exponent part E are “0” is provided, and when the exponent part E is detected as “0”, For operand data side to respond to the forced '1' value of exponent supplied to the exponent operation portion,
Further, when the 1-bit integer part supplied to the mantissa operation unit is set to '0' and at least 1 bit of the exponent part E is '1', the exponent part of the operand data is set to the corresponding operand data side. Supply it to the above-mentioned exponent part operation part,
In addition, the 1-bit integer part supplied to the mantissa arithmetic unit is set to '1' to perform floating point arithmetic.

[Industrial applications]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a denormalized number processing method in a floating point processing device using a binary floating point representation format conforming to the American Institute of Electrical and Electronics Engineers (IEEE) standard or the standard.

2. Description of the Related Art Conventionally, in a large-scale computer that performs chemical engineering calculation, there is a strong demand for high-speed processing of the scientific and technological calculation, and the ability to execute floating point arithmetic instructions at high speed has become an important issue.

Therefore, in the large-scale computer, the floating-point arithmetic is executed at high speed by providing the arithmetic unit dedicated to the floating-point.

In addition, since the operand data of the floating point arithmetic instruction is usually the normalized floating point data which has been normalized in advance, the dedicated arithmetic unit as described above operates at the highest speed with respect to the normalized number. In general, the optimum design is made so that it can be done.

However, even when the operand data is not normalized data, it is originally desired to be processed at high speed.

Usually, the floating-point data processed by a computer can express only a limited number of significant digits, so that an error occurs in the result of the floating-point operation in many cases.

Conventionally, how much error occurs depends largely on the hardware configuration. Even if the programs are the same, the degree of error differs depending on the computer. For example, if the operation result is near zero, In some cases, the calculation result becomes zero, and a program exception occurs, which may result in a result that the user does not expect.

Until now, standardization of unified processing for the calculation results such as exceptional processing and processing for errors in such numerical calculation has been delayed, so as application software for numerical calculation has recently been packaged, , Spread of the packaged application software,
And hindered the promotion of development.

In recent years, mainly for the purpose of improving such a situation, there is a standard having a rounding mode that can be specified by a user and a floating point representation format that can express a special operand such as infinity and not a number (data that is not a number). Advocated by the Institute of Electrical and Electronics Engineers (IEEE) Committee, it is becoming widespread in the world, and it is expected that the demand for the IEEE standard or standards conforming to it will increase in the future. A floating-point arithmetic processing method capable of coping with various standards is required.

[Problems to be Solved by Conventional Techniques and Inventions]

FIG. 2 is a diagram for explaining a conventional denormalized number processing method.

As described above, in the processor using the American Institute of Electrical and Electronics Engineers (hereinafter referred to as IEEE) standard or the binary floating point representation format based on this standard, the maximum value of the exponent part (each bit constituting the exponent part is All are "1"), and the minimum value (all bits that make up the exponent part are all "0") is an infinite number, NAN
Reserved for representing special numbers such as (not a number), zero, and denormalized numbers.

An example of such a floating point representation format is shown in FIG. In the figure, S is a sign bit, which represents'positive 'when S = 0 and'negative' when S = 1, and E is the exponent part with an appropriate bias value added to the actual exponent e. . Also, F
Is a mantissa part and is composed of a bit string representing the fraction part of the second trial floating point. In the case of a normalized number, the integer part of the mantissa part is implicitly assumed to be '1'.

The floating point representation format of FIG. 2 (a) represents the following numerical values.

When E = 2 ^m −1 and F ≠ 0, it is not a number (NAN), when E = 2 ^m −1 and F = 0, (−1) ^S × ∞ ... (± infinity) 0 <E < When 2 ^m -1 (-1) ^S x (1.F) x 2 ^E-bias ... (normalized number) When E = 0 and F ≠ 0 (-1) ^s x (0.F) × 2 ^1-bias (unnormalized number) When E = 0 and F = 0 (−1) ^s × 0 (± 0) where 0 ≦ E ≦ 2 ^m −1 (m is a bit of the exponent part) Number), and when 0 <E <2 ^m −1, it represents a normalized number, and bias is a bias value.

In this IEEE standard, as described above, E = 0 (minimum exponent part) and E = 2 ^m −1 (maximum exponent part) are infinite,
Reserved to represent special numbers such as not-a-number, zero, and denormalized numbers.

Then, the denormalized number is recognized by E = 0 and F ≠ 0. However, the actual exponent value of the normalized number is defined to be equal to the minimum number of exponents of the normalized number (ie, E = 1-bias).

When the operand data of the floating point arithmetic according to the IEEE standard is a denormalized number, the processing differs depending on the arithmetic mode.

That is, there are a warning operation mode in which an exception is detected as an invalid operation, and a normalization operation mode in which an operation is performed using an intermediate result obtained by performing pre-operation normalization processing of operand data as having an infinite exponent range.

Generally, a data processing device that processes floating-point arithmetic at high speed is provided with a dedicated arithmetic unit especially for multiplication and addition / subtraction that require high processing speed.

However, since the operand data is expected to be a normalized number in most cases, these dedicated arithmetic units are designed to be optimal for the operation of the normalized number, and processing for a special operand is performed. Suffices to detect that it is not the processing target of the dedicated arithmetic unit and perform the processing separately. This is because the special operand is rarely processed, and in general, the processing result of the special operand produces a special result.

However, in the above normalization operation mode, when performing operations such as operations on normalized numbers and denormalized numbers, or operations on denormalized numbers and denormalized numbers, numerical values should be obtained as a result. Therefore, it is preferable that the processing is performed as fast as possible.

However, as shown in FIG. 2B, the conventional floating point arithmetic unit has a configuration for a normalized number.
The arithmetic unit shown in the figure is an example of a general multiplier configuration.

First, when a normalized number is supplied as an input operand, the sign arithmetic circuit 1 causes the sign bits (S ₁ , S
₂ ) The exclusive OR (∀) of
and outputs it as r, and the mantissa arithmetic circuit 3 is supplied with L ₁ as the integer part of operand 1 and F ₁ as the decimal part, and with L ₂ as the integer part of operand 2 and F ₂ as the decimal part,
The product of the two is supplied to the normalization circuit 5 after the provisional part calculation.

The mantissa post-normalization circuit 5 shifts the product to the right or left so that the bit with the highest weight among the bits that are not "0" of the product comes to the position 1 bit higher than the decimal point. After calculation, normalization is performed, and the result is output as Fr, and the shift amount is calculated as the exponent part correction circuit 4
To send to.

Further, the exponent arithmetic circuit 2 uses the exponent part (E ₁ ,
E ₂ ) is added, and the exponential bias added at that time {usually, a predetermined bias value (bias) is added to the actual exponent value so that the exponent part of the floating point data is a positive number} The result obtained by subtracting the
To send to.

The exponent part post-compensation correction circuit 4 performs the normalization correction of the exponent calculation result based on the shift amount supplied from the mantissa part post-normalization circuit 5, and outputs the exponent part Er of the multiplication result.

The post-computation correction of the exponent is performed by adding "+1" per 1-bit shift when the mantissa calculation result is right-shifted by the post-addition-part normalization circuit 5, and 1 when left-shifted.
This is done by correcting the exponent value by '−1' per bit shift.

Incidentally, in the actual multiplication circuit, a rounding processing circuit (not shown) for the operation result and various exception detection circuits (not shown) are further added, but they are omitted for simplification of description. .

In the conventional multiplier as described above, when the input operand is a non-normalized number, it cannot be processed by the scholar, so it is necessary to add a pre-operation normalization circuit for the input operand. Therefore, the normalized data after performing the pre-computation normalization processing by the above-mentioned method must be supplied to the present arithmetic unit.

Therefore, if a floating point operation is executed after performing pre-operation normalization processing of a denormalized number, an extra processing time is required for the pre-operation normalization processing, and pre-operation normalization for one operand at a time is performed. In the case of a configuration capable of performing only processing, there is a problem that the processing time is increased by an amount corresponding to the pre-operation normalization processing of two operands in the worst case.

Also, the exponent part E of the above denormalized number is '0', but since the actual exponent value has the same size as the minimum exponent value of the normalized number as described above, When converting to a normalized number by the normalization process, for example, “+1” must be added to subtract the normalized shift amount from the exponent part.

Further, when the pre-computation normalization processing circuit is added to the dedicated arithmetic unit, there is a problem that the amount of hardware of the dedicated arithmetic unit increases and the control becomes complicated, and the pre-computation normalization processing is performed by the above-mentioned separate means. When the result of the operation is supplied to the dedicated arithmetic unit, the exponent part E of the operand data obtained by normalizing the denormalized number supplied to the arithmetic unit becomes a negative number. Usually, the exponent part E cannot be expressed by a positive integer), and therefore, there is a problem that a new processing mode must be added, and there is a problem in realizing the normalization operation mode of the floating point expression format such as the IEEE standard. It was an overflow road.

In view of the above conventional drawbacks, the present invention provides a pre-operation normalization circuit for processing a denormalized number in a normalization operation mode in a processing device using a binary floating point format conforming to the IEEE standard or the IEEE standard. It is an object of the present invention to provide a denormalized number processing method that improves the processing speed of operations including the deletion of and denormalized numbers.

[Means for solving the problem]

The above problems can be solved by the denormalized number processing method configured as follows.

1-bit sign part S, m-bit exponent part E, and n
According to the mantissa part F of a bit, when E = 2 ^m −1 and F ≠ 0, it is not a number (NAN), when E = 2 ^m −1 and F = 0, (−1) ^S × ∞ ... … (± Infinity) 0 <E <2 ^m −1, (−1) ^S × (1.F) × 2 ^E-bias …… (Normalized number) E = 0 and F ≠ 0 (-1) ^s x (0.F) x 2 ^1-bias (unnormalized number) When E = 0 and F = 0, (-1) ^s x 0 (± 0) where bias is the bias It is a value.

In a binary floating-point processor having a floating-point format that represents each of the two, and the operand data has a mechanism to operate as having an infinite exponent range even in the case of the above denormalized number, two input operand data For each of the above, a means for detecting whether or not all the bits constituting the exponent part E are '0' is provided, and when the exponent part E is detected as '0' in the means, For the corresponding operand data side, the value of the exponent part supplied to the exponent calculation unit is forcibly set to "1", and the 1-bit integer part supplied to the mantissa calculation unit is set to "0". If at least 1 bit of the operand is '1', the exponent part of the operand data is supplied to the exponent operation part of the corresponding operand data side, and the 1-bit integer part supplied to the mantissa operation part To Configure as '1' to perform floating point arithmetic.

[Action]

That is, according to the present invention, even if the operand data is a denormalized number, the precision of the intermediate result can be reduced in the arithmetic processing unit of the floating point data in the processing device of the floating point representation format conforming to the IEEE standard. Is sufficiently secured, the correct result can be obtained by performing the post-operation normalization processing on the result calculated without performing the pre-operation normalization processing. Although the exponent value of the denormalized number is the same as the minimum exponent value of the normalized number, the denormalized exponent part is '0' and the exponent part of the normalized number is '1'. ', Further, the integer part of the mantissa of the denormalized number is'0', the integer part of the mantissa of the normalized number is' 1 ', in the present invention, the exponent of the operand data It is detected whether or not the part E is the minimum value (= 0), and when E ≠ 0, the exponent part E of the operand data is supplied to the sagittal exponent operation part and the upper part of the mantissa part. 1-bit implicit integer part in
Is supplied to the exponent arithmetic circuit, and when E = 0, the least significant bit of the exponent E of the operand data is forcibly supplied as '1' to the exponentiation arithmetic unit, and at the same time, it is 1 above the mantissa. By providing a means to supply the mantissa arithmetic circuit with the implicit integer part of the bit set to '0', even if the operand data is a denormalized number, floating point arithmetic is executed without performing pre-operation normalization processing. It is possible to process denormalized operands without major modification of the arithmetic unit designed optimally for normalized number processing, and it is necessary for pre-normalization processing. Since the amount of hardware and processing time can be saved, the arithmetic processing for denormalized numbers in the normalized arithmetic mode according to the IEEE standard, etc. can be significantly improved both in terms of hardware and time. But You.

〔Example〕

 Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of the present invention, which is a circuit for detecting whether or not the exponent part E of the operand data is the minimum value (E = 0) (E ₁ = 0 detection circuit, E 1 ₂ = 0 detection circuit) 6
0, 61 and means 7, 8 for supplying the detection output thereof to the exponential arithmetic circuit 2 and the mantissa arithmetic circuit 3 are means necessary for carrying out the present invention. The same reference numerals denote the same objects throughout the drawings.

Hereinafter, the denormalized number processing method of the present invention will be described with reference to FIG. 1 with reference to the example of the floating point representation format shown in FIG.

Also in the present embodiment, for convenience of explanation, a multiplication circuit will be described as an example.

Even if the present invention is implemented, the basic operation of the multiplication processing of floating-point data does not change in particular, so it is omitted. Here, the input method of the operand data to the exponent arithmetic circuit 2 and the mantissa arithmetic circuit 3 is described. I will explain mainly.

The floating-point multiplication circuit of the present invention is the same as the conventional floating-point multiplication circuit of FIG. 2 except that E ₁ = 0 detection circuit 60 and E ₂ =
It is the same as the conventional one except that the 0 detection circuit 61 is added and the operand data supplied to the exponent calculation circuit 2 and the mantissa calculation circuit 3 are controlled by the outputs of the detection circuits 60, 61.

First, with respect to operand 1, when E ₁ = 0, the output result of the E ₁ = 0 detection circuit 60 of the present invention becomes '1', so that E ₁ supplied to the exponential calculation circuit 2 is E ₁ L _{1 which} is forced to = 1 and is supplied to the mantissa arithmetic circuit 3 becomes L ₁ = 0 by the negating circuit 7.

When E ₁ ≠ 0 of the operand 1, the output result of the E ₁ = 0 detection circuit 60 becomes '0', and thus the exponent calculation circuit 2 selects the value of E ₁ as select 8. L ₁ supplied to the mantissa calculation circuit 3 through the shadow circuit is L ₁ = 1 by the negation circuit 7.

Similarly for operand 2, if E ₂ = 0,
When the output result of the E ₂ = 0 detection circuit 61 of the present invention becomes '1', E ₂ supplied to the exponential calculation circuit ₂ is forced to E ₂ = 1 and supplied to the mantissa calculation circuit 3. ₂ becomes L ₂ = 0 by the negation circuit 7.

If E ₂ ≠ 0 of the operand 2, the above E ₂ = 0
When the output result of the detection circuit 61 becomes “0”, the value of E ₂ is supplied to the exponential calculation circuit 2 via the select 8 and L ₂ supplied to the mantissa calculation circuit 3 is Negation circuit 7
Therefore, L ₂ = 1.

As a result, the above-described normalized numbers and denormalized numbers defined by the IEEE standard are generated without performing pre-processing, and are input to a conventional floating-point multiplication circuit and operated. It

In the above multiplication, when only the normalized number is targeted, the mantissa operation result Z is 4> Z ≧ 1 from the above definition.
Since (for example, 4> 1.XXXX ... × 1.XXXX> 1), the post-computation normalization process is sufficient if at most Z is shifted by 1 bit to the right, but not. If the normalized number is also a calculation target, 4>Z> 0, and therefore the left shift mechanism in the case of 1>Z> 0 (that is, 1> 0.1XXXX ... × 0.1XXXX ...> 0) Will be needed. That is, in this case, if the multiplication result Z is, for example, 0.0001XXX,
A 3-bit left shift is required.

As the left shift mechanism, if the mantissa post-operation normalization circuit 5 of the multiplier is not provided with the left shift mechanism, and a left shift by the post-operation normalization is required,
A method of reading the intermediate result Z after the operation of the multiplier and before the normalization and performing the post-operation normalization processing by using, for example, a general-purpose shifter mechanism and a general-purpose exponential arithmetic unit can be considered. It goes without saying that the invention can be applied.

Further, in the above example, the operation for denormalized numbers has been described as an example, but "infinity", "not a number", and "zero" other than denormalized numbers are not particularly distinguished from denormalized numbers. ,
Based on the result of being thrown into the floating point arithmetic unit of the present invention and separately processed by firmware or the like (the arithmetic result in this case can be definitely determined by the IEEE standard),
By handling the result of the arithmetic unit, for example, deciding whether or not to ignore it, the floating point arithmetic according to the IEEE standard can be performed at high speed in all cases.

As described above, the present invention relates to a denormalized number processing method in a floating point processing apparatus that uses the IEEE standard or a binary floating point representation format based on the IEEE standard. Even if the numbers are strictly defined and the operand data is a denormalized number, if the precision of the intermediate result is sufficiently secured, the result calculated without the pre-operation normalization processing will be normalized after the operation. Paying attention to the fact that a correct result can be obtained by doing so, it is detected whether the exponent part of the operand data is the minimum value (E = 0) for detecting whether it is a denormalized number or not. The output of the result controls the input of operand data to the floating-point arithmetic unit, and it is possible to perform unified floating-point arithmetic without performing pre-operation normalization processing on operands other than normalized numbers. Characteristic A.

〔The invention's effect〕

As described above in detail, the denormalized number processing method of the present invention uses the IEEE standard or the binary floating point representation format conforming to the IEEE standard, and the operand data is the above denormalized number. However, in a binary floating-point processor having a mechanism for operating as having an infinite exponent range, whether or not all the bits forming the exponent part E of each of the two input operand data are "0". If the exponent E is detected to be "0", the exponent value supplied to the exponent calculator is forcibly set to "1" for the corresponding operand data side. 'age,
Further, when the 1-bit integer part supplied to the mantissa operation unit is set to '0' and at least 1 bit of the exponent part E is '1', the exponent part of the operand data is set to the corresponding operand data side. Since the 1-bit integer part supplied to the exponent operation part and the mantissa operation part is operated as '1', the operation designed optimally for the processing of normalized numbers is performed. Without major remodeling of the vessel,
It can handle denormalized operands, so
The amount of hardware required for pre-computation normalization processing and the processing time can be saved, and the arithmetic processing for denormalized numbers in the normalization arithmetic mode in the IEEE standard etc. can be performed in terms of both hardware volume and time. There is an effect that can be greatly improved.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a diagram for explaining a conventional denormalized number processing system. In the drawings, 1 is a sign arithmetic circuit (∀), 2 is an exponential arithmetic circuit, 3 is a mantissa arithmetic circuit, 4 is a post-exponential arithmetic normalization circuit, or a post-arithmetic normalization correction circuit, 5 is a post-mantissa arithmetic normal Circuit, 60 is an E ₁ = 0 detection circuit, 61 is an E ₂ = 0 detection circuit, 7 is a negation circuit, 8 is a selector, S ₁ , S ₂ , S are sign bits, E ₁ , E ₂ , E are exponents Parts, F ₁ , F ₂ , and F represent the mantissa part, or the fractional part thereof, and L ₁ and L ₂ represent the integer part of the mantissa part, respectively.

Claims (1)

(57) [Claims] 1. A 1-bit sign part S and an m-bit exponent part E
, And the n-bit mantissa F, if E = 2 ^m −1 and F ≠ 0, not a number (NAN), if E = 2 ^m −1, and F = 0, (−1) ⁵ × ∞ …… (± infinity) 0 <E <2 ^m −1, (−1) ^S × (1.F) × 2 ^E-bias …… (normalized number) E = 0 and F ≠ When 0, (−1) ^s × (0.F) × 2 ^1-bias (unnormalized number) When E = 0 and F = 0, (−1) ^s × 0 (± 0) where , Bias indicates a bias value. In the binary floating-point processor, which has a floating-point format that represents each of the two, and has a mechanism that operates as if the operand data had an infinite exponent range even in the case of the above denormalized number, two input operand data Means (60, 61) for detecting whether or not all the bits constituting the exponent part E are '0', and the exponent part E is '0' in the means (60, 61). If it is detected that the value of the exponent part supplied to the exponent operation part (2) is forced to be “1” on the corresponding operand data side, and is also supplied to the mantissa operation part (3). When the 1-bit integer part is 0, and at least 1 bit of the exponent part E is '1', the exponent part of the operand data for the corresponding operand data side is the exponent operation part 2) and mantissa performance Part of the integer part of 1 bit supplied to (3) as '1', a denormalized number of processing method characterized by the floating-point operation.