JP2518030B2 - Shift circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a shift circuit used in a data processing device, and more particularly to detection of a code error thereof.

[Prior Art] FIG. 5 is an explanatory diagram relating to a shift of data having a parity bit. FIG. 5 (a) is before shift, FIG. (Shift) state.

In the figure a0, a1, a2, ... …… a8, a9, ………… b0, b1, b2,…
... are data bits, c0, c1, cn, d0, d1, dn are parity bits, and 8 bits (generally m
1) by adding 1 parity bit for each
This is an example of configuring individual data. A2 ⇒ b after the shift
0, a3⇒b1, ……… a8⇒b6, a9⇒b7, but c0 has no relation to the shifted data b0 to b7, so this is removed and the parity for b0 to b7 is removed. Generate bit d0 and insert it in the position shown.

FIG. 4 is an explanatory diagram showing a conventional circuit of this type,
In the figure, (1) is an n-bit master barrel shifter, (9) is an n-bit slave barrel shifter, (11)
Is a parity checker, (12) is a parity generator, and (13) is a comparison circuit. N is an integer multiple of m,
Let n = km.

The input data has a total of k (m + 1) bits, but m + 1
A parity checker (11) performs a parity check on each bit data, the parity bits are deleted here, and the data is input in parallel to barrel shifters (1) and (9) as n = km bit data. .

When both barrel shifters (1) and (9) operate normally, the two inputs of the comparison circuit (13) are always in agreement, and the parity bit corresponding to the output of the barrel shifter (1) (Fig. 5, d0, d1, ...) is the parity generator (12)
Generated by.

[Problems to be Solved by the Invention] Since the conventional circuit is configured as described above, it is possible to independently perform the parity check of the input signal, the operation check of the master barrel shifter, and the parity check of the output signal. However, there is a problem that the redundancy is large and the volume of the circuit is large accordingly. Further, since the parity bit for the output signal is generated from the output signal, there is a problem that the output parity signal is delayed by this generation time.

One example of measures for removing this signal delay is JP-A-59.
It is disclosed as a "shift circuit" (hereinafter referred to as prior art) in Japanese Patent Laid-Open No. 158438. However, in this prior art,
There is a problem that only a smaller number of bits than the number of input signal bits can be taken out, and shifting can be performed only in a single direction.

The present invention has been made to solve the above-mentioned problems in the conventional one, and it is possible to obtain a shift circuit constituted by a simple circuit, take out an output having the same width as an input signal, and shift in both directions. The purpose of the invention is to obtain a shift circuit that enables the above.

[Means for Solving the Problem] A shift circuit according to the present invention is provided with an m-bit parity predict circuit corresponding to each input word, and the shift number is represented by pm + q (p is 0 or a positive integer, q
<M), it is decided to create the parity bit after the shift in the q-bit shift.

[Operation] It is easy to generate the parity bit after pm + q bit shift from the parity bit after q bit shift, and the entire circuit configuration can be simplified by providing the m bit parity predict circuit.

Embodiments Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is an explanatory view showing an embodiment of the present invention, in which the same reference numerals as those in FIG. 4 indicate the same or corresponding portions, and (2)
Is the parity predict circuit, (7) is the input data,
(8) is an output parity signal.

In this case, the input data (7) is a signal including a parity bit, and the parity predict circuit (2) is input with the parity bit added, and n bits
The parity bit is removed and input to the master barrel shifter (1). The operation of the n-bit master barrel shifter (1) is the same as that of the n-bit master barrel shifter (1) of FIG.

FIG. 2 is a block diagram showing an example of the configuration of the parity predict circuit (2). In the figure, the same reference numerals as those in FIG. 1 indicate the same parts, and (3) shows an 8-bit parity predict circuit and (4) respectively. ) Is an 8-bit shifter,
(5) is a control circuit, (6) is a control signal, (9) is a shift count signal, and (10) is a shift direction signal.

FIG. 3 is a block diagram showing an example of the 8-bit parity predict circuit (3) in FIG. 2, in which (7) is the same input signal as (7) in FIG. 2 and (6a) is from the previous stage. Control signals (6) and (6b) are control signals (6) and (30) to the subsequent stage, mask logic, (31) is a shift signal from the control circuit (5), and (32) is a parity bit generation circuit, (33) is an exclusive OR circuit.

Next, the operation will be described. Control circuit (5)
Shift count signal (9) and shift direction signal (10)
Although and are input, change this to the shift count for left shift. For example, a right 2 bit shift is converted to a left 62 bit shift. Next, this shift number is expressed in the form of pm + q. Since m = 8 in the example shown in the figure, p = 7 and q = 6 (62 = 7 × 8 + 6) in the left 62-bit shift, so the 8-bit parity predict circuit (3) is set to -Control the shifter (4) with p.

Each input data (7) composed of 8 data bits and 1 parity bit is input to each mask logic (30). The q-bit left shift command is input as a shift signal (31), and only the data that is not shifted out of each input data (7) is logic "0" in the mask logic (30).
It is controlled so that only q bits and input parity bits to be shifted out are input to the parity bit generation circuit (32). The parity bit generation circuit (32) checks whether the number of logic "1" bits included in the discharged bits is an even number (including 0) or an odd number. Output a signal.

By the way, input data (7) to the mask logic (30).
The parity of the data should be maintained at the time when is input, and the fact that the odd number "1" is discharged from this means that the parity of the remaining data is no longer valid.
Ejecting an even number of "1" means that the parity of the remaining data is preserved. In this sense, the output of the parity bit generation circuit (32) is tentatively called a parity bit, which is used as one input of the exclusive OR circuit (33) and is sent to the next stage as a control signal (6b). . Since the bits shifted out from the previous stage are input to the next stage, the logic of the control signal (6a) from the previous stage and the parity bit generation circuit (32) of the relevant stage should be used to determine what happens to the parity of that stage. It will be determined by the exclusive OR of the outputs.

Therefore, the output of the exclusive OR circuit (33) is
If input to the corresponding stage of the shifter (4), the parity bit for each data at the time of q-but left shift can be obtained. Actually, a parity bit for the left shift of pm + q bits is required, so the input of the 8-bit shifter (4) is shifted to the left by p bits to be the output parity signal (8), and this parity bit is n bits. It is added as a parity bit of each m-bit word output from the master barrel shifter (1). The data to which the parity bit is added is checked by a parity checker (not shown).

With the above configuration, since the output parity signal (8) is created by the parity predict circuit (2) in parallel with the operation of the n-bit master barrel shifter (1), there is no time delay and the parity is -The check is performed only once at the final stage, but if there is a parity error at the stage of the input data (7), the output of the parity bit generation circuit (32) becomes an error and this is the output parity signal (8). Appears as an error and is detected by the parity checker in the output stage.

Further, when an error occurs due to a failure in the barrel shifter (1) or the parity predict circuit (2), the output of the barrel shifter (1) and the output parity signal (8) cannot be associated with each other, and the error checker of the output stage is not provided. Detected in.

[Effects of the Invention] As described above, the present invention has an effect that it is possible to obtain a shift circuit in which the amount of hardware is reduced and the processing speed is improved.

[Brief description of drawings]

FIG. 1 is an explanatory view showing an embodiment of the present invention, FIG. 2 is a block diagram showing a configuration example of the parity predict circuit of FIG. 1, and FIG. 3 is an 8-bit parity predict circuit of FIG. FIG. 4 is an explanatory diagram showing a conventional circuit, and FIG. 5 is an explanatory diagram relating to shift of data having parity bits. (1) is an n-bit master barrel shifter, (2) is a parity predict circuit, (3) is an 8-bit parity predict circuit, (4) is an 8-bit shifter,
(5) is a control circuit, (6) is a control signal, (7)
Is input data, (8) is an output parity signal, (30) is a mask logic, (31) is a shift signal, (32) is a parity bit generation circuit, and (33) is an exclusive OR circuit. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Claims] 1. A 1-bit parity bit is added to each m-bit data bit to form 1 data, and k pieces of such data are concatenated and input, and an arbitrary number of bits in an arbitrary direction. In the shift circuit that shifts to and outputs the data, the parity bit is deleted from the input data, and the n = km-bit data that is configured by concatenating the m-bit data bits is input and any number of bits can be input in any direction. A barrel shifter for shifting and outputting, and a parity predict circuit for generating one parity bit corresponding to each m bits of the output bits of the barrel shifter from the input data are provided, and the parity predict circuit has k inputs. K pieces of m bits are provided corresponding to each input data of data, and are arranged in the order of the corresponding input data. And utility-Puridikuto circuit, and a one k-bit shift register, the number of the shift pm + q (p is 0 or a positive integer, q <m)
Then, in each of the above m-bit parity predict circuits, a parity bit for q bits to be shifted out is generated and sent to the adjacent lower stage, and this parity bit and the parity bit sent from the adjacent upper stage. To generate a parity bit of the stage and input it to the corresponding stage of the shift register, and the shift register shifts p bits to generate each parity bit corresponding to each m bit of the output of the barrel shifter. Shift circuit characterized by.