JP2523170B2 - Burst error detection circuit - Google Patents

Description

The present invention relates to a burst error detection circuit in a digital transmission device.

(Prior Art) In a digital transmission system, the state of the transmission line,
An error occurs in the transmitted signal due to the influence of noise from the outside and further due to abnormal operation of the device. This error is divided into a random error that is accidental and one-shot, and a burst error that continuously occurs for a certain period of time. The present invention relates to the latter detection of burst errors, and when a burst error occurs, it is necessary to process the entire signal received during the duration of the burst error as a signal containing an error.

FIG. 2 is an example of a conventional burst error detection circuit, in which a burst error occurs when two or more of eight consecutive parity detection signals obtained by parity detection are parity errors. Is.

In FIG. 2, the received signal 21 is sequentially input in parallel to the input terminals A to H of the parity error detection circuit 24 at a predetermined timing. Parity error detection circuit 24 receives the signal
A parity check is performed for 21 and a parity detection signal (a pulse is output when a parity error is not detected, and a pulse output is stopped when a parity error is detected) is output. This parity detection signal is sequentially input to the input terminal A of the 8-bit shift register 25 based on the clock 22. The 8-input NAND circuit 27 negates the logical product of the outputs from the output terminals Q _A (first stage) to Q _H (8 th stage) of the 8-bit shift register 25, and outputs the error input counter 32 and the error output counter. Input to each ▲ ▼ terminal of 33. That is, when there is at least one parity error in the 8-bit shift register 25, the reset of the error input counter 32 and the error output counter 33 is released. On the other hand, the 3-input OR circuit 29 outputs the output from the output terminal Q _A and the output terminal Q inverted by the NOT circuit 28.
The logical sum of the output from _H and the clock from the NOT circuit 26 is input to the clock terminal CK of the error input counter 32. The error input counter 32, for each input of the clock,
That is, the parity error is 1 in the 8-bit shift register 25.
Counts each time the number increases. The 3-input OR circuit 31 ORs the output from the output terminal Q _H , the output from the output terminal Q _A inverted by the NOT circuit 30, and the clock from the NOT circuit 26, and the error output counter 33. Input to the clock terminal CK of. The error output counter 33 counts each time the clock is input, that is, each time the parity error in the 8-bit shift register 25 decreases by one. It is to be noted that an error input counter 32 is used as the clock which is obtained by inverting the clock 22 by the NOT circuit 26.
This is because the clock is given after the reset is released in the error output counter 33. The subtraction circuit 34 calculates the difference between the value of the error input counter 32 and the value of the error output counter 33, and resets the 8-bit shift register 35 when the count difference is 2 or more. 8bit shift register 35 is fixed to the input is "H", the output terminal Q _H "L" and is reset, as "H" from "L" after 8 clocks after reset is released, a burst error Output the detection signal. This burst error detection signal indicates a burst error detection section, and when attention is paid to any eight consecutive parity detection signals in the burst error detection section, two or more of them correspond to a parity error. .

(Problem to be Solved by the Invention) However, in the circuit having the above configuration, the number of parity errors in the 8-bit shift register 25
The error input counter 32, the error output counter 33, the subtraction circuit 34, and other peripheral circuits are required because the difference between the number of input parity errors and the number of output parity errors is calculated. There was a problem that it became complicated.

The present invention reduces the complexity of the circuits described above.
It is an object of the present invention to provide a burst error detection circuit having a simplified circuit configuration by using only logic gates instead of the counter and subtraction circuit.

(Means for Solving the Problem) The present invention provides a parity error detection circuit for detecting the presence or absence of a parity error in a received signal, and an n-stage first shift register for sequentially inputting detection results from the parity error detection circuit. And the first stage of the first shift register or n
A detection circuit that outputs a reset signal when the content of the first stage corresponds to the parity error and the content of at least one of the second to (n-1) th stages corresponds to the parity error; A burst error in which the input is fixed to a predetermined voltage and which is secondly reset by the reset signal, and which outputs a burst error detection signal from the (n-3) th stage of the second shift register. It is a detection circuit.

(Operation) The n-th first shift register sequentially inputs the detection result from the parity error detection circuit based on a predetermined clock and shifts the result. The detection circuit monitors the contents of each stage of the first shift register, the contents of the first stage or the nth stage correspond to a parity error, and from the second stage to (n-1).
A reset signal is output when the contents of at least one stage up to the stage corresponds to a parity error. The second shift register sets the output of the (n-3) th stage to "L" level by the reset signal, and sets it to "H" level after (n-3) clocks.

That is, in the first shift register, if the first to (n-1) th stages include detection results (hereinafter referred to as parity signals) corresponding to two or more parity errors, a parity error signal is generated. When one is output,
Alternatively, when one or more parity error signals are included in the first to (n-1) th stages and one parity error signal is input and the number increases by one, the second shift register is changed each time. It is to reset. As a result, starting from the time when two parity error signals are first included in the first to (n-1) th stages of the first shift register, (n-1) It is possible to obtain from the second shift register a burst error detection signal whose end point is (n-3) clocks after the number of parity error signals included in the second stage is reduced from two to one.

(Embodiment) FIG. 1 shows an embodiment of the present invention, in which two or more of eight consecutive parity detection signals obtained by the parity check are parity error signals as in the case of FIG. It is said that a burst error has occurred.

In FIG. 1, 1 is a received signal, 2 is a clock, 3 is a burst error detection signal, 4 is a parity error detection circuit, and 5 is 9 bits.
Shift register, 6 is a 7-input AND circuit, 7 is a 2-input AND circuit, 8
Is a 2-input OR circuit, and 9 is a 6-bit shift register.

Next, the operation of this embodiment will be described with reference to the time chart shown in FIG.

Received signal 1 is input terminal A of parity error detection circuit 4.
The clock 2 is sequentially input to H in parallel at a timing. In FIG. 3, only the received signal input to the input terminal A is shown for simplification of the drawing. The parity error detection circuit 4 performs a parity check on the received signal 1 that has been input and outputs a parity detection signal. This parity detection signal is a pulse whose output is stopped when it corresponds to a parity error signal. In FIG. 3, since a parity error is detected for the received signals A _{7 to} H ₇ and A _{8 to} H ₈ , a parity error signal is output from the parity error detection circuit 4 at the corresponding times t ₇ and t ₈ and a pulse is present. This is an example in the case of not performing. The parity detection signal is sequentially input to the terminal A of the 9-bit shift register 5, and is sequentially shifted from the first stage to the ninth stage based on the clock 2. 9b in Fig. 3
The waveforms at the output terminals Q _{A to} Q _I of each stage of the it shift register 5 are shown. Here, the number of stages of the 9-bit shift register 5 is n when the number of parity detection signals when defining a burst error is (n-1), and in the present embodiment, n-1.
= 8 so there are 9 rounds. Output of the output terminal Q _A of the first stage of the 9-bit shift register 5 and the output terminal of the ninth stage
The output of Q _I is logically ANDed by the 2-input AND circuit 7, and “L” is output when at least one of them corresponds to the parity error signal. Further, each output from the output terminal Q _B of the second stage of the 9-bit shift register 5 to the output terminal Q _H of the eighth stage is ANDed by the 7-input AND circuit 6, and at least one of the outputs is parity. "L" is output when the error signal is detected. 7-input AND circuits 6 and 2 are shown in FIG.
The output waveform of the input AND circuit 7 is shown. The 2-input AND circuit 7 takes the logical sum of the outputs of the 7-input AND circuit 6 and the 2-input AND circuit 7 and inputs it to the ▲ ▼ terminal of the 6-bit shift register 9 to reset it. That is, the 6-bit shift register 9 receives the parity error at the first stage of the 9-bit shift register 5 or outputs the parity error at the eighth stage, and at least one of the second stage to the eighth stage. Whenever there is a parity error signal in the stage, it is reset. When the 6-bit shift register 9 is reset, all the stages are set to "L", so that the output terminal Q _F of the sixth stage becomes "L". However, since the input of the 6-bit shift register 9 is fixed to "H", the output terminal Q _F changes from "L" to "H" unless reset again 6 clocks after the reset. As a result, the burst error detection signal 3 is output from the output terminal Q _F of the 6-bit shift register 9.

 Hereinafter, a more specific description will be given.

FIG. 3 shows a case where a parity error is detected in the received signals A _{7 to} H ₇ and A _{8 to} H ₈ . Therefore, when two or more of the eight parity detection signals are parity error signals, that is, when two or more parity errors are detected within eight periods, a burst error occurs
Since the first burst error has occurred within the 8 periods from T ₁ (not shown) to T ₈ and the last burst error has occurred within the 8 periods from T ₇ to T ₁₄ . After all period T ₁
14 periods through T ₁₄ is a burst error occurrence section. Therefore, the burst error detection signal corresponding to these 14 periods is 6 bits.
It is necessary to output from the output terminal Q _F of the shift register 9.

First, in the period T ₉ , since the output terminals Q _A and Q _{B of the 9-} bit shift register 5 both become “L”, “L” is output from the 2-input OR circuit 8 and the 6-bit shift register 9 is reset and its output terminal. Q _F becomes “L”. This period T ₉ is a period in which two parity error signals are included for the first time from the first stage to the eighth stage of the _9- bit shift register 5,
It is the starting point of the burst error detection signal 3. Output terminal Q _F
"L" is hereinafter least six clocks in, i.e. until the time period T _15, is maintained.

Next, in the period T ₁₆ , since the output terminals Q _H and Q _I of the 9-bit shift register 5 both become “L”, “L” is output from the 2-input OR circuit 8 and the bit shift register 9 is reset again. The output terminal Q _F continues to be "L". this period
T ₁₆ is a period in which the number of parity error signals present in the first to eighth stages of the 9-bit shift register 5 is reduced from two to one, and serves as a reference for determining the end point of the burst error detection signal 3. The output at the output terminal Q _F becomes 6 cloaks thereafter, that is, becomes “L” until the period T ₂₂ and becomes H at the period T ₂₃ . From the output terminal Q _F of the 6bit shift register 9,
It becomes “L” for 14 periods. Burst error detection signal 3
Is output, and the period length (14 periods) of the burst error detection signal 3 matches the period length (14 periods) of the burst error occurrence sections T _{1 to} T ₁₄ in the reception signal described above. . Therefore, by delaying the received signal by a predetermined period, the burst error occurrence section and the burst error detection signal 3 can be temporally matched.

As described above, in this embodiment, a burst error is present when two or more of eight parity detection signals correspond to a parity error signal, but the present invention is different from the above-described eight parity detection signals. It is apparent from the present embodiment that it can also be applied to the case.

As described above in detail, according to the present invention, the burst error occurrence section is determined by detecting the presence or absence of a parity error in a predetermined stage of the n-stage shift register. It can be configured only by itself and can be simplified as compared with a conventional circuit using an error input counter, an error output counter, a subtraction circuit, and the like.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a circuit diagram of a conventional burst error detection circuit, and FIG. 3 is a time chart of the circuit shown in FIG. 1 ... Received signal, 2 ... Clock, 3 ... Burst error detection signal, 4 ... Parity error detection circuit, 5 ... 9bit
Shift register, 6 …… 7 inputs AND circuit, 7 …… 2 inputs A
ND circuit, 8 …… 2 input OR circuit, 9 …… 6bit shift register.

Claims (1)

(57) [Claims] 1. A parity error detection circuit for detecting the presence or absence of a parity error in a received signal, an n-stage first shift register for sequentially inputting detection results from the parity error detection circuit, and the first shift register. The contents of the first stage or the nth stage correspond to the parity error, and (n-1) from the second stage
A detection circuit that outputs a reset signal when the contents of at least one of the stages up to the stage corresponds to a parity error, and a second shift register whose input is fixed to a predetermined voltage and which is reset by the reset signal. A burst error detection circuit, comprising: outputting a burst error detection signal from the (n-3) th stage of the second shift register.