JP2523398B2 - Control method for fetching instruction data to instruction cache - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] Regarding a data fetch control method for an instruction cache in a computer having an instruction cache and an operand cache, it is possible to register data in the instruction cache without executing an instruction sequence. The illegal code search control unit and the instruction illegal code interrupt control unit are provided for the purpose of executing the instruction, and the illegal code search control unit sets the address to the operand Set as the access address for the cache, issue an operand fetch request, check whether the read data is an invalid code, and if it is not an invalid code, update the access address and return to the processing. If it is an invalid code, , Store the access address corresponding to the illegal coded data in a predetermined storage means and store the address. Is configured to perform a process for starting an illegal code interrupt control unit, the instruction unduly code interrupt control unit, when activated, '
The address of the storage means is set as an access address for the instruction cache, and a process for issuing an instruction fetch request is performed.

[Industrial applications]

According to the present invention, a computer having a cache having a structure divided into an instruction cache and an operand cache can fetch data into the instruction cache without executing the instruction.

[Conventional technology]

In the conventional method, since the instruction cache and the operand cache are one shared cache, the fetch into the cache can be registered in block data units by operand access.

The method of registration in the cache will be described with reference to FIG. In FIG. 3, reference numeral 111 denotes an instruction execution control unit, 112
Is an operand access control unit, 160 is a cache, 200
Is a main memory, 210 is an instruction data storage area, 220 is an access data storage area, and Bi (i is 1, 2, ...) Is a block area.

Instruction execution controller 111 and operand access controller 1
12 is in the processor. The cache 160 is
It holds a copy of the data in main memory 200,
It is divided into a plurality of block areas B1, B2, .... Data transfer between the cache 160 and the main storage device 200 is performed in block units. The cache 160 resides in the storage control unit.

When the instruction execution control unit 111 issues an instruction fetch request, the storage control unit checks whether or not the corresponding instruction data exists in the cache 200, and if there is, reads the corresponding instruction data from the cache 200 and outputs the instruction. To the execution control unit 111, and if it does not exist, read one block of data including the relevant instruction data from the main storage device 200,
While passing the relevant instruction data to the instruction execution control unit 111,
Write the instruction data block to cache 160.

When the operand access control unit 112 issues an operand fetch request, the storage control unit performs the same operation and passes the operand data to the arithmetic unit.

[Problems to be Solved by the Invention]

As described above, in the case of one shared cache, it is possible to register the specified block data (instruction string) in the cache by operand access (read operation for the instruction string). there were.

However, if there is an instruction cache and an operand cache, registration to the operand cache can be performed by the conventional access, but data registration to the instruction cache cannot be performed by the operand access. If the instruction was not executed, data could not be registered in the instruction cache.

The present invention was created in view of this point,
The purpose is to enable data to be registered in the instruction cache without executing the instruction sequence.

[Means for solving the problem]

FIG. 1 is an explanatory view of the principle of the present invention. The computer on which the present invention is based has a storage control unit having an instruction cache 161 and an operand cache 162, and a hardware mechanism (not shown) for executing instructions.

The storage control unit, when an instruction fetch request is issued, issues a data instruction cache of the address specified by the request.
161 is checked to see if it exists, and if it exists, the corresponding data is read from the instruction cache 161 and passed to the hardware mechanism for executing the instruction. The data is read from the storage device 200, written in the instruction cache 161, and the corresponding data is passed to the hardware mechanism for instruction execution. Also, when an operand fetch request is issued, the data at the address specified by the request is written in the operand cache 16
It is checked whether or not it exists in 2, and if it exists, the corresponding data is read from the operand cache 162 and passed to the arithmetic unit. If it does not exist, one block of data including the corresponding data is read from the main storage device 200. And writes the data to the operand cache 162 and passes the corresponding data to the arithmetic unit.

The hardware mechanism for instruction execution generates an illegal instruction code interrupt when the instruction code portion of the data passed as instruction data is not defined as an instruction code.

The present invention provides an instruction illegal code interrupt control unit 113 and an illegal code search control unit 114 in the above computer.
And are provided.

The illegal code search control unit 114 has a designated address.
When the activation is instructed, the address is set as the access address for the operand cache 162, an operand fetch request is issued, it is checked whether the read data is an invalid code, and if it is not an invalid code, access is made. Returning to the processing after updating the address, if the code is an illegal code, the access address corresponding to the data regarded as the illegal code is stored in a predetermined storage means and the instruction illegal code interrupt control unit 113 is activated. Is configured to do.

When activated, the instruction illegal code interrupt control unit 113 is configured to set the address of the storage means as an access address to the instruction cache 161 and issue an instruction fetch request.

[Action]

First, the address of the instruction data area of the main storage device is designated as the head address, and the illegal code search control unit 114 is activated.

The illegal code search control unit 114, when activated, reads an instruction data block from the main storage device 200 and stores it in the operand cache 162.
The block is read every 2 bytes and the illegal code is searched. The illegal code is a code that is not defined as an instruction code, and is, for example, a code such as “00” or “FF” in hexadecimal notation. If an illegal code is found, an address for specifying the storage location of this illegal code in the main storage device is stored in the storage means, and the instruction illegal code interrupt control unit 113
To start.

When the instruction illegal code interrupt control unit 113 is activated,
The address of the storage means is read, and an instruction fetch request is issued using this address as an address for the instruction cache. In the storage control unit, the corresponding data is stored in the instruction cache 16
If it exists in 1, the relevant data is immediately cached in the instruction cache 1
The data is read from 61 and sent to the hardware mechanism for instruction execution. If it does not exist, one block of data including the corresponding data is read from the main storage device 200 and written to the instruction cache 161, and the corresponding data is executed by the hardware for instruction execution. Send to wear organization.

Assuming that the corresponding data does not exist in the instruction cache 161, one block of instruction data is registered in the instruction cache 161, and the corresponding data (in this case, an instruction having an invalid instruction code) is used for instruction execution. Sent to the hardware mechanism. The hardware mechanism analyzes the input corresponding data. Since it is an illegal instruction code, an illegal instruction code interrupt occurs. The illegal instruction code interrupt trigger is released by the illegal instruction code interrupt control unit 113.
As described above, according to the present invention, data can be registered in the instruction cache without executing the instruction.

〔Example〕

FIG. 2 is a diagram for explaining one embodiment of the present invention. In the figure, 100 is a processor, 113 is an illegal instruction code interrupt control unit, 114 is an illegal code search control unit, 150 is an address data storage unit, 161 is an instruction cache, 162 is an operand cache, 200 is a main storage device, 301 is a program starting part, 302 is a test program execution control part, and Bi (i is 1,
2, ...) indicates the block areas.

The start-up unit 301 of the program selects an address existing in the instruction data area of the main storage device 200 as the start address, and gives the start address and the start instruction to the illegal code search control unit 114.

The processor 100 is provided with an instruction illegal code interrupt control unit 113 and an illegal code search control unit 114. Instruction cache 161 and operand cache 162
Exists in the storage control unit. The instruction data corresponding to the instruction fetch request is sent to hardware for instruction execution (including an instruction decoder), and instruction execution based on the instruction data is started.

The illegal code search control unit 114 performs the following processing. When the start instruction is given, the illegal code search control unit 114 sequentially reads the instruction sequence after the designated start address at the 2-byte boundary and checks whether the data at the 2-byte boundary is an illegal code. The illegal code means a code that is not defined as an instruction code, and for example, "00" or "FF" (hexadecimal notation) corresponds to this.

In order to check whether the data on the 2-byte boundary is an illegal code, the illegal code search control unit 114 issues an operand fetch request. Upon receiving the operand fetch request, the storage control unit checks whether the data exists in the operand cache 162, and if there is, reads the corresponding data from the operand cache 162 and controls the illegal code search. When it does not exist, the instruction data block containing the relevant data is read from the main memory device 200, and the relevant data is passed to the illegal code.
The relevant instruction data block is written to the operand cache 162 while being passed to the search control unit 114. When an illegal code is found, the illegal code search control unit 114 writes the address of the illegal code in the address data storage unit 150 and activates the instruction illegal code interrupt control unit 113.

For example, the instruction data block is a 2-byte A instruction, 6
It is assumed that the B instruction is stored in the addresses 00 to 01 and the B instruction is stored in the addresses 02 to 07. Illegal code search control unit 114
First checks whether the 2-byte data (A instruction) at addresses 00 and 01 is an illegal code. Since it is not an illegal code, the illegal code search control unit 114
It is checked whether or not the byte data at the address and the address 03 (the instruction code of the B instruction and the 1-byte data of the address portion following this) is an illegal code. Since it is not an illegal code, the illegal code search control unit 114 next checks whether or not the 2-byte data at addresses 04 and 05 is an illegal code.
Assuming that the 1-byte data at address 04 does not belong to the set of instruction codes, the 2-byte data at addresses 04 and 05 is regarded as an invalid code, and address 04 is written in the address data storage unit 150. Note that there are two-byte instructions, four-byte instructions, six-byte instructions, and eight-byte instructions.

When the instruction illegal code interrupt control unit 113 is activated,
The data in the address data storage unit 150 is read, this is set in the address register for the instruction cache, and the instruction fetch request is issued. The storage control unit checks whether the corresponding data exists in the instruction cache 161, reads the corresponding data from the instruction cache 161, and sends it to the hardware (for executing the instruction) if it exists, and if it does not exist, the corresponding The instruction data block including the data is read from the main memory 200, the relevant data is sent to the hardware (for executing the instruction), and the relevant instruction data block is written in the instruction cache 161.

When the instruction data is input, the hardware for executing the instruction first decodes the instruction. In this case, since the instruction code is an illegal code, an illegal instruction code interrupt occurs.
When an illegal instruction code interrupt occurs, the instruction illegal code interrupt control unit 113 performs an interrupt canceling process, and notifies the execution control unit 302 of the test program that the instruction data has been fetched into the instruction cache 161. The test program execution control unit 302 starts a predetermined test condition / test item.

〔The invention's effect〕

As is clear from the above description, according to the present invention, it is possible to register the instruction data (column) in the block unit on the instruction cache without performing the functional execution (functional operation) of the instruction. Therefore, the instruction cache registration algorithm test can be performed as before.

It is possible to change the instruction cache state to an arbitrary environment.

It becomes possible to test the instruction cache that could not be tested.

[Brief description of drawings]

FIG. 1 is a diagram for explaining the principle of the present invention, FIG. 2 is a diagram for explaining one embodiment of the present invention, and FIG. 3 is a diagram for explaining fetching of data into the cache in a computer having one cache. . 100 ... Processor, 111 ... Instruction execution control section, 112 ... Operand access control section, 113 ... Instruction illegal code interrupt control section, 114 ... Illegal code search control section, 150 ... Address data storage section , 161 ... Instruction cache, 162 ... Operand cache, 200 ... Main storage device, 301 ... Program startup unit, 302 ... Test program execution control unit.

Claims (1)

(57) [Claims] 1. A storage control unit having an instruction cache (161) and an operand cache (162), and a hardware mechanism for executing instructions, wherein the storage control unit issues (a) an instruction fetch request. When it is determined, it is checked whether or not it exists in the data instruction cache (161) at the address specified by the request, and if it exists, the corresponding data is read from the instruction cache (161) and the hardware for instruction execution is read. (1) to the hardware mechanism for executing instructions, reading one block of data including the relevant data from the main storage device (200) and writing it to the instruction cache (161) when it does not exist. b) When an operand fetch request is issued, it is checked whether the data at the address specified by the request exists in the operand cache (162). If it exists, the corresponding data is read from the operand cache (162) and passed to the operation unit. If it does not exist, one block of data including the corresponding data is read from the main storage device (200) and the operand cache (162) is read. 162) and the corresponding data is passed to the arithmetic unit, and the hardware mechanism for instruction execution is such that the instruction code part of the data passed as instruction data is not defined as an instruction code. In the computer configured to generate an illegal instruction code interrupt, an illegal instruction code interrupt control unit (113) and an illegal code search control unit (114) are provided. (114) points the address to the operand cache (162) when the address is specified and activation is instructed. Access address, issue an operand fetch request, check whether the read data is an invalid code, and if it is not an invalid code, update the access address and return to the processing. If it is an invalid code, An instruction illegal code interrupt control unit (113) is configured to store an access address corresponding to data regarded as an illegal code in a predetermined storage unit and to activate an instruction illegal code interrupt control unit (113). ) Is configured so that, when activated, ′ sets an address stored in the storage means as an access address to the instruction cache (161) and issues an instruction fetch request. Control method for fetching instruction data into the instruction cache.