JP2523716B2 - Semiconductor memory device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a static random access memory.

[Conventional technology]

FIG. 7 shows the timing of writing in the conventional static random access memory (hereinafter referred to as SRAM). In particular, address signals A1 and A2, write control signal ▲
▼ is shown. The signal ▲ ▼ selects the read state at the “H” level and the write state at the “L” level. When the SRAM is actually mounted on the board, the address signal has a skew t ₄ as shown in FIG.
Since the signal ▲ ▼ has jitters t ₅ and t ₆ , the system cycle time T _c is T _c = t ₁ + t ₂ + t ₃ + t ₄ + t ₅ + t ₆ . Here, t ₁ , t ₂ , and t ₃ are the write pulse width, address setup time, and write recovery time, which are specifications of SRAM, respectively. However, a very fast SR
In AM, using the minimum specifications, T _c = t ₁ + t ₂ + t ₃ . Therefore, the cycle time of the system is increased by t ₄ + t ₅ + t ₆ and the high speed is impaired.

Therefore, one solution is to write the data with the signal () fixed at the "L" level, that is, in the written state. This is because the jitters t ₅ and t ₆ can be ignored by using this method. However, even if this method is used, since the address skew t ₄ still exists, the data of the memory cell transiently selected may be rewritten during the time of the skew t ₄ .

As one solution to this problem, there is a method of detecting a change in an address signal, generating a one-shot pulse, and using the pulse to prohibit writing in the chip. FIG. 8 shows the timing of this method, and FIG. 9 shows a block diagram of an SRAM using this method.

Next, the operation of this SRAM will be described with reference to these figures.

The address signal A1, A2, there is a skewed by time t _4. Further, the write control signal ▲ ▼ is fixed to the "L" level, that is, the write state. ATD1 and ATD2 are one-shot pulses in which an address change has occurred for addresses A1 and A2, respectively. The logical sum of these is taken and the write inhibit signal WI is generated. Where signal WI is pulse AT
Although the logical sum of D1 and ATD2 is used, the logical sum of signals obtained by waveform shaping the pulses ATD1 and ATD2 using a buffer may be used. Therefore, as shown in FIG. 8, the write control signal WE inside the chip is in the “L” level during the period including the skew t ₄ , that is, the write-inhibited state, and the memory cell selected transiently during the skew t ₄ . Data destruction can be prevented.

[Problems to be solved by the invention]

Since the conventional semiconductor memory device is configured as described above, as shown in FIG. 10, the skew t ₄ ′ is large (t ₄ ′).
> T ₄ ), the internal write control signal WE once becomes “H” level, that is, the write state, during the skew t ₄ ′,
There is a problem in that the data of the memory cell transiently selected during the skew t ₄ ′ may be destroyed by erroneous writing.

In order to solve this, it is conceivable to lengthen the width of the pulse ATD1, ATD2 or the signal WI, but in this case, if it is used at the conventional timing, the writable time inside the chip will be shortened and normal writing There is a problem that you can not do.

The present invention has been made in order to solve the above problems, and while ensuring a write time within the chip that can be normally written even when used at the conventional timing, the write control for the address skew is performed. Signal ▲
It is an object of the present invention to obtain a static type semiconductor memory device capable of stable writing while ▼ is fixed at "L" level.

[Means for solving problems]

A semiconductor memory device according to the present invention is a static semiconductor memory device having a plurality of address inputs and data read / write control inputs from the outside, detects a change in the address input, and performs a write operation inside a chip. A circuit for generating the first and second write-inhibit signals for inhibition for a certain period from the change of the address input, and the pulse width of the second write-inhibit signal from the pulse width of the first write-inhibit signal. And a circuit for generating a write inhibit release signal for releasing the write inhibit state for a certain period from the change of the read write control input when the read write control input changes from the read state to the write state. , The first and second write inhibit signals, the read / write control input signal, and And a write control circuit which outputs a memory read / write control signal for controlling a read / write operation to a memory inside the chip, and the write control circuit receives the read / write control input. When data is written by changing the address input while fixing the write state, the memory read / write control signal is controlled by the first and second write inhibit signals to at least the second write inhibit. The memory read / write control signal is set to write-disabled during a signal generation period, and after the address input is confirmed, the read / write control input is changed to the write state for a certain period to write data. In the case of, By disabling the second write inhibit signal, said first
The memory read / write control signal is controlled by the write inhibit signal, and the memory read / write control signal is set to be unwritable at least during the period when the first write inhibit signal is generated.

The semiconductor memory device according to the present invention is the semiconductor memory device according to claim 1, wherein the pulse width of the write inhibit release signal is longer than the pulse width of the second write inhibit signal.

[Action]

In the semiconductor memory device according to the present invention, in a static semiconductor memory device having a plurality of address inputs and data read / write control inputs from the outside, a change in the address input is detected to write data in the chip. A circuit for generating first and second write inhibit signals for inhibiting the operation for a certain period from the change of the address input, and a pulse width of the second write inhibit signal are
A circuit for making the pulse width longer than the pulse width of the first write inhibit signal, and a write inhibit release signal for releasing the write inhibit state when the read / write control input changes from the read state to the write state. A circuit that occurs for a certain period of time after a change in control input, the first and second write inhibit signals, the read / write control input signal, and the write inhibit release signal are input, and read to a memory inside the chip. A write control circuit for outputting a memory read / write control signal for controlling a write operation, wherein the write control circuit changes the address input while fixing the read / write control input to the write state to write data. When performing the above, the first and second write inhibit signals are used. The memory read / write control signal is controlled, and the memory read / write control signal is set to write disabled at least during the period when the second write inhibit signal is generated, and the read / write control input is set after the address input is confirmed. In the case of normal writing in which data is written by changing to the write state only for a certain period, the second write inhibit signal is invalidated by the write inhibit release signal, and the first write inhibit signal is generated by the first write inhibit signal. Since the memory read / write control signal is controlled and the memory read / write control signal is set to write-disabled at least during the period in which the first write-inhibit signal is generated, the read / write control input is set to the write state. The above address input is changed while it is fixed at Even if the data is written by using the address skew, it is possible to prevent the erroneous writing of the data due to the address skew. Furthermore, after the address input is confirmed, the read / write control input is changed to the write state for a certain period of time and the It is possible to secure a sufficient writing period even in the case of normal writing in which

Further, in the semiconductor memory device according to the present invention, in the semiconductor memory device according to claim 1, since the pulse width of the write inhibit release signal is made longer than the pulse width of the second write inhibit signal, the address skew is generated. Even if is large, the same operation can be performed.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, 1 is a circuit for increasing the pulse width, and 2 is a WE.
The buffer 3 is a write control circuit, and the other parts except the pulse width increasing circuit 1 are almost the same as the conventional SRAM shown in FIG. However, the buffer 2 generates the write inhibit release signal ▲ ▼ in addition to the WE buffer output signal WEA in which the signal ▲ ▼ is shaped and inverted.
Is an internal write control signal W using the four signals WEA, ▲ ▼ and the first and second write inhibit signals WI1 and WI2.
E is occurring. The signal WI1 is the SRAM signal shown in FIG.
It is the same signal as WI, and signal WI2 is a longer pulse than signal WI1.

2A and 2B show an example of the circuit 1 for increasing the pulse width and its timing waveform diagram. The inputs are connected to the gates of the N-channel MOSFET N1, P-channel MOSFETs P1, P2, P3 and P4, and the drains of the MOSFETs P1 and N1 are connected to the capacitors and connected to the next stage inverter. Since the P-channel MOSFETs P1, P2, P3, P4 are connected in series, the ability to drive point A to "H" level is smaller than the ability to drive point A to "L" level, and the waveform at point A is When the input changes, it changes as shown in FIG. 2 (b). Therefore, the rising edge of the output pulse is greatly delayed and the pulse width is increased as compared with the input pulse.

3 (a) and 3 (b) show an example of a write-prohibition release signal () generation circuit in the WE buffer 2 and its timing waveform diagram. A negative pulse ▲ ▼ is generated only at the trailing edge of the signal ▲ ▼ by ORing the signal at the point B in phase with the signal ▲ ▼ and the signal at the point C delayed and inverted from the signal at the point B. .

4A and 4B show an example of the write control circuit 3 and its timing waveform diagram. First, AND circuit A
In step 2, even if the second write inhibit signal WI2 (“H” is pulse) is generated, the write inhibit state is released when the signal ▲ ▼ (“L” is pulse) is generated, and the point D is at “L” level. , Becomes writable. Next, in the NOR circuit B, if the first write inhibit signal WI1 (“H” is a pulse) is generated, the output point E becomes “L” level and cannot be written even if the point D is writable. Finally, AND circuit C
Therefore, the internal write control signal WE becomes "H" only when both the signal WEA and the signal at the point E are writable levels ("H").
The level becomes writable.

Next, the operation of the SRAM using these circuits is shown in FIG.
This will be described with reference to FIG.

First, FIG. 5 shows a case where data is written while the signal () is fixed at "L" level. Address signal A1, A
When 2 changes at the skew t ₄ ′, pulses ATD1 and ATD2 are generated according to the respective addresses. Therefore, the first write inhibit signal WI1 is generated as shown in the figure. But W
The second write-inhibit signal WI2, which has a wider pulse width than I1, overlaps to form one large pulse. Therefore, the internal write control signal WE has no inversion pulse during the skew t ₄ ′, and erroneous write does not occur. Here, with respect to the pulse width of the signal WI2, the wider it is, the more margin can be provided for the skew t ₄ ′. However, if it is too wide, the writable period of the signal WE becomes too short, and normal writing cannot be performed. Therefore, it is better to make the pulse width of the signal WI2 as wide as possible in consideration of the margin for normal writing.

Next, FIG. 6 shows the case of using the conventional timing. The write control signal ▲ ▼ is clocked. When the signal ▲ ▼ rises, the internal write control signal WE also changes to "L" level and writing becomes impossible. Therefore,
If the signal ▲ ▼ rises quickly, the time after the signal WI2 is cut off, that is, the writable time is shortened, and there is a possibility that writing cannot be performed normally. Therefore, the signal ▲ ▼
The falling edge of is detected and pulse ▲ ▼ is issued,
The write protection by signal WI2 is released to secure sufficient write time. Here, the release of write protection by the pulse ▲ ▼ does not reach the signal WI1. It requires a few ns to precharge the bit line after the address change,
This is to prevent writing during that period.

Also, as shown in FIG. 11, the change of the address signal A2 and the signal ▲
If the falling edges of ▼ are at the same time or if the falling edges of signal ▲ ▼ are a little faster, if the pulse width of signal ▲ ▼ is
If it is shorter than the pulse width of WI2, the internal write control signal WE is once set to the “L” level, and it becomes impossible to secure a sufficient write time. Therefore, the signal ▲
The pulse width of ▼ must be set wider than the pulse width of the signal WI2.

In the above embodiment, the write control signal WE in the chip is controlled by using the write inhibit signals WI1 and WI2 and the write inhibit release signal ▲ ▼ as the input of the write control circuit. May be used as an input of the write circuit to prohibit the operation of the write driver that drives the bit line pair connected to the memory cell, and the same effect as the above embodiment can be obtained.

〔The invention's effect〕

As described above, according to the semiconductor memory device of the present invention, in a static semiconductor memory device having a plurality of address inputs and data read / write control inputs from the outside, a change in the address input is detected. ,
A circuit for generating first and second write inhibit signals for inhibiting a write operation inside the chip for a certain period from the change of the address input, and a pulse width of the second write inhibit signal are set to the first write A circuit that makes the pulse width longer than the pulse width of the inhibit signal and a write inhibit release signal for releasing the write inhibit state when the read / write control input changes from the read state to the write state from the change of the read / write control input. A circuit generated for a certain period of time, the first and second write inhibit signals, the signal of the read / write control input, and the write inhibit release signal are input to control the read / write operation to the memory inside the chip. And a write control circuit for outputting a memory read / write control signal for When data is written by changing the address input while fixing the read / write control input in the write state, the memory read / write control signal is controlled by the first and second write inhibit signals, and at least While the second write inhibit signal is being generated, the memory read / write control signal is set to write-disabled, and after the address input is confirmed, the read / write control input is changed to the write state for a certain period to write data. In the case of normal writing in which writing is performed, the second write-inhibit signal is invalidated by the write-inhibit release signal, and the memory read / write control signal is controlled by the first write-inhibit signal. The first write inhibit signal is generated. Since the memory read / write control signal is set to be not writable during the period, even if data is written by changing the address input while fixing the read / write control input in the write state, Skew can prevent erroneous writing of data,
Further, even in the case of normal writing in which the read / write control input is changed to the write state for a fixed period to write data after the address input is confirmed, it is possible to secure a sufficient write period. is there.

Further, according to the semiconductor memory device of the present invention, in the semiconductor memory device according to claim 1, the pulse width of the write inhibit release signal is made longer than the pulse width of the second write inhibit signal. The same effect can be obtained even if the skew is large.

[Brief description of drawings]

FIG. 1 is a block diagram showing a semiconductor memory device according to one embodiment of the present invention, FIG. 2 (a) is a circuit diagram showing a pulse width increasing circuit according to one embodiment of the present invention, and FIG. A timing diagram, FIG. 3 (a) is a circuit diagram showing a write inhibit release signal generating circuit according to an embodiment of the present invention, FIG. 3 (b).
Is its timing diagram, FIG. 4 (a) is a circuit diagram showing a write control circuit according to one embodiment of the present invention, FIG. 4 (b) is its timing diagram, and FIG. 5 is a semiconductor according to one embodiment of the present invention. FIG. 6 is a first operation timing chart of the memory device, FIG. 6 is a second operation timing diagram of the semiconductor memory device according to one embodiment of the present invention, and FIG. 7 is a first operation for explaining a conventional semiconductor memory device. Timing diagram, FIG. 8 is a second operation timing diagram for explaining a conventional semiconductor memory device, FIG. 9 is a block diagram showing a conventional semiconductor memory device, and FIG. 10 is a conventional semiconductor memory device. And FIG. 11 is a third operation timing chart of the semiconductor memory device according to the embodiment of the present invention. 1 is a pulse width increasing circuit, 2 is a WE buffer, AX and AY are address inputs, ▲ ▼ is a write control signal, ATD1 and ATD2 are one-shot pulses, WI1 and WI2 are write inhibit signals, ▲
▼ is a write protect release signal. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (2)

(57) [Claims] 1. A static semiconductor memory device having a plurality of address inputs and a data read / write control input from the outside, for detecting a change in the address input and for inhibiting a write operation inside the chip. A circuit for generating the first and second write inhibit signals for a certain period from the change of the address input, and a circuit for making the pulse width of the second write inhibit signal longer than the pulse width of the first write inhibit signal. A circuit for generating a write-prohibition release signal for releasing the write-prohibited state when the read-write control input changes from the read state to the write state for a certain period from the change of the read-write control input; And a second write inhibit signal, the read / write control input signal, and the write inhibit release And a write control circuit that outputs a memory read / write control signal for controlling a read / write operation to a memory inside the chip, the write control circuit sets the read / write control input to a write state. When writing data by changing the address input with the address fixed, the memory read / write control signal is controlled by the first and second write inhibit signals to generate at least the second write inhibit signal. In the case of normal writing, in which the memory read / write control signal is set to write-disabled during that period, and after the address input is confirmed, the read / write control input is changed to the write state for a certain period to write data. Is set to the second level by the write protection release signal. The memory read / write control signal is controlled by the first write inhibit signal by disabling the write-in inhibit signal, and the memory read / write control signal is generated at least during the period in which the first write inhibit signal is generated. The semiconductor memory device is characterized in that it is set to be writable. 2. The semiconductor memory device according to claim 1, wherein the pulse width of the write inhibit release signal is longer than the pulse width of the second write inhibit signal.