JP2525708B2 - Method for manufacturing thin film transistor - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor having a structure for reducing leak current.

[0002]

2. Description of the Related Art In recent years, active research has been conducted on forming a thin film transistor on an insulating substrate. This technology is expected to have many applications, such as an active matrix panel that realizes a thin display using an inexpensive insulating substrate, or a so-called three-dimensional integrated circuit that forms active elements such as transistors on a normal semiconductor integrated circuit. It is possible. Hereinafter, the case where the thin film transistor is applied to the active matrix panel will be described as an example, but the gist of the present invention can be applied to other cases using the thin film transistor in exactly the same manner. This is because the gist of the present invention is to improve the essential characteristic of the thin film transistor, which is to reduce the leakage current.

A liquid crystal display device in which a thin film transistor is applied to an active matrix panel is generally composed of an upper glass substrate, a lower thin film transistor substrate, and liquid crystal enclosed between them. An arbitrary character, figure, or image is displayed by selecting liquid crystal driving elements arranged in a matrix form in an external selection circuit and applying a voltage to the liquid crystal driving electrodes connected to the liquid crystal driving element. Is. A general circuit diagram of the thin film transistor substrate is shown in FIG.

FIG. 1A is a matrix layout view of liquid crystal driving elements on a thin film transistor substrate. A region surrounded by 1 in the drawing is a display region, and the liquid crystal driving elements 2 are arranged in a matrix in the display region. 3 is a data signal line to the liquid crystal drive element 2, and 4 is a liquid crystal drive element 2
Is a timing signal line to. FIG. 1B shows a circuit diagram of the liquid crystal driving element 2. A thin film transistor 5 switches data. Reference numeral 6 denotes a capacitor used for holding a data signal. Reference numeral 7 is a liquid crystal panel, 7-1 is a liquid crystal drive electrode formed corresponding to each liquid crystal drive element, and 7-2 is an upper glass panel.

[0005]

As can be seen from the above description, the thin film transistor is used for switching the data of the voltage applied to the liquid crystal, and the characteristics required of the thin film transistor at this time are largely classified into the following two types . Be divided.

(1) When the thin film transistor is turned on, a sufficient current can be passed to charge the capacitor.

(2) No current flows as much as possible when the thin film transistor is turned off.

(1) relates to the characteristics of writing data to the capacitor. Since the liquid crystal display is determined by the potential of the capacitor, the thin film transistor must be able to pass a sufficiently large current so that data can be written completely in a short time. The current at this time (hereinafter referred to as ON current) is determined by the capacity of the capacitor and the writing time, and the thin film transistor must be manufactured so that the ON current can be cleared. The ON current that the thin film transistor can flow is
It largely depends on the transistor size (channel length and channel width), structure, manufacturing process, gate voltage, and so on.
When a thin film transistor is formed using a polycrystalline semiconductor thin film, it is generally possible to obtain a sufficiently large ON current, and therefore the requirement (1) is satisfied. This is because, unlike an amorphous semiconductor, a polycrystalline semiconductor can obtain a considerably large carrier mobility.

(2) relates to the retention characteristic of the data written in the capacitor. In general, the written data must be retained for much longer than the write time. Capacitor capacitance is usually 1
Since the value is as small as PF, the thin film transistor is
If a leak current (hereinafter referred to as an OFF current) flows even in the FF state, the potential of the drain (that is, the potential of the capacitor) rapidly approaches the potential of the source, and the written data cannot be held correctly. When a thin film transistor is formed using a polycrystalline semiconductor thin film, many trap levels are localized at crystal grain boundaries in the polycrystalline semiconductor thin film, so a large amount of OFF current flows through this trap. . The mechanism of the OFF current will be described in detail later because it relates to the gist of the present invention.

As can be seen from the contents described above, in a thin film transistor using a polycrystalline semiconductor thin film, a relatively large ON current can be obtained, but an OFF current also becomes large, deteriorating the data retention characteristic. There is. Therefore, there is an urgent need to keep the OFF current small. The same can be said when the thin film transistor is applied to applications other than the active matrix panel. For example, when a normal logic circuit is formed by using thin film transistors, a quiescent current increases, and when a memory circuit is formed, it causes a malfunction.

[0011]

DISCLOSURE OF THE INVENTION The present invention eliminates such drawbacks of conventional thin film transistors, and an object of the present invention is to provide a method of manufacturing a thin film transistor having a structure for reducing OFF current. That is, the structure of the present invention is a polycrystalline semiconductor formed on a substrate.
Channel region formed in body thin film and the polycrystalline semiconductor thin film
The same conductivity that is formed at a distance from the channel region
Thin film transistor having a first region and a second region of a mold
In the manufacturing method of, at least the first and second regions
The polycrystalline semiconductor located between one side and the channel region
Impurities are introduced into the thin film, making it impure than the first and second regions
And has the same conductivity type as the first and second regions.
The method further comprises the step of forming a third region having

[0012]

EXAMPLES The mechanism of the OFF current will be described in detail below, and the contents of the present invention will be described based on it.

FIG. 2 is a sectional view showing a conventional general structure of an N-channel thin film transistor using a polycrystalline semiconductor thin film. 8 is an insulating transparent substrate such as glass or quartz, 9 is a polycrystalline semiconductor thin film such as polycrystalline silicon, 10 is a source region formed by doping the polycrystalline semiconductor thin film 9 with impurities such as phosphorus or arsenic, and 11 is Drain region, 12
Is a gate film, 13 is a gate electrode, 14 is an interlayer insulating film, 1
Reference numeral 5 is a source electrode, and 16 is a drain electrode. Typical characteristics of a thin film transistor having this structure are shown in FIG. This data is the result of the applicant's experiment. The horizontal axis of this graph is the gate voltage VGS with respect to the source, and the vertical axis is the drain current ID.

The drain voltage VDS with respect to the source is 4V. As can be seen from this graph, the drain current ID takes a minimum value in the vicinity of VGS = 0V, and the drain current ID increases as the absolute value of VGS increases. The increase in drain current in the region where VGS is positive means that the transistor is O
This means changing from the FF state to the ON state, and it is desirable that the rate of increase in current be as large as possible. On the other hand, an increase in drain current in the negative VGS region means that the OFF current has gate voltage dependence, which is not desirable as a transistor characteristic. This phenomenon is explained as follows.

In FIG. 2, when the gate electrode 13 is negatively biased, a P-type layer is formed on the surface of the polycrystalline semiconductor thin film 9. In the case of a metal oxide film semiconductor structure field effect transistor (MOS FET) used in a normal integrated circuit or the like, an almost perfect PN junction is formed between the P-type layer on the surface and the N-type regions of the source region and the drain region. Are formed, and extremely high resistance insulation separation is realized, so that almost no OFF current flows. However, in the case of a thin film transistor using a polycrystalline semiconductor thin film, since a high-density trap level exists at a crystal grain boundary in the polycrystalline semiconductor thin film, carriers move through this trap and an OFF current flows. . That is, a thin film transistor using a polycrystalline semiconductor essentially has a larger OFF current than a normal MOS FET. When the gate voltage VGS is negatively increased, the carrier concentration of the P-type layer formed on the surface of the polycrystalline semiconductor thin film is increased, and the width of the energy barrier of the PN junction formed between the P-type layer and the N-type region is narrowed. . For this reason, the concentration of the electric field is likely to occur, and therefore the OFF current increases. Since such an effect appears, the drain current ID becomes VGS =
When the minimum value is taken near 0V and VGS is increased to a negative value, the drain current increases.

The present invention reduces the gate voltage dependency of such OFF current, and even if VGS is increased to a negative value, OF
It is intended to provide a thin film transistor having a characteristic that the F current hardly increases. In order to realize this, in the present invention, in a thin film transistor provided with a source electrode, a drain electrode and a gate electrode using a polycrystalline semiconductor thin film,
An offset gate region formed of a low concentration region having the same conductivity type as the source region and the drain region is provided in contact with the source region under the source electrode or the drain region under the drain electrode. The present invention will be described below with reference to the drawings.

FIG. 4 shows an embodiment of the present invention.
3 illustrates a thin film transistor in which an offset gate region is provided in a source and drain region. Reference numeral 17 is an insulating transparent substrate, 18 is a polycrystalline semiconductor thin film, 19 is a source region formed in the polycrystalline semiconductor thin film 18, 20 is also a drain region, 21 is a gate film, 22 is a gate electrode, 23 is an interlayer insulating film, Reference numeral 24 is a source electrode, 25 is a drain electrode, and 26 is an offset gate region formed in the polycrystalline semiconductor thin film 18 and formed of a low concentration region of the same conductivity type as the source region 19 and the drain region 20. By providing the offset gate region in this way, even if the gate voltage is negatively biased and the P-type layer is formed on the surface of the polycrystalline semiconductor thin film, the impurity concentration of the offset gate region, which is the N-type region, is low. The energy barrier width of the junction becomes wider. Therefore, the electric field strength applied to the PN junction is weakened, and OF
F-current hardly increases.

FIG. 5 shows typical characteristics of the thin film transistor having the structure shown in FIG. 4, which is the result obtained by the applicant's experiments. The horizontal axis of this graph is the gate voltage VGS with respect to the source, and the vertical axis is the drain current ID. The drain voltage VDS for the source is 4V. Comparing with the characteristics of the conventional thin film transistor shown in FIG. 3, it can be seen that the characteristics are hardly changed in the positive VGS region, but the OFF current is significantly reduced in the negative VGS region. This is because, as described above, the present invention has a structure for relaxing the electric field concentration at the PN junction. The ON current similar to the conventional one is obtained despite the provision of the high resistance offset gate region, because the channel resistance of the thin film transistor is considerably larger than that of the normal MOSFET. That is, if the resistance of the offset gate region is sufficiently smaller than the channel resistance (about 100 KΩ or less), the ON current hardly decreases. OFF when the resistance of the offset gate region is further increased
It is possible to further reduce the current, while O
Since the N current also decreases, it is necessary to provide an offset gate region having an appropriate resistance value according to the purpose of use of the thin film transistor. This resistance value control can be easily realized by using the ion implantation method.

Finally, a method of manufacturing the thin film transistor of the embodiment of the present invention will be described. In the manufacturing method of the embodiment of the present invention, the gate film 2 is formed after forming the source region 19 and the drain region 20 in the polycrystalline semiconductor thin film 18 in FIG.
1. A method of forming a gate electrode 22 and providing an offset gate region by an ion implantation method using the gate electrode as a mask. According to this method, the offset gate region is formed in self-alignment with the gate electrode.
The process can be simplified and the parasitic capacitance between the offset gate region and the gate electrode can be reduced. Further, the source region 19 and the drain region 20 may be formed by introducing impurities from a contact hole opened in the interlayer insulating film 23. According to this method, a special pattern is not required when forming the source region and the drain region, so the process is further simplified. For gist of the present invention in that Ru is provided an offset gate region,
Of course, other manufacturing processes may be used as long as this structure can be obtained.

In the description of the present invention, the offset gate region is provided on both the source region side and the drain region side, but it may be provided on only one side in some cases. That is, in order to reduce the OFF current, it is only necessary to reduce the leakage at at least one place of the PN junction formed between the source region and the drain region. By doing so, the OFF current flowing between the source region and the drain region can be reduced. However, in order to reduce the OFF current more reliably, it is better to provide the offset gate regions on both the source region side and the drain region side.

[0021]

As described above, the manufacturing method of the present invention is
By using the thin film transistor, it is possible to provide a thin film transistor capable of significantly reducing the OFF current without substantially reducing the ON current.

[Brief description of drawings]

FIG. 1 is a general circuit diagram when a thin film transistor is applied to an active matrix panel.

FIG. 2 is a cross-sectional view showing a structure of a conventional thin film transistor.

FIG. 3 is a graph showing the characteristic.

FIG. 4 is a cross-sectional view showing the structure of the thin film transistor of the invention.

5 is a graph showing the characteristics of FIG.

Claims (1)

(57) [Claims] 1. A polycrystalline semiconductor thin film formed on a substrate.
The channel region formed and the polycrystalline semiconductor thin film
First regions of the same conductivity type that are formed with a gap between them
Method of manufacturing thin film transistor having region and second region
In at least one of the first and second regions and the channel region
Introducing impurities into the polycrystalline semiconductor thin film located between
However, the impurity concentration is lower than that of the first and second regions, and
Forming a third region having the same conductivity type as the first and second regions
Manufacturing a thin film transistor characterized by including
Build method.