JP2526494B2 - Insulation separation method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the production of insulating isolation regions in fine structures.

[0002]

2. Description of the Related Art Insulation and isolation technology for semiconductor microstructures is important for the integration of high speed transistors and new devices utilizing the quantum effect. Conventionally used fine structure insulation isolation techniques have been patterning using photoresist and removal of the conductive layer by etching. This method is suitable for manufacturing many devices at one time, but it requires many steps, and it is not easy to perform insulation separation with a width of about nanometer.
As an alternative to this method, there is ion milling in which focused high-energy ions are bombarded on a substrate to scrape atoms on the substrate surface. Since this method has no transfer step and is simple,
It is easy to perform insulation separation with a width of about nanometer. This method is described, for example, by Melungeiris in the Journal of Vacuum Science and
Technology ("Focusedion beamt"
technology and application
s ", John Melngailis, Journa
l of VacuumScience & Tech
nology B, Vol. 5, No. 2, pp. 46
9-495, 1987).

FIG. 2 is a process diagram of insulation separation by ion milling using conventional focused ions. (A) shows the substrate during ion irradiation and (B) shows the substrate after ion irradiation.
Is an insulating crystal substrate, 2 is a conductive layer, 3 is focused ions, 4 is a damaged region, and 5 is an insulating separation region.

Regarding this conventional method for producing a fine structure,
Semi-insulating GaAs on the substrate 1, n-GaAs on the conductive layer,
An explanation will be given using Ar ⁺ for the ion 3. High energy A
When the r ⁺ substrate is irradiated, Ar ⁺ ions are implanted into the GaAs substrate to form the damaged region 4, but Ga and As atoms on the substrate surface jump out of the substrate due to the impact. Therefore, a groove is selectively formed on the surface of the substrate irradiated with ions. When the depth of the groove is deeper than the conductive layer, the conductive layer is divided to form the insulating isolation region 5. Since the region of the groove is almost determined by the spread of the ions to be irradiated, it is easy to form a fine insulating separation region.

[0005]

In this method of insulation isolation by ion milling using focused ions, fine insulation isolation regions can be easily formed, but the periphery of the formed insulation isolation regions (grooves) is damaged. Since the region 4 remains, a deep level or the like is formed there, causing electrical instability of the conductive layer. In order to narrow the insulating isolation region and form fine elements with high density, it is desired to remove such a damaged region. The heat treatment after the ion irradiation recovers some damage, but it is not easy to remove the damage because the amount of ions implanted into the substrate is large.

An object of the present invention is to provide a method for easily forming a fine insulating isolation region with less substrate damage that causes electrical instability.

[0007]

SUMMARY OF THE INVENTION The method of dielectric isolation of the present invention is directed to a portion of a thin semiconductor layer on an insulative substrate that is capable of severing at least the bonds between crystalline constituent atoms and accelerating an amount that does not cause sputtering. It is characterized in that the ion is selectively implanted, and then heat treatment is performed to form a selective groove in the ion-implanted region to divide the semiconductor into layers.

According to this method, the substrate is less damaged and the fine insulating isolation region can be easily formed.

[0009]

Embodiment 1 The present invention will be described in detail below with reference to the drawings showing an embodiment. FIG. 1 is a process drawing showing an embodiment of the present invention. 1, the same symbols as those in FIG. 2 are equivalent to those in FIG. 2 and have the same functions. Further, (a) is a step during ion implantation, (b) is a step after ion implantation, and (c) is a step after heat treatment.

Regarding the method of processing a crystal substrate of the present invention, the substrate 1 is semi-insulating GaAs, and the conductive layer 2 is n-Ga.
A description will be given by taking Si ⁺ as an As and ion 3. First, n-G
The focused Si ⁺ ions 3 are implanted into the semi-insulating GaAs substrate 1 on which the aAs conductive layer 2 is formed. The ions that have been implanted into the substrate lose their energy due to collision with crystal atoms inside the substrate and stop. In this process, the bonds of the atoms forming the crystal are broken, so that the substrate becomes amorphous in the damaged region 4 in which the ions are implanted (FIG. 1B). Since the atoms in the amorphized region are broken, the volume thereof expands more than that of the crystalline region. Therefore, as shown in FIG. 1B, a raised area is formed on the damaged area 4. Of course, some of the substrate surface atoms jump out, but in the method of the present invention, the mass and energy of the ions to be implanted are large enough to penetrate deeply into the substrate, and the amount of ions to be implanted is much smaller than that of ion milling. The atoms that jump out to can be almost ignored. In this step, it is necessary to set the optimum ion implantation amount. If the amount of ions to be implanted is small as in the case of usual impurity doping, the crystal bonds cannot be sufficiently broken, so that it cannot be made amorphous. Further, when the amount of ions is too large to be used for ion milling, the method of the conventional example is used, and the surface is scraped off by sputtering, and many damage areas are left in the end. As described above, in the ion implantation step of the present invention, it is necessary to carefully set the amount of implanted ions to be in the middle thereof.

Next, when a heat treatment is performed at a temperature at which the crystallinity of the amorphized damaged region 4 is restored, the amorphized portion starts to crystallize again and the raised region decreases. go. Further, since the atom whose bond has been broken is easy to move and has high reactivity, the atom in the damaged region moves to its periphery, is evaporated, or is taken into the heat treatment atmosphere.

As a result, the number of atoms in the damaged area decreases,
A groove (insulating region 5) reaching the insulating substrate is formed therein (FIG. 1C). By this heat treatment, most of the amorphized region disappears, and the damaged region containing crystal defects is also annealed to improve the crystallinity. Therefore, there is no damaged region under or around the insulating region 5 and no electrical instability occurs.

[0013] The semi-insulating GaAs substrate to 100nm diameter forming the n-GaAs layer having a thickness of 20 nm Si ⁺ focused ion beam acceleration voltage 260 keV, linear density 10 ^{1 0} c
When injected linearly at m ⁻¹ , the surface of the injected region was raised by 20 nm. Subsequently, when this substrate was heat-treated at 650 ° C. for 15 minutes while flowing arsine gas, a wedge-shaped groove having a width of 200 nm and a depth of 25 nm was formed, and the n-GaAs layer could be isolated.

Also, when Au ⁺ ions were used instead of Si ⁺ ions, the same thing occurred, although there were some differences. An Au ⁺ focused ion beam having a diameter of 100 nm was applied to a semi-insulating GaAs substrate having a 15 nm thick n-GaAs layer formed thereon at an acceleration voltage of 260 keV and a linear density of 3 × 10 ¹⁹ xcm.
^{When the} line was injected at ^-1 , the surface of the injected region was raised by 3 nm. Subsequently, when this substrate was heat-treated at 650 ° C. for 15 minutes while flowing arsine gas, a wedge-shaped groove having a width of 200 nm and a depth of 20 nm was formed, and the n-GaAs layer was isolated.

In order to form a groove having such a depth by the conventional ion milling method, 10 ⁶ times as many ions as the ion implantation amount used in the present invention are required, which requires a long implantation time. A lot of damage will remain on the substrate surface.

In the above-mentioned embodiments of the present invention, only the formation of the insulating isolation region having a depth of about 25 nm has been shown. However, by selecting the mass, acceleration energy and distribution of implanted ions,
The depth and shape of the groove can be adjusted. The depth and shape of the groove can also be adjusted by adjusting the heat treatment temperature and time.

Although only single crystal GaAs is shown as the substrate, it is obvious that the present invention can be applied to other semiconductor single crystal substrates such as Si, Ge, InP, GaSb and polycrystalline substrates. It is also clear that it can be applied to an insulating single crystal substrate or a polycrystalline substrate. In addition, SOI (Se
microphone on insulator)
The present invention can also be applied to insulation separation when a single crystal or a semiconductor film similar thereto is formed on a substrate or film which is not crystalline as described above. In the above-mentioned embodiment, the semi-insulating Ga is used.
After forming an n-GaAs layer on the As substrate, this n-
The GaAs layer was divided, but i-Ga instead of n-GaAs
After forming the As layer and dividing it, n is formed by ion implantation or the like.
A type impurity may be doped.

Although only Si ⁺ and Au ⁺ are shown as the ions to be implanted, it is also clear that other ions such as Ga ⁺ , As ⁺ , Sb ⁺ may be used.

Further, although only arsine gas was shown as the atmosphere for the heat treatment, it is also clear that other gas may be used, and pressurization, depressurization, and vacuum may be performed.

In the present invention, it is desirable to use a focused ion beam for facilitating the fine structure manufacturing process. However, when processing a large area at a time, a spread ion beam is used and placed on the substrate surface. It is also apparent that the ions may be selectively implanted through the mask.

[0021]

According to the method of insulation separation of the present invention, fine insulation separation regions can be formed, and fine semiconductor elements can be formed at high density.

[Brief description of drawings]

FIG. 1 is a process drawing showing an example of the present invention. (A) shows during ion implantation, (b) shows after ion implantation, and (c) shows after heat treatment.

FIG. 2 is a process drawing of insulation separation by conventional ion milling. (A) shows during ion irradiation and (B) shows after ion irradiation.

[Explanation of symbols]

 1 Insulating Crystal Substrate 2 Conductive Layer 3 Ion 4 Substrate Damage Area 5 Insulation Separation Area

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 21/265 Q

Claims (1)

(57) [Claims] 1. A part of a thin semiconductor layer on an insulating substrate is selectively implanted with accelerated ions in an amount that does not cause a bond between crystal constituent atoms and does not cause sputtering, and is then subjected to heat treatment. A method in which a groove is selectively formed in an ion-implanted region and the semiconductor layer is divided to perform insulation separation.