JP2526497B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a low resistance ohmic electrode and operating at high speed in the microwave and millimeter wavelength regions.

[0002]

BACKGROUND OF THE INVENTION While non-alloy ohmic electrode is a metal-semiconductor interface is Schottky contact, the shot
The structure shows that the key barrier has a low height or a small thickness, so that electrical conduction is obtained with the channel by the tunnel effect and thermionic emission. When the gate electrode is formed on the gate contact layer made of a semiconductor having a band gap larger than that of the cap layer and an electron affinity smaller than that of the cap layer, in order to improve tunneling efficiency, the gate electrode of the semiconductor layer is higher than the gate electrode forming position on the surface side. the first cap layer that comprises a layer which is doped provided, the ohmic electrode is an example that is formed on the second capping layer formed on the semiconductor layer surface.

Such a structure has InAl on the InP substrate.
An example applied to an As / InGaAs HEMT is, for example, an IEE electron device.
Letters, Vol. 1, No. 11, pp. 502-504 (IE
EE ELECTRON DEVICE LETTER
S, VOL. 1, NO. 11, P.I. 502-504, 1
990 ) by Enoki et al. (T. Enoki et a.
l. ). The block diagram and the band diagram are shown in FIGS. 5 and 6, respectively. Here, an InGaAs layer is used as the second cap layer and an InAlAs layer is used as the first cap layer. In this report, AuGe / Ni is used in a non-alloy state as an electrode metal, and a contact resistance of an ohmic electrode is 0.14Ω.
・ Mm is obtained. In such a structure, although the ohmic electrode is in Schottky contact with the cap layer, since the barrier of the gate contact layer is thin, tunnel efficiency is improved, and an ohmic electrode having low source resistance and low drain resistance can be manufactured.

[0004]

THE INVENTION Problems to be Solved] In non-alloy ohmic electrode structure according to a two-layer cap employed with a high concentration InAlAs layer described in the prior art, In the Schottky interface
The In composition of the GaAs cap layer is set to 53%, which is the ratio of lattice matching with InP which is the substrate. Device performance improves with improvement in source resistance and drain resistance. Therefore, a heterojunction electrode formed on the InP substrate
In order to further improve the device performance of field effect transistors, it is desired to develop ohmic electrodes with lower resistance.

[0005]

In a non-alloy type ohmic electrode characterized in that a highly doped portion is provided on the surface side of an ohmic electrode forming layer, a semiconductor layer in contact with an ohmic metal is further provided with a high indium composition. Therefore, it is considered that tunnel efficiency can be increased and low resistance can be achieved.

The present invention is intended to develop a semiconductor device having an ohmic electrode having a resistance lower than that of the ohmic structure shown in the conventional example by the method described above. In this semiconductor device, at least a buffer layer, a channel layer, a gate contact layer, a first cap layer, and a second cap layer are laminated in this order on an InP substrate.
A gate electrode is formed on the gate contact layer, and an ohmic electrode is formed on the second cap layer.
In the heterojunction field effect transistor in which the second cap layer is impurity-doped, the composition of indium in the second cap layer is set to a value larger than 0.53.
It is characterized in that at least one InGaAs layer is present.

[0007]

The cap InGaAs layer according to the present invention has at least one portion where the indium composition is set to a value larger than 53%, so that the height of the Schottky barrier can be reduced from the conventional one. It is intended provided <br/> to be smaller than the value. Further, when used in combination with the cap layer having a high In composition mentioned ohmic co <br/> Ntakuto layer such as the highly-doped portions on the surface side of the gate electrode located previously existing Schottky barrier for the channel The height can be effectively reduced, and a low resistance ohmic electrode can be formed.

[0008]

Embodiments of the present invention will be described in detail with reference to the drawings. Here, a field effect transistor will be described as an example.

(Embodiment 1) FIG. 1 is a sectional view showing a principal part of an example of the structure of a semiconductor device of the present invention. FIG. 2 is the band diagram.

Non-doped I on the semi-insulating InP substrate 11
The n _0.52 Al _0.48 As layer 12 has a thickness of, for example, 800 nm, and the non-doped In _0.53 Ga _0.47 As layer 13 has, for example, 4 nm.
Non-doped In _0.52 Al _0.48 As layer 1 with a thickness of 0 nm
4 has a thickness of, for example, 3 nm, and the In _0.52 Al _0.48 As electron supply layer 15 doped with n-type Si at a concentration of, for example, 2 × 10 ¹⁸ cm ⁻³ has a thickness of, for example, 30 nm, and is not doped I
n _0.52 Al _0.48 As gate contact layer 16 is, for example, 2
With a thickness of 0 nm, for example, 5 × 10 ¹⁸ cm ⁻³ of n-type Si
In doped In _0.52 Al _0.48 As cap layer 17, for example, 20nm thick, for example, a concentration of 5 × 10 ¹⁸ cm ^-3 is Si doped n-type In _0.7 Ga _0.3 As cap
In flop layer 18, for example, 10nm thick are successively grown respectively, and the source electrode 19 and drain electrode 20 is thus formed on the deposition <br/> of Ti and Pt and Au on the n-type InGaAs cap layer, The Schottky gate electrode 2 made of, for example, Ti, Pt, and Au is formed inside the recess region that is etched and removed halfway through the non-doped InAlAs gate contact layer 16 between the ohmic electrodes.
1 is formed .

In the field effect transistor of this embodiment, the non-doped In _0.53 Ga _0.47 As layer 13 corresponds to the channel layer, and the highly-doped In _0.52 Al _0.48 As layer.
17 and the highly doped In _0.7 Ga _0.3 As layer 18
It corresponds to the cap layer. The ohmic electrode has good ohmic property without heat treatment like normal alloy ohmic, and has a contact resistance of 0.12Ω · mm.
Is obtained. When the In composition of the cap InGaAs layer 18 is 53%, the same evaluation results show that the contact resistance is 0.17 Ω · mm, which is 0.0 compared to the previous result.
A difference of 5 Ω · mm was shown.

(Embodiment 2) FIG. 3 is a sectional view showing the principal part of another example of the structure of the semiconductor device of the present invention. FIG. 4 is the band diagram.

Non-doped I on the semi-insulating InP substrate 11
_{n 0. 2 5 Al 0.} 4 8 As layer 12 is for example 800nm
In thickness, doped In _0. In _{5 3} Ga _{0. 4 7} As layer 13, for example, 40nm thick, doped In
_{.. 0 5 2 Al 0 4} 8 As layer 14 by, for example, 3nm thick, for example, _{^{2 × 10 1 8 cm -.}} . In 0 which is Si-doped n-type to a ^third concentration _{5 2} Al _{0 4 8} As Electron supply layer 1
5, for example, 30nm thick, undoped an In _{0. 5 2}
Al _{0. 4 8} As gate contact layer 16 is for example 20
nm thickness, for example, at a concentration of 5 × 10 ¹⁸ cm ⁻³
In ₀ which is Si-doped to the _mold. In _{5 2} Al _{0. 4 8} As the thickness of the cap layer 17 is for example 20 nm, for example, 5 × 1
In doped with n-type Si at a concentration of 0 ¹⁸ cm ^-3
_{.. 0 5 3 Ga 0 47} As a cap layer 22 (a), for example, 10nm thick, for example, _{^{5 × 10 1 8 cm -.}} . In 0 which is Si-doped n-type to a ^third concentration ₇ Ga _{0 3} As
The cap layer 22 (b) is, for example, 10 nm thick and is sequentially crystal-grown, and the source electrode 19 and the drain electrode 20 are formed on the n-type InGaAs cap layer 22 (b).
Is formed by vapor deposition of Ti, Pt, and Au, and a Schottky gate composed of, for example, Ti, Pt, and Au is formed inside the recess region which is etched and removed halfway through the non-doped InAlAs gate contact layer 16 between the ohmic electrodes. The electrode 21 is formed.

[0014] In the field effect transistor of this embodiment, the undoped _{In 0. 5 3 Ga 0.} 4 7 As layer 1
3 corresponds to the channel layer, the high-doped In _{0. 5 2} A
l _{0. 4 8} As layer 17 and the high-doped In _{0. 5 3} G
a _{0. 4 7} As layer 22 (a) and the high-doped In
_{0. 7} Ga _{0. 3} As layer 22 (b) correspond to the cap layer. Ohmic electrodes have good ohmic properties without heat treatment like ordinary alloy ohmic,
A contact resistance of 0.13 Ω · mm is obtained.

InGaAs layer 18 used for the cap
Although the In composition of is set to 0.7 in this embodiment, the present invention does not limit this In composition ratio to this value, and it is within the range where misfit transition does not occur as a strained layer. In addition, the In composition ratio can be further increased. Further, the In composition ratio in the cap InGaAs layer does not have to be uniform, and if at least one portion having a large In composition exists in the layer, the conduction band of the cap InGaAs layer has a uniform In composition of 53%. Although it is smaller than the case where it is set, it is small, so the effect of reducing ohmic resistance can be confirmed.

[0016]

As described above, a low resistance ohmic electrode can be formed by providing an InGaAs layer having a high In content of more than 53% in the ohmic electrode forming layer in the non-alloiomic state. This is reflected in the improvement of the high frequency operation in the device, and realizes the improvement of the device characteristics such as the cutoff frequency, the noise characteristic, and the high output characteristic.

[Brief description of drawings]

FIG. 1 is a diagram illustrating a semiconductor device of the present invention.

FIG. 2 is a diagram showing a band diagram of the semiconductor device of FIG.

FIG. 3 is a diagram illustrating a semiconductor device of the present invention.

4 is a diagram showing a band diagram of the semiconductor device of FIG.

FIG. 5 is a diagram illustrating a conventional semiconductor device.

FIG. 6 is a diagram showing a band diagram of a conventional semiconductor device.

[Explanation of symbols]

11 InP substrate 12 doped _{In 0. 5 2 Al 0.} 4 7 As layer 13 doped _{In 0. 5 3 Ga 0.} 4 7 As layer 14 doped _{In 0. 5 2 Al 0.} 4 7 As layer 15 Si doped In _{0 . 5 2 Al 0. 4 7} As layer 16 doped _{In 0. 5 2 Al 0.} 4 7 As layer 17 Si doped _{In 0. 5 2 Al 0.} 4 7 As layer 18 Si doped In _{0. 7} Ga _{0. 3} As layer 19 source electrode 20 drain electrode 21 gate electrode 22 (a) Si-doped _{In 0. 5 3 Ga 0.} 4 7 As
Layer 22 (b) Si-doped _{In 0. 7 Ga 0. 7} As layer 23 Si doped _{In 0. 5 3 Ga 0.} 4 7 Layer

Continuation of front page (56) References JP-A-4-369842 (JP, A) JP-A-5-166843 (JP, A) IEEE ELECTRON DEV ICE LETTERS, VOL. 11, NO. 11, NOVERBER1990PP. 502-504

Claims (2)

(57) [Claims] 1. An InP substrate and at least a buffer layer,
A channel layer, a gate contact layer, a first cap layer, and a second cap layer are sequentially stacked , a gate electrode is formed on the gate contact layer, and an ohmic electrode is formed on the second cap layer. A heterojunction field effect transistor formed by doping the second cap layer with impurities, wherein the composition of indium in the second cap layer is set to a value greater than 0.53.
A semiconductor device having at least one s layer . 2. The second cap layer has a composition of indium.
0.53 InGaAs layer and I greater than 0.53
A contract characterized by comprising a laminated structure with an nGaAs layer
The semiconductor device according to claim 1.